stm32h7 SDMMC support IDMA, Interrupt driven, pullups and SDIO
* stm32h7:Supports ARMV7M Stack check * stm32h7:sdmmc bug fix writting address 0 * stm32h7:sdmmc Clean up timming * stm32f7:Kconfig typos, formating * stm32f7:sdmmc use binary not * stm32f7:nxstyle formatting * stm32h7:SDMMC Kconfig add Block Setup, Preflight, Delayed Invalidate * stm32h7:Correct value of ICR reset * stm32h7:SDMMC support IDMA, Interrupt driven, pullups and SDIO * stm32h7:Add AXI * stm32h7:Workaround for Errata 2.2.9 Reading from AXI SRAM may lead to data read corruption
This commit is contained in:
David Sidrane
Gregory Nutt
parent
9eba6bf018
commit
c6689b3093
@ -347,7 +347,7 @@ config ARCH_CHIP_STM32H7
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# select ARCH_HAVE_HEAPCHECK
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select ARCH_HAVE_SPI_BITORDER
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select ARM_HAVE_MPU_UNIFIED
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# select ARMV7M_HAVE_STACKCHECK
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select ARMV7M_HAVE_STACKCHECK
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---help---
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STMicro STM32H7 architectures (ARM Cortex-M7).
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@ -2329,7 +2329,7 @@ config STM32F7_SDMMC2_DMAPRIO
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hex "SDMMC2 DMA priority"
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default 0x00010000
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---help---
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Select SDMMC1 DMA prority.
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Select SDMMC2 DMA prority.
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Options are: 0x00000000 low, 0x00010000 medium,
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0x00020000 high, 0x00030000 very high. Default: medium.
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@ -3,7 +3,7 @@
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*
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* Copyright (C) 2009, 2011-2018,2019 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david.sidrane@nscdg.com>
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* David Sidrane <david.sidrane @nscdg.com>
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* Bob Feretich <bob.feretich@rafresearch.com>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -75,6 +75,7 @@
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****************************************************************************/
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/* Configuration ************************************************************/
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/* Required system configuration options:
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*
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* CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem
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@ -88,8 +89,8 @@
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* CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking
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* APIs to manage concurrent accesses on the SDMMC bus. This is not
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* needed for the simple case of a single SD card, for example.
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* CONFIG_STM32F7_SDMMC_DMA - Enable SDMMC. This is a marginally optional. For
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* most usages, SDMMC will cause data overruns if used without DMA.
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* CONFIG_STM32F7_SDMMC_DMA - Enable SDMMC. This is a marginally optional.
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* For most usages, SDMMC will cause data overruns if used without DMA.
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* NOTE the above system DMA configuration options.
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* CONFIG_SDMMC1/2_WIDTH_D1_ONLY - This may be selected to force the driver
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* operate with only a single data line (the default is to use all
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@ -185,8 +186,9 @@
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#endif
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/* Mode dependent settings. These depend on clock divisor settings that must
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* be defined in the board-specific board.h header file: STM32_SDMMC_INIT_CLKDIV,
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* STM32_SDMMC_MMCXFR_CLKDIV, and STM32_SDMMC_SDXFR_CLKDIV.
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* be defined in the board-specific board.h header file:
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* STM32_SDMMC_INIT_CLKDIV, STM32_SDMMC_MMCXFR_CLKDIV, and
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* STM32_SDMMC_SDXFR_CLKDIV.
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*/
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#define STM32_CLCKCR_INIT (STM32_SDMMC_INIT_CLKDIV | \
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@ -230,7 +232,6 @@
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* - Memory burst size (F4 only)
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*/
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/* STM32 stream configuration register (SCR) settings base settings sans
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* priority.
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*/
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@ -252,7 +253,6 @@
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# define SDMMC1_DMACHAN DMAMAP_SDMMC1
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#endif
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#ifdef DMAMAP_SDMMC2
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/* SDMMC DMA Channel/Stream selection. There
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@ -337,7 +337,6 @@
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/* Let's wait until we have both SDIO transfer complete and DMA complete. */
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#define SDMMC_XFRDONE_FLAG (1)
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#define SDMMC_DMADONE_FLAG (2)
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#define SDMMC_ALLDONE (3)
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@ -371,6 +370,7 @@ struct stm32_dev_s
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struct sdio_dev_s dev; /* Standard, base SDIO interface */
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/* STM32-specific extensions */
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uint32_t base;
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int nirq;
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#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE
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@ -748,7 +748,7 @@ static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES];
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* Name: sdmmc_putreg32
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****************************************************************************/
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static inline void sdmmc_putreg32(struct stm32_dev_s *priv, uint32_t value,\
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static inline void sdmmc_putreg32(struct stm32_dev_s *priv, uint32_t value,
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int offset)
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{
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putreg32(value, priv->base + offset);
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@ -896,7 +896,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask,
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{
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/* Do not use this in STM32_SDMMC_MASK register */
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waitmask &= !SDIOWAIT_WRCOMPLETE;
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waitmask &= ~SDIOWAIT_WRCOMPLETE;
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pinset = priv->d0_gpio & (GPIO_PORT_MASK | GPIO_PIN_MASK);
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pinset |= (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI);
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@ -933,7 +933,8 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask,
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else
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#endif
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{
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sdmmc_putreg32(priv, priv->xfrmask | priv->waitmask, STM32_SDMMC_MASK_OFFSET);
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sdmmc_putreg32(priv, priv->xfrmask | priv->waitmask,
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STM32_SDMMC_MASK_OFFSET);
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}
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leave_critical_section(flags);
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@ -1039,7 +1040,8 @@ static inline uint32_t stm32_getpwrctrl(struct stm32_dev_s *priv)
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#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG
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static void stm32_sampleinit(void)
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{
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memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * sizeof(struct stm32_sampleregs_s));
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memset(g_sampleregs, 0xff, DEBUG_NSAMPLES *
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sizeof(struct stm32_sampleregs_s));
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}
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#endif
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@ -1149,22 +1151,26 @@ static void stm32_dumpsample(struct stm32_dev_s *priv,
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#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG
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static void stm32_dumpsamples(struct stm32_dev_s *priv)
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{
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stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup");
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stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP],
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"Before setup");
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#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA)
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if (priv->dmamode)
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{
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stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE], "Before DMA enable");
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stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_ENABLE],
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"Before DMA enable");
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}
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#endif
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stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_AFTER_SETUP], "After setup");
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stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER], "End of transfer");
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stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_END_TRANSFER],
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"End of transfer");
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#if defined(CONFIG_DEBUG_DMA_INFO) && defined(CONFIG_STM32F7_SDMMC_DMA)
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if (priv->dmamode)
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{
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stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK], "DMA Callback");
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stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_DMA_CALLBACK],
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"DMA Callback");
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}
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#endif
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}
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@ -1312,6 +1318,7 @@ static void stm32_datadisable(struct stm32_dev_s *priv)
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/* Disable the data path */
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/* Reset DTIMER */
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sdmmc_putreg32(priv, SDMMC_DTIMER_DATATIMEOUT, STM32_SDMMC_DTIMER_OFFSET);
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sdmmc_putreg32(priv, 0, STM32_SDMMC_DLEN_OFFSET); /* Reset DLEN */
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@ -1349,7 +1356,8 @@ static void stm32_sendfifo(struct stm32_dev_s *priv)
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/* Loop while there is more data to be sent and the RX FIFO is not full */
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while (priv->remaining > 0 &&
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(sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET) & STM32_SDMMC_STA_TXFIFOF) == 0)
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(sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET) &
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STM32_SDMMC_STA_TXFIFOF) == 0)
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{
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/* Is there a full word remaining in the user buffer? */
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@ -1413,7 +1421,8 @@ static void stm32_recvfifo(struct stm32_dev_s *priv)
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*/
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while (priv->remaining > 0 &&
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(sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET) & STM32_SDMMC_STA_RXDAVL) != 0)
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(sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET) &
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STM32_SDMMC_STA_RXDAVL) != 0)
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{
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/* Read the next word from the RX FIFO */
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@ -1637,12 +1646,12 @@ static int stm32_sdmmc_rdyinterrupt(int irq, void *context, void *arg)
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static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
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{
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struct stm32_dev_s *priv =(struct stm32_dev_s *)arg;
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uint32_t enabled;
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uint32_t pending;
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#ifdef HAVE_SDMMC_SDIO_MODE
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uint32_t mask;
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#endif
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struct stm32_dev_s *priv = (struct stm32_dev_s *) arg;
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DEBUGASSERT(priv != NULL);
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@ -1676,9 +1685,9 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
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stm32_recvfifo(priv);
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}
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/* Otherwise, Is the transmit FIFO half empty or less? If so we must
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* be processing a send transaction. NOTE: We can't be processing
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* both!
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/* Otherwise, Is the transmit FIFO half empty or less? If so we
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* must be processing a send transaction. NOTE: We can't be
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* processing both!
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*/
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else if ((pending & STM32_SDMMC_STA_TXFIFOHE) != 0)
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@ -1772,7 +1781,8 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
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{
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/* Terminate the transfer with an error */
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mcerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining);
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mcerr("ERROR: TX FIFO underrun, remaining: %d\n",
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priv->remaining);
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stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
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}
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@ -1803,7 +1813,8 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
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/* Yes.. wake the thread up */
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sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR |
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STM32_SDMMC_CMDDONE_ICR, STM32_SDMMC_ICR_OFFSET);
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STM32_SDMMC_CMDDONE_ICR,
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STM32_SDMMC_ICR_OFFSET);
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stm32_endwait(priv, SDIOWAIT_RESPONSEDONE);
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}
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}
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@ -2117,7 +2128,6 @@ static int stm32_attach(FAR struct sdio_dev_s *dev)
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ret = irq_attach(priv->nirq, stm32_sdmmc_interrupt, priv);
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if (ret == OK)
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{
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/* Disable all interrupts at the SDIO controller and clear static
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* interrupt flags
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*/
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@ -2255,7 +2265,7 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
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size_t nbytes)
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{
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struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
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uint32_t dblocksize;
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uint32_t dblksize;
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DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0);
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DEBUGASSERT(((uint32_t)buffer & 3) == 0);
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@ -2276,9 +2286,9 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
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/* Then set up the SDIO data path */
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dblocksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
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dblksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
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stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT * ((nbytes + 511) >> 9),
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nbytes, dblocksize | STM32_SDMMC_DCTRL_DTDIR);
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nbytes, dblksize | STM32_SDMMC_DCTRL_DTDIR);
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/* And enable interrupts */
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@ -2310,7 +2320,7 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const
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uint8_t *buffer, size_t nbytes)
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{
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struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
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uint32_t dblocksize;
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uint32_t dblksize;
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DEBUGASSERT(priv != NULL && buffer != NULL && nbytes > 0);
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DEBUGASSERT(((uint32_t)buffer & 3) == 0);
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@ -2331,9 +2341,9 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const
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/* Then set up the SDIO data path */
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dblocksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
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dblksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
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stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT * ((nbytes + 511) >> 9),
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nbytes, dblocksize);
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nbytes, dblksize);
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/* Enable TX interrupts */
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@ -2436,7 +2446,6 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
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timeout = SDMMC_LONGTIMEOUT;
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break;
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case MMCSD_R3_RESPONSE:
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case MMCSD_R7_RESPONSE:
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events = STM32_SDMMC_RESPDONE_STA;
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@ -2518,7 +2527,6 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
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* 0 1 End bit
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*/
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#ifdef CONFIG_DEBUG_FEATURES
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if (!rshort)
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{
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@ -2632,7 +2640,8 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
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return ret;
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}
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static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort)
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static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd,
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uint32_t *rshort)
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{
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struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
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uint32_t regval;
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@ -3009,21 +3018,22 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
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size_t buflen)
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{
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struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
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uint32_t dblocksize;
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uint32_t dblksize;
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DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
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#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT
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DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0);
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#else
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# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
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# if defined(CONFIG_ARMV7M_DCACHE) && \
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!defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
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/* buffer alignment is required for DMA transfers with dcache in buffered
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* mode (not write-through) because the up_invalidate_dcache could lose
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* buffered buffered writes if the buffer alignment and sizes are not on
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* ARMV7M_DCACHE_LINESIZE boundaries.
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*/
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if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE-1)) != 0 ||
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(buflen & (ARMV7M_DCACHE_LINESIZE-1)) != 0)
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if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE - 1)) != 0 ||
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(buflen & (ARMV7M_DCACHE_LINESIZE - 1)) != 0)
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{
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return -EFAULT;
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}
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@ -3048,9 +3058,9 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
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/* Then set up the SDIO data path */
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dblocksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
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dblksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
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stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT * ((buflen + 511) >> 9),
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buflen, dblocksize | STM32_SDMMC_DCTRL_DTDIR);
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buflen, dblksize | STM32_SDMMC_DCTRL_DTDIR);
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/* Configure the RX DMA */
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@ -3066,7 +3076,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer,
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if ((uintptr_t)buffer < DTCM_START || (uintptr_t)buffer + buflen > DTCM_END)
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{
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#if !defined(CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT)
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up_invalidate_dcache((uintptr_t)buffer,(uintptr_t)buffer + buflen);
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up_invalidate_dcache((uintptr_t)buffer, (uintptr_t)buffer + buflen);
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#endif
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}
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@ -3104,21 +3114,22 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
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FAR const uint8_t *buffer, size_t buflen)
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{
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struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
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uint32_t dblocksize;
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uint32_t dblksize;
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DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
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#ifdef CONFIG_ARCH_HAVE_SDIO_PREFLIGHT
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DEBUGASSERT(stm32_dmapreflight(dev, buffer, buflen) == 0);
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#else
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# if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
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# if defined(CONFIG_ARMV7M_DCACHE) && \
|
||||
!defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
|
||||
/* buffer alignment is required for DMA transfers with dcache in buffered
|
||||
* mode (not write-through) because the up_flush_dcache would corrupt adjacent
|
||||
* memory if the buffer alignment and sizes are not on ARMV7M_DCACHE_LINESIZE
|
||||
* boundaries.
|
||||
* mode (not write-through) because the up_flush_dcache would corrupt
|
||||
* adjacent memory if the buffer alignment and sizes are not on
|
||||
* ARMV7M_DCACHE_LINESIZE boundaries.
|
||||
*/
|
||||
|
||||
if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE-1)) != 0 ||
|
||||
(buflen & (ARMV7M_DCACHE_LINESIZE-1)) != 0)
|
||||
if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE - 1)) != 0 ||
|
||||
(buflen & (ARMV7M_DCACHE_LINESIZE - 1)) != 0)
|
||||
{
|
||||
return -EFAULT;
|
||||
}
|
||||
@ -3153,14 +3164,15 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev,
|
||||
|
||||
/* Then set up the SDIO data path */
|
||||
|
||||
dblocksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
|
||||
dblksize = stm32_log2(priv->blocksize) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT;
|
||||
stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT * ((buflen + 511) >> 9),
|
||||
buflen, dblocksize);
|
||||
buflen, dblksize);
|
||||
|
||||
/* Configure the TX DMA */
|
||||
|
||||
stm32_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, (uint32_t)buffer,
|
||||
(buflen + 3) >> 2, SDMMC_TXDMA32_CONFIG | priv->dmapri);
|
||||
stm32_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET,
|
||||
(uint32_t)buffer, (buflen + 3) >> 2,
|
||||
SDMMC_TXDMA32_CONFIG | priv->dmapri);
|
||||
|
||||
sdmmc_modifyreg32(priv, STM32_SDMMC_DCTRL_OFFSET, 0, STM32_SDMMC_DCTRL_DMAEN);
|
||||
stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE);
|
||||
@ -3286,7 +3298,8 @@ static void stm32_callback(void *arg)
|
||||
/* Yes.. queue it */
|
||||
|
||||
mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg);
|
||||
(void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0);
|
||||
(void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback,
|
||||
priv->cbarg, 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -3424,6 +3437,7 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno)
|
||||
}
|
||||
|
||||
/* Initialize the SDIO slot structure */
|
||||
|
||||
/* Initialize semaphores */
|
||||
|
||||
nxsem_init(&priv->waitsem, 0, 0);
|
||||
@ -3542,7 +3556,6 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
|
||||
}
|
||||
#endif /* CONFIG_STM32F7_SDMMC1 || CONFIG_STM32F7_SDMMC2 */
|
||||
|
||||
|
||||
#ifdef HAVE_SDMMC_SDIO_MODE
|
||||
void sdio_set_sdio_card_isr(FAR struct sdio_dev_s *dev,
|
||||
int (*func)(void *), void *arg)
|
||||
@ -3561,6 +3574,7 @@ void sdio_set_sdio_card_isr(FAR struct sdio_dev_s *dev,
|
||||
priv->sdiointmask = 0;
|
||||
}
|
||||
|
||||
sdmmc_putreg32(priv, priv->xfrmask | priv->waitmask | priv->sdiointmask, STM32_SDMMC_MASK_OFFSET);
|
||||
sdmmc_putreg32(priv, priv->xfrmask | priv->waitmask | priv->sdiointmask,
|
||||
STM32_SDMMC_MASK_OFFSET);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -27,6 +27,7 @@ config STM32H7_STM32H7X3XX
|
||||
default n
|
||||
select ARCH_HAVE_FPU
|
||||
select ARCH_HAVE_DPFPU
|
||||
select ARCH_HAVE_SDIO_DELAYED_INVLDT
|
||||
select ARMV7M_HAVE_ICACHE
|
||||
select ARMV7M_HAVE_DCACHE
|
||||
select ARMV7M_HAVE_ITCM
|
||||
@ -74,6 +75,22 @@ config STM32H7_FLASH_OVERRIDE_I
|
||||
|
||||
endchoice # "Override Flash Size Designator"
|
||||
|
||||
config STM32H7_AXI_SRAM_CORRUPTION_WAR
|
||||
bool "Errata 2.2.9 Reading from AXI SRAM data read corruption Workaround"
|
||||
default y
|
||||
---help---
|
||||
Enable workaround for Reading from AXI SRAM may lead to data read
|
||||
corruption. See ES0392 Rev 6.
|
||||
|
||||
Read data may be corrupted when the following conditions are met:
|
||||
- Several read transactions are performed to the AXI SRAM,
|
||||
- and a master delays its data acceptance while a new transfer is
|
||||
requested
|
||||
|
||||
This workaround will set the READ_ISS_OVERRIDE bit in the
|
||||
AXI_TARG7_FN_MOD register. This will reduce the read issuing capability
|
||||
of the SRAM to 1 at AXI interconnect level and avoid data corruption.
|
||||
|
||||
menu "STM32H7 Peripheral Selection"
|
||||
|
||||
# These "hidden" settings determine is a peripheral option is available for the
|
||||
@ -245,6 +262,8 @@ config STM32H7_SDMMC1
|
||||
select STM32H7_SDMMC
|
||||
select ARCH_HAVE_SDIO
|
||||
select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
|
||||
select ARCH_HAVE_SDIO_PREFLIGHT
|
||||
select SDIO_BLOCKSETUP
|
||||
|
||||
config STM32H7_SDMMC2
|
||||
bool "SDMMC2"
|
||||
@ -252,6 +271,8 @@ config STM32H7_SDMMC2
|
||||
select STM32H7_SDMMC
|
||||
select ARCH_HAVE_SDIO
|
||||
select ARCH_HAVE_SDIOWAIT_WRCOMPLETE
|
||||
select ARCH_HAVE_SDIO_PREFLIGHT
|
||||
select SDIO_BLOCKSETUP
|
||||
|
||||
menu "STM32H7 I2C Selection"
|
||||
|
||||
@ -919,8 +940,7 @@ config STM32H7_SDMMC_XFRDEBUG
|
||||
config STM32H7_SDMMC_IDMA
|
||||
bool "Support IDMA data transfers"
|
||||
default y
|
||||
select STM32H7_SDMMC_DMA
|
||||
depends on STM32H7_DMA
|
||||
select SDIO_DMA
|
||||
---help---
|
||||
Support IDMA data transfers.
|
||||
|
||||
|
||||
@ -63,6 +63,10 @@ CMN_CSRCS += up_usestack.c up_vfork.c
|
||||
|
||||
# Configuration-dependent common files
|
||||
|
||||
ifeq ($(CONFIG_ARMV7M_STACKCHECK),y)
|
||||
CMN_CSRCS += up_stackcheck.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARMV7M_LAZYFPU),y)
|
||||
CMN_ASRCS += up_lazyexception.S
|
||||
else
|
||||
|
||||
196
arch/arm/src/stm32h7/hardware/stm32_axi.h
Normal file
196
arch/arm/src/stm32h7/hardware/stm32_axi.h
Normal file
@ -0,0 +1,196 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32h7/hardware/stm32_axi.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david.sidrane@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_AXI_H
|
||||
#define __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_AXI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register Offsets *****************************************************************/
|
||||
|
||||
#define STM32_AXI_PERIPH_ID_4_OFFSET 0x01fd0 /* AXI interconnect peripheral ID4 register */
|
||||
#define STM32_AXI_PERIPH_ID_0_OFFSET 0x01fe0 /* AXI interconnect peripheral ID0 register */
|
||||
#define STM32_AXI_PERIPH_ID_1_OFFSET 0x01fe4 /* AXI interconnect peripheral ID1 register */
|
||||
#define STM32_AXI_PERIPH_ID_2_OFFSET 0x01fe8 /* AXI interconnect peripheral ID2 register */
|
||||
#define STM32_AXI_PERIPH_ID_3_OFFSET 0x01fec /* AXI interconnect peripheral ID3 register */
|
||||
#define STM32_AXI_COMP_ID_0_OFFSET 0x01ff0 /* AXI interconnect component ID0 register */
|
||||
#define STM32_AXI_COMP_ID_1_OFFSET 0x01ff4 /* AXI interconnect component ID1 register */
|
||||
#define STM32_AXI_COMP_ID_2_OFFSET 0x01ff8 /* AXI interconnect component ID2 register */
|
||||
#define STM32_AXI_COMP_ID_3_OFFSET 0x01ffc /* AXI interconnect component ID3 register */
|
||||
#define STM32_AXI_TARG1_FN_MOD_ISS_BM_OFFSET 0x02008 /* AXI interconnect TARG 1 bus matrix issuing functionality register */
|
||||
#define STM32_AXI_TARG2_FN_MOD_ISS_BM_OFFSET 0x03008 /* AXI interconnect TARG 2 bus matrix issuing functionality register */
|
||||
#define STM32_AXI_TARG3_FN_MOD_ISS_BM_OFFSET 0x04008 /* AXI interconnect TARG 3 bus matrix issuing functionality register */
|
||||
#define STM32_AXI_TARG4_FN_MOD_ISS_BM_OFFSET 0x05008 /* AXI interconnect TARG 4 bus matrix issuing functionality register */
|
||||
#define STM32_AXI_TARG5_FN_MOD_ISS_BM_OFFSET 0x06008 /* AXI interconnect TARG 5 bus matrix issuing functionality register */
|
||||
#define STM32_AXI_TARG6_FN_MOD_ISS_BM_OFFSET 0x07008 /* AXI interconnect TARG 6 bus matrix issuing functionality register */
|
||||
#define STM32_AXI_TARG7_FN_MOD_ISS_BM_OFFSET 0x08008 /* AXI interconnect TARG 7 bus matrix issuing functionality register */
|
||||
#define STM32_AXI_TARG1_FN_MOD2_OFFSET 0x02024 /* AXI interconnect TARG 1 bus matrix functionality 2 register */
|
||||
#define STM32_AXI_TARG2_FN_MOD2_OFFSET 0x03024 /* AXI interconnect TARG 2 bus matrix functionality 2 register */
|
||||
#define STM32_AXI_TARG7_FN_MOD2_OFFSET 0x08024 /* AXI interconnect TARG 7 bus matrix functionality 2 register */
|
||||
#define STM32_AXI_TARG1_FN_MOD_LB_OFFSET 0x0202c /* AXI interconnect TARG 1 long burst functionality modification register */
|
||||
#define STM32_AXI_TARG2_FN_MOD_LB_OFFSET 0x0302c /* AXI interconnect TARG 2 long burst functionality modification register */
|
||||
#define STM32_AXI_TARG1_FN_MOD_OFFSET 0x02108 /* AXI interconnect TARG 1 issuing functionality modification register */
|
||||
#define STM32_AXI_TARG2_FN_MOD_OFFSET 0x03108 /* AXI interconnect TARG 2 issuing functionality modification register */
|
||||
#define STM32_AXI_TARG7_FN_MOD_OFFSET 0x08108 /* AXI interconnect TARG 7 issuing functionality modification register */
|
||||
#define STM32_AXI_INI1_FN_MOD2_OFFSET 0x42024 /* AXI interconnect INI 1 functionality modification 2 register */
|
||||
#define STM32_AXI_INI3_FN_MOD2_OFFSET 0x44024 /* AXI interconnect INI 3 functionality modification 2 register */
|
||||
#define STM32_AXI_INI1_FN_MOD_AHB_OFFSET 0x42028 /* AXI interconnect INI 1 AHB functionality modification register */
|
||||
#define STM32_AXI_INI3_FN_MOD_AHB_OFFSET 0x44028 /* AXI interconnect INI 3 AHB functionality modification register */
|
||||
#define STM32_AXI_INI1_READ_QOS_OFFSET 0x42100 /* AXI interconnect INI 1 read QoS register */
|
||||
#define STM32_AXI_INI2_READ_QOS_OFFSET 0x43100 /* AXI interconnect INI 2 read QoS register */
|
||||
#define STM32_AXI_INI3_READ_QOS_OFFSET 0x44100 /* AXI interconnect INI 3 read QoS register */
|
||||
#define STM32_AXI_INI4_READ_QOS_OFFSET 0x45100 /* AXI interconnect INI 4 read QoS register */
|
||||
#define STM32_AXI_INI5_READ_QOS_OFFSET 0x46100 /* AXI interconnect INI 5 read QoS register */
|
||||
#define STM32_AXI_INI6_READ_QOS_OFFSET 0x47100 /* AXI interconnect INI 6 read QoS register */
|
||||
#define STM32_AXI_INI1_WRITE_QOS_OFFSET 0x42104 /* AXI interconnect INI 1 write QoS register */
|
||||
#define STM32_AXI_INI2_WRITE_QOS_OFFSET 0x43104 /* AXI interconnect INI 2 write QoS register */
|
||||
#define STM32_AXI_INI3_WRITE_QOS_OFFSET 0x44104 /* AXI interconnect INI 3 write QoS register */
|
||||
#define STM32_AXI_INI4_WRITE_QOS_OFFSET 0x45104 /* AXI interconnect INI 4 write QoS register */
|
||||
#define STM32_AXI_INI5_WRITE_QOS_OFFSET 0x46104 /* AXI interconnect INI 5 write QoS register */
|
||||
#define STM32_AXI_INI6_WRITE_QOS_OFFSET 0x47104 /* AXI interconnect INI 6 write QoS register */
|
||||
#define STM32_AXI_INI1_FN_MOD_OFFSET 0x42108 /* AXI interconnect INI 1 issuing functionality modification register */
|
||||
#define STM32_AXI_INI2_FN_MOD_OFFSET 0x43108 /* AXI interconnect INI 2 issuing functionality modification register */
|
||||
#define STM32_AXI_INI3_FN_MOD_OFFSET 0x44108 /* AXI interconnect INI 3 issuing functionality modification register */
|
||||
#define STM32_AXI_INI4_FN_MOD_OFFSET 0x45108 /* AXI interconnect INI 4 issuing functionality modification register */
|
||||
#define STM32_AXI_INI5_FN_MOD_OFFSET 0x46108 /* AXI interconnect INI 5 issuing functionality modification register */
|
||||
#define STM32_AXI_INI6_FN_MOD_OFFSET 0x47108 /* AXI interconnect INI 6 issuing functionality modification register */
|
||||
|
||||
/* Register Addresses ***************************************************************/
|
||||
|
||||
#define STM32_AXI_PERIPH_ID_4 (STM32_GPV_BASE + STM32_AXI_PERIPH_ID_4_OFFSET)
|
||||
#define STM32_AXI_PERIPH_ID_0 (STM32_GPV_BASE + STM32_AXI_PERIPH_ID_0_OFFSET)
|
||||
#define STM32_AXI_PERIPH_ID_1 (STM32_GPV_BASE + STM32_AXI_PERIPH_ID_1_OFFSET)
|
||||
#define STM32_AXI_PERIPH_ID_2 (STM32_GPV_BASE + STM32_AXI_PERIPH_ID_2_OFFSET)
|
||||
#define STM32_AXI_PERIPH_ID_3 (STM32_GPV_BASE + STM32_AXI_PERIPH_ID_3_OFFSET)
|
||||
#define STM32_AXI_COMP_ID_0 (STM32_GPV_BASE + STM32_AXI_COMP_ID_0_OFFSET)
|
||||
#define STM32_AXI_COMP_ID_1 (STM32_GPV_BASE + STM32_AXI_COMP_ID_1_OFFSET)
|
||||
#define STM32_AXI_COMP_ID_2 (STM32_GPV_BASE + STM32_AXI_COMP_ID_2_OFFSET)
|
||||
#define STM32_AXI_COMP_ID_3 (STM32_GPV_BASE + STM32_AXI_COMP_ID_3_OFFSET)
|
||||
#define STM32_AXI_TARG1_FN_MOD_ISS_BM (STM32_GPV_BASE + STM32_AXI_TARG1_FN_MOD_ISS_BM_OFFSET)
|
||||
#define STM32_AXI_TARG2_FN_MOD_ISS_BM (STM32_GPV_BASE + STM32_AXI_TARG2_FN_MOD_ISS_BM_OFFSET)
|
||||
#define STM32_AXI_TARG3_FN_MOD_ISS_BM (STM32_GPV_BASE + STM32_AXI_TARG3_FN_MOD_ISS_BM_OFFSET)
|
||||
#define STM32_AXI_TARG4_FN_MOD_ISS_BM (STM32_GPV_BASE + STM32_AXI_TARG4_FN_MOD_ISS_BM_OFFSET)
|
||||
#define STM32_AXI_TARG5_FN_MOD_ISS_BM (STM32_GPV_BASE + STM32_AXI_TARG5_FN_MOD_ISS_BM_OFFSET)
|
||||
#define STM32_AXI_TARG6_FN_MOD_ISS_BM (STM32_GPV_BASE + STM32_AXI_TARG6_FN_MOD_ISS_BM_OFFSET)
|
||||
#define STM32_AXI_TARG7_FN_MOD_ISS_BM (STM32_GPV_BASE + STM32_AXI_TARG7_FN_MOD_ISS_BM_OFFSET)
|
||||
#define STM32_AXI_TARG1_FN_MOD2 (STM32_GPV_BASE + STM32_AXI_TARG1_FN_MOD2_OFFSET)
|
||||
#define STM32_AXI_TARG2_FN_MOD2 (STM32_GPV_BASE + STM32_AXI_TARG2_FN_MOD2_OFFSET)
|
||||
#define STM32_AXI_TARG7_FN_MOD2 (STM32_GPV_BASE + STM32_AXI_TARG7_FN_MOD2_OFFSET)
|
||||
#define STM32_AXI_TARG1_FN_MOD_LB (STM32_GPV_BASE + STM32_AXI_TARG1_FN_MOD_LB_OFFSET)
|
||||
#define STM32_AXI_TARG2_FN_MOD_LB (STM32_GPV_BASE + STM32_AXI_TARG2_FN_MOD_LB_OFFSET)
|
||||
#define STM32_AXI_TARG1_FN_MOD (STM32_GPV_BASE + STM32_AXI_TARG1_FN_MOD_OFFSET)
|
||||
#define STM32_AXI_TARG2_FN_MOD (STM32_GPV_BASE + STM32_AXI_TARG2_FN_MOD_OFFSET)
|
||||
#define STM32_AXI_TARG7_FN_MOD (STM32_GPV_BASE + STM32_AXI_TARG7_FN_MOD_OFFSET)
|
||||
#define STM32_AXI_INI1_FN_MOD2 (STM32_GPV_BASE + STM32_AXI_INI1_FN_MOD2_OFFSET)
|
||||
#define STM32_AXI_INI3_FN_MOD2 (STM32_GPV_BASE + STM32_AXI_INI3_FN_MOD2_OFFSET)
|
||||
#define STM32_AXI_INI1_FN_MOD_AHB (STM32_GPV_BASE + STM32_AXI_INI1_FN_MOD_AHB_OFFSET)
|
||||
#define STM32_AXI_INI3_FN_MOD_AHB (STM32_GPV_BASE + STM32_AXI_INI3_FN_MOD_AHB_OFFSET)
|
||||
#define STM32_AXI_INI1_READ_QOS (STM32_GPV_BASE + STM32_AXI_INI1_READ_QOS_OFFSET)
|
||||
#define STM32_AXI_INI2_READ_QOS (STM32_GPV_BASE + STM32_AXI_INI2_READ_QOS_OFFSET)
|
||||
#define STM32_AXI_INI3_READ_QOS (STM32_GPV_BASE + STM32_AXI_INI3_READ_QOS_OFFSET)
|
||||
#define STM32_AXI_INI4_READ_QOS (STM32_GPV_BASE + STM32_AXI_INI4_READ_QOS_OFFSET)
|
||||
#define STM32_AXI_INI5_READ_QOS (STM32_GPV_BASE + STM32_AXI_INI5_READ_QOS_OFFSET)
|
||||
#define STM32_AXI_INI6_READ_QOS (STM32_GPV_BASE + STM32_AXI_INI6_READ_QOS_OFFSET)
|
||||
#define STM32_AXI_INI1_WRITE_QOS (STM32_GPV_BASE + STM32_AXI_INI1_WRITE_QOS_OFFSET)
|
||||
#define STM32_AXI_INI2_WRITE_QOS (STM32_GPV_BASE + STM32_AXI_INI2_WRITE_QOS_OFFSET)
|
||||
#define STM32_AXI_INI3_WRITE_QOS (STM32_GPV_BASE + STM32_AXI_INI3_WRITE_QOS_OFFSET)
|
||||
#define STM32_AXI_INI4_WRITE_QOS (STM32_GPV_BASE + STM32_AXI_INI4_WRITE_QOS_OFFSET)
|
||||
#define STM32_AXI_INI5_WRITE_QOS (STM32_GPV_BASE + STM32_AXI_INI5_WRITE_QOS_OFFSET)
|
||||
#define STM32_AXI_INI6_WRITE_QOS (STM32_GPV_BASE + STM32_AXI_INI6_WRITE_QOS_OFFSET)
|
||||
#define STM32_AXI_INI1_FN_MOD (STM32_GPV_BASE + STM32_AXI_INI1_FN_MOD_OFFSET)
|
||||
#define STM32_AXI_INI2_FN_MOD (STM32_GPV_BASE + STM32_AXI_INI2_FN_MOD_OFFSET)
|
||||
#define STM32_AXI_INI3_FN_MOD (STM32_GPV_BASE + STM32_AXI_INI3_FN_MOD_OFFSET)
|
||||
#define STM32_AXI_INI4_FN_MOD (STM32_GPV_BASE + STM32_AXI_INI4_FN_MOD_OFFSET)
|
||||
#define STM32_AXI_INI5_FN_MOD (STM32_GPV_BASE + STM32_AXI_INI5_FN_MOD_OFFSET)
|
||||
#define STM32_AXI_INI6_FN_MOD (STM32_GPV_BASE + STM32_AXI_INI6_FN_MOD_OFFSET)
|
||||
|
||||
/* AXI Register Bitfield Definitions *********************************************************/
|
||||
|
||||
/* TARG x bus matrix issuing functionality Register */
|
||||
|
||||
#define AXI_TARG_READ_ISS_BM_OVERRIDE (1 << 0) /* Bit 0: Switch matrix read issuing override for target */
|
||||
#define AXI_TARG_WRITE_ISS_BM_OVERRIDE (1 << 1) /* Bit 1: Switch matrix write issuing override for target */
|
||||
|
||||
/* TARG x bus matrix issuing functionality 2 Register */
|
||||
|
||||
#define AXI_TARG_BYPASS_MERGE (1 << 0) /* Bit 0: Disable packing of beats to match the output data width. Unaligned transactions are not realigned to the input data word boundary */
|
||||
|
||||
/* TARG x long burst functionality modification Register */
|
||||
|
||||
#define AXI_TARG_FN_MOD_LB (1 << 0) /* Bit 0: Controls burst breaking of long bursts */
|
||||
|
||||
/* TARG x bus matrix issuing functionality Register */
|
||||
|
||||
#define AXI_TARG_READ_ISS_OVERRIDE (1 << 0) /* Bit 0: Override AMIB read issuing capability */
|
||||
#define AXI_TARG_WRITE_ISS_OVERRIDE (1 << 1) /* Bit 1: Override AMIB write issuing capability */
|
||||
|
||||
/* INI x functionality modification 2 Register */
|
||||
|
||||
#define AXI_INI_BYPASS_MERGE (1 << 0) /* Bit 0: Disables alteration of transactions by the up-sizer unless required by the protocol */
|
||||
|
||||
/* INI x AHB functionality modification Register */
|
||||
|
||||
#define AXI_INI_RD_INC_OVERRIDE (1 << 0) /* Bit 0: Converts all AHB-Lite read transactions to a series of single beat AXI transactions. */
|
||||
#define AXI_INI_WR_INC_OVERRIDE (1 << 1) /* Bit 1: Converts all AHB-Lite write transactions to a series of single beat AXI transactions */
|
||||
|
||||
/* INI x read QoS Register */
|
||||
|
||||
#define AXI_INI_AR_QOS_SHIFT (0) /* Bits 0-3: Read channel QoS setting */
|
||||
#define AXI_INI_AR_QOS_MASK (0xf << AXI_INI_AR_QOS_SHIFT)
|
||||
#define AXI_INI_AR_QOS(x) (((x) & 0xf) << AXI_INI_AR_QOS_SHIFT)
|
||||
|
||||
/* INI x write QoS Register */
|
||||
|
||||
#define AXI_INI_AW_QOS_SHIFT (0) /* Bits 0-3: Write channel QoS setting */
|
||||
#define AXI_INI_AW_QOS_MASK (0xf << AXI_INI_AW_QOS_SHIFT)
|
||||
#define AXI_INI_AW_QOS(x) (((x) & 0xf) << AXI_INI_AW_QOS_SHIFT)
|
||||
|
||||
/* INI x issuing functionality modification Register */
|
||||
|
||||
#define AXI_INI_READ_ISS_OVERRIDE (1 << 0) /* Bit 0: Override ASIB read issuing capability */
|
||||
#define AXI_INI_WRITE_ISS_OVERRIDE (1 << 1) /* Bit 1: Override ASIB write issuing capability */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H7_HARDWARE_STM32_AXI_H */
|
||||
@ -1062,31 +1062,31 @@
|
||||
#define GPIO_SDMMC1_CDIR (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_SDMMC1_CK (GPIO_ALT|GPIO_AF12|GPIO_PORTC|GPIO_PIN12)
|
||||
#define GPIO_SDMMC1_CKIN (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_SDMMC1_CMD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_SDMMC1_D0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_SDMMC1_CMD (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_SDMMC1_D0 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN8)
|
||||
#define GPIO_SDMMC1_D0DIR (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_SDMMC1_D1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_SDMMC1_D1 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_SDMMC1_D123DIR (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_SDMMC1_D2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_SDMMC1_D3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_SDMMC1_D4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_SDMMC1_D5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_SDMMC1_D6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_SDMMC1_D7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_SDMMC1_D2 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
|
||||
#define GPIO_SDMMC1_D3 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
|
||||
#define GPIO_SDMMC1_D4 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_SDMMC1_D5 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_SDMMC1_D6 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_SDMMC1_D7 (GPIO_ALT|GPIO_AF12|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
|
||||
|
||||
#define GPIO_SDMMC2_CK_1 (GPIO_ALT|GPIO_AF11|GPIO_PORTD|GPIO_PIN6)
|
||||
#define GPIO_SDMMC2_CK_2 (GPIO_ALT|GPIO_AF9|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_SDMMC2_CMD_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTD|GPIO_PIN7)
|
||||
#define GPIO_SDMMC2_CMD_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_SDMMC2_D0 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_SDMMC2_D1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_SDMMC2_D2_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTG|GPIO_PIN11)
|
||||
#define GPIO_SDMMC2_D2_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_SDMMC2_D3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_SDMMC2_D4 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_SDMMC2_D5 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_SDMMC2_D6 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_SDMMC2_D7 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_SDMMC2_CMD_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_SDMMC2_D0 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14)
|
||||
#define GPIO_SDMMC2_D1 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_SDMMC2_D2_1 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULLGPIO_PORTG|GPIO_PIN11)
|
||||
#define GPIO_SDMMC2_D2_2 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_SDMMC2_D3 (GPIO_ALT|GPIO_AF9|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_SDMMC2_D4 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_SDMMC2_D5 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_SDMMC2_D6 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_SDMMC2_D7 (GPIO_ALT|GPIO_AF10|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
|
||||
|
||||
/* SPDIFRX */
|
||||
|
||||
|
||||
@ -62,7 +62,9 @@
|
||||
#define STM32_SDMMC_ICR_OFFSET 0x0038 /* SDMMC interrupt clear register */
|
||||
#define STM32_SDMMC_MASK_OFFSET 0x003c /* SDMMC mask register */
|
||||
#define STM32_SDMMC_IDMACTRLR_OFFSET 0x0050 /* SDMMC DMA control register */
|
||||
#define STM32_SDMMC_IDMABSIZER_OFFSET 0x0054 /* SDMMC DMA size register */
|
||||
#define STM32_SDMMC_IDMABASE0R_OFFSET 0x0058 /* SDMMC IDMA buffer 0 base register */
|
||||
#define STM32_SDMMC_IDMABASE1R_OFFSET 0x005c /* SDMMC IDMA buffer 1 base register */
|
||||
#define STM32_SDMMC_FIFO_OFFSET 0x0080 /* SDMMC data FIFO register */
|
||||
|
||||
/* Register Bitfield Definitions ****************************************************/
|
||||
@ -78,13 +80,21 @@
|
||||
#define STM32_SDMMC_CLKCR_CLKDIV_SHIFT (0) /* Bits 9-0: Clock divide factor */
|
||||
#define STM32_SDMMC_CLKCR_CLKDIV_MASK (0x3ff << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_CLKCR_PWRSAV (1 << 12) /* Bit 12: Power saving configuration bit */
|
||||
#define STM32_SDMMC_CLKCR_WIDBUS_SHIFT (14) /* Bits 12-11: Wide bus mode enable bits */
|
||||
#define STM32_SDMMC_CLKCR_WIDBUS_SHIFT (14) /* Bits 15-14: Wide bus mode enable bits */
|
||||
#define STM32_SDMMC_CLKCR_WIDBUS_MASK (3 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT)
|
||||
# define STM32_SDMMC_CLKCR_WIDBUS_D1 (0 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 00: Default (STM32_SDMMC_D0) */
|
||||
# define STM32_SDMMC_CLKCR_WIDBUS_D4 (1 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (STM32_SDMMC_D[3:0]) */
|
||||
# define STM32_SDMMC_CLKCR_WIDBUS_D8 (2 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (STM32_SDMMC_D[7:0]) */
|
||||
#define STM32_SDMMC_CLKCR_NEGEDGE (1 << 16) /* Bit 16: STM32_SDMMC_CK dephasing selection bit */
|
||||
#define STM32_SDMMC_CLKCR_HWFC_EN (1 << 17) /* Bit 17: HW Flow Control enable */
|
||||
#define STM32_SDMMC_CLKCR_DDR (1 << 18) /* Bit 18: Data rate signaling selection */
|
||||
#define STM32_SDMMC_CLKCR_BUS_SPEED (1 << 19) /* Bit 19: Bus speed mode selection */
|
||||
#define STM32_SDMMC_CLKCR_SELCLKRX_SHIFT (20) /* Bits 21-20: Receive clock selection */
|
||||
#define STM32_SDMMC_CLKCR_SELCLKRX_MASK (3 << STM32_SDMMC_CLKCR_SELCLKRX_SHIFT)
|
||||
# define STM32_SDMMC_CLKCR_SELCLKRX_IO_IN (0 << STM32_SDMMC_CLKCR_SELCLKRX_SHIFT) /* 00: sdmmc_io_in_ck selected as receive clock */
|
||||
# define STM32_SDMMC_CLKCR_SELCLKRX_CKIN (1 << STM32_SDMMC_CLKCR_SELCLKRX_SHIFT) /* 01: SDMMC_CKIN feedback clock selected as receive clock */
|
||||
# define STM32_SDMMC_CLKCR_SELCLKRX_FB (2 << STM32_SDMMC_CLKCR_SELCLKRX_SHIFT) /* 10: sdmmc_fb_ck tuned feedback clock selected as receive clock. */
|
||||
/* 11: Reserved (select sdmmc_io_in_ck) */
|
||||
|
||||
#define STM32_SDMMC_CLKCR_RESET (0) /* Reset value */
|
||||
|
||||
@ -209,7 +219,7 @@
|
||||
#define STM32_SDMMC_ICR_IDMATEC (1 << 27) /* Bit 27: IDMA transfer error clear bit */
|
||||
#define STM32_SDMMC_ICR_IDMABTCC (1 << 28) /* Bit 28: IDMA buffer transfer complete clear bit */
|
||||
|
||||
#define STM32_SDMMC_ICR_RESET 0x00000000
|
||||
#define STM32_SDMMC_ICR_RESET 0x1fe00fff
|
||||
#define STM32_SDMMC_ICR_ALLFLAGS 0x1fe00fff
|
||||
|
||||
#define STM32_SDMMC_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */
|
||||
@ -238,7 +248,12 @@
|
||||
|
||||
#define STM32_SDMMC_MASK_RESET (0)
|
||||
|
||||
#define STM32_SDMMC_IDMACTRLR_IDMAEN (1 << 0)
|
||||
#define STM32_SDMMC_IDMACTRLR_IDMAEN (1 << 0) /* Bit 0: IDMA enable */
|
||||
#define STM32_SDMMC_IDMACTRLR_IDMABMODE (1 << 1) /* Bit 1: Buffer mode selection */
|
||||
#define STM32_SDMMC_IDMACTRLR_IDMABACT (1 << 2) /* Bit 2: Double buffer mode active buffer indication */
|
||||
|
||||
#define STM32_SDMMC_IDMABSIZER_SHIFT (5) /* Bits 12-5: Number of bytes per buffer divided by 32 */
|
||||
#define STM32_SDMMC_IDMABSIZER_MASK (0xff << STM32_SDMMC_IDMABSIZER_SHIFT)
|
||||
|
||||
#define STM32_SDMMC_FIFOCNT_SHIFT (0)
|
||||
#define STM32_SDMMC_FIFOCNT_MASK (0x0ffffff << STM32_SDMMC_FIFOCNT_SHIFT)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,9 +1,9 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h7/stm32h7x3xx_rcc.c
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2018, 2019 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
* David Sidrane <david.sidrane@nscdg.com>
|
||||
* Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@ -40,6 +40,7 @@
|
||||
****************************************************************************/
|
||||
|
||||
#include "stm32_pwr.h"
|
||||
#include "hardware/stm32_axi.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@ -95,6 +96,14 @@ static inline void rcc_reset(void)
|
||||
regval |= RCC_CR_HSION;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
#if defined(CONFIG_STM32H7_AXI_SRAM_CORRUPTION_WAR)
|
||||
/* Errata 2.2.9 Enable workaround for Reading from AXI SRAM may lead to data
|
||||
* read corruption. See ES0392 Rev 6.
|
||||
*/
|
||||
|
||||
putreg32(AXI_TARG_READ_ISS_OVERRIDE, STM32_AXI_TARG7_FN_MOD);
|
||||
#endif
|
||||
|
||||
/* Reset CFGR register */
|
||||
|
||||
putreg32(0x00000000, STM32_RCC_CFGR);
|
||||
@ -209,7 +218,7 @@ static inline void rcc_enableahb2(void)
|
||||
|
||||
regval = getreg32(STM32_RCC_AHB2ENR);
|
||||
|
||||
// TODO: ...
|
||||
/* TODO: ... */
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */
|
||||
}
|
||||
@ -244,7 +253,7 @@ static inline void rcc_enableahb3(void)
|
||||
regval |= RCC_AHB3ENR_SDMMC1EN;
|
||||
#endif
|
||||
|
||||
// TODO: ...
|
||||
/* TODO: ... */
|
||||
|
||||
putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
|
||||
}
|
||||
@ -379,13 +388,13 @@ static inline void rcc_enableapb1(void)
|
||||
regval |= RCC_APB1LENR_I2C3EN;
|
||||
#endif
|
||||
|
||||
// TODO: ...
|
||||
/* TODO: ... */
|
||||
|
||||
putreg32(regval, STM32_RCC_APB1LENR); /* Enable APB1L peripherals */
|
||||
|
||||
regval = getreg32(STM32_RCC_APB1HENR);
|
||||
|
||||
// TODO: ...
|
||||
/* TODO: ... */
|
||||
|
||||
putreg32(regval, STM32_RCC_APB1HENR); /* Enable APB1H peripherals */
|
||||
}
|
||||
@ -453,7 +462,7 @@ static inline void rcc_enableapb3(void)
|
||||
|
||||
regval = getreg32(STM32_RCC_APB3ENR);
|
||||
|
||||
// TODO: ...
|
||||
/* TODO: ... */
|
||||
|
||||
putreg32(regval, STM32_RCC_APB3ENR); /* Enable peripherals */
|
||||
}
|
||||
@ -494,7 +503,7 @@ static inline void rcc_enableapb4(void)
|
||||
regval |= RCC_APB4ENR_SPI6EN;
|
||||
#endif
|
||||
|
||||
// TODO: ...
|
||||
/* TODO: ... */
|
||||
|
||||
putreg32(regval, STM32_RCC_APB4ENR); /* Enable peripherals */
|
||||
}
|
||||
@ -620,7 +629,6 @@ static void stm32_stdclockconfig(void)
|
||||
regval |= STM32_RCC_D3CFGR_D3PPRE;
|
||||
putreg32(regval, STM32_RCC_D3CFGR);
|
||||
|
||||
|
||||
#ifdef CONFIG_STM32H7_RTC_HSECLOCK
|
||||
/* Set the RTC clock divisor */
|
||||
|
||||
@ -729,7 +737,8 @@ static void stm32_stdclockconfig(void)
|
||||
|
||||
/* Wait until the PLL source is used as the system clock source */
|
||||
|
||||
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL1)
|
||||
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
|
||||
RCC_CFGR_SWS_PLL1)
|
||||
{
|
||||
}
|
||||
|
||||
@ -790,7 +799,6 @@ static void stm32_stdclockconfig(void)
|
||||
putreg32(regval, STM32_RCC_D3CCIPR);
|
||||
#endif
|
||||
|
||||
|
||||
#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK)
|
||||
/* Low speed internal clock source LSI */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user