arch/risc-v: Refine exception_common
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
This commit is contained in:
Huang Qi
Petro Karashchenko
parent
297c8dfc3a
commit
c6749fd6fd
@ -23,9 +23,7 @@
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HEAD_ASRC = bl602_entry.S
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# Specify our general Assembly files
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CHIP_ASRCS = bl602_head.S
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CMN_ASRCS += riscv_vectors.S riscv_testset.S
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CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
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# Specify C code within the common directory to be included
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CMN_CSRCS += riscv_initialize.c riscv_swint.c
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@ -1,170 +0,0 @@
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/****************************************************************************
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* arch/risc-v/src/bl602/bl602_head.S
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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/****************************************************************************
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* Public Symbols
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****************************************************************************/
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.global exception_common
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/****************************************************************************
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* Name: exception_common
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****************************************************************************/
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.align 8
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exception_common:
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addi sp, sp, -XCPTCONTEXT_SIZE
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sw x1, 1*4(sp) /* ra */
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sw x3, 3*4(sp) /* gp */
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sw x4, 4*4(sp) /* tp */
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sw x5, 5*4(sp) /* t0 */
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sw x6, 6*4(sp) /* t1 */
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sw x7, 7*4(sp) /* t2 */
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sw x8, 8*4(sp) /* s0 */
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sw x9, 9*4(sp) /* s1 */
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sw x10, 10*4(sp) /* a0 */
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sw x11, 11*4(sp) /* a1 */
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sw x12, 12*4(sp) /* a2 */
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sw x13, 13*4(sp) /* a3 */
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sw x14, 14*4(sp) /* a4 */
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sw x15, 15*4(sp) /* a5 */
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sw x16, 16*4(sp) /* a6 */
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sw x17, 17*4(sp) /* a7 */
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sw x18, 18*4(sp) /* s2 */
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sw x19, 19*4(sp) /* s3 */
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sw x20, 20*4(sp) /* s4 */
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sw x21, 21*4(sp) /* s5 */
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sw x22, 22*4(sp) /* s6 */
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sw x23, 23*4(sp) /* s7 */
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sw x24, 24*4(sp) /* s8 */
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sw x25, 25*4(sp) /* s9 */
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sw x26, 26*4(sp) /* s10 */
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sw x27, 27*4(sp) /* s11 */
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sw x28, 28*4(sp) /* t3 */
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sw x29, 29*4(sp) /* t4 */
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sw x30, 30*4(sp) /* t5 */
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sw x31, 31*4(sp) /* t6 */
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csrr s0, mstatus
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sw s0, 32*4(sp) /* mstatus */
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addi s0, sp, XCPTCONTEXT_SIZE
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sw s0, 2*4(sp) /* original SP */
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csrr s0, mepc
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sw s0, 0(sp) /* exception PC */
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#ifdef CONFIG_STACK_OVERFLOW_CHECK
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la t0, __cyg_profile_func_enter
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jalr x1, 0(t0)
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#endif
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/* Setup arg0(exception cause), arg1(context) */
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csrr a0, mcause /* exception cause */
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mv a1, sp /* context = sp */
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#if CONFIG_ARCH_INTERRUPTSTACK > 15
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/* Switch to interrupt stack */
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lui sp, %hi(g_intstacktop)
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addi sp, sp, %lo(g_intstacktop)
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#ifdef CONFIG_STACK_OVERFLOW_CHECK
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la s11, g_intstackalloc
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#endif
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#endif
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/* Call interrupt handler in C */
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jal x1, bl602_dispatch_irq
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/* If context switch is needed, return a new sp */
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mv sp, a0
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lw s0, 0(sp) /* restore mepc */
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csrw mepc, s0
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lw s0, 32*4(sp) /* restore mstatus */
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csrw mstatus, s0
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lw x3, 3*4(sp) /* gp */
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lw x4, 4*4(sp) /* tp */
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lw x5, 5*4(sp) /* t0 */
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lw x6, 6*4(sp) /* t1 */
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lw x7, 7*4(sp) /* t2 */
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lw x8, 8*4(sp) /* s0 */
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lw x9, 9*4(sp) /* s1 */
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lw x10, 10*4(sp) /* a0 */
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lw x11, 11*4(sp) /* a1 */
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lw x12, 12*4(sp) /* a2 */
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lw x13, 13*4(sp) /* a3 */
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lw x14, 14*4(sp) /* a4 */
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lw x15, 15*4(sp) /* a5 */
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lw x16, 16*4(sp) /* a6 */
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lw x17, 17*4(sp) /* a7 */
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lw x18, 18*4(sp) /* s2 */
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lw x19, 19*4(sp) /* s3 */
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lw x20, 20*4(sp) /* s4 */
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lw x21, 21*4(sp) /* s5 */
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lw x22, 22*4(sp) /* s6 */
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lw x23, 23*4(sp) /* s7 */
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lw x24, 24*4(sp) /* s8 */
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lw x25, 25*4(sp) /* s9 */
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lw x26, 26*4(sp) /* s10 */
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lw x27, 27*4(sp) /* s11 */
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lw x28, 28*4(sp) /* t3 */
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lw x29, 29*4(sp) /* t4 */
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lw x30, 30*4(sp) /* t5 */
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lw x31, 31*4(sp) /* t6 */
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lw x1, 1*4(sp) /* ra */
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lw sp, 2*4(sp) /* restore original sp */
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/* Return from Machine Interrupt */
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mret
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/************************************************************************************
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* Name: g_intstackalloc and g_intstacktop
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************************************************************************************/
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#if CONFIG_ARCH_INTERRUPTSTACK > 15
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.bss
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.balign 16
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.global g_intstackalloc
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.global g_intstacktop
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.type g_intstackalloc, object
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.type g_intstacktop, object
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g_intstackalloc:
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.skip ((CONFIG_ARCH_INTERRUPTSTACK + 8) & ~15)
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g_intstacktop:
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.size g_intstacktop, 0
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.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~15)
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#endif
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@ -48,10 +48,10 @@ volatile uintptr_t *g_current_regs[1];
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****************************************************************************/
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/****************************************************************************
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* bl602_dispatch_irq
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* riscv_dispatch_irq
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****************************************************************************/
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void *bl602_dispatch_irq(uintptr_t vector, uintptr_t *regs)
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void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
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{
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uintptr_t irq = vector & 0x3ff; /* E24 [9:0] */
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uintptr_t *mepc = regs;
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@ -23,7 +23,7 @@
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HEAD_ASRC = c906_head.S
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# Specify our general Assembly files
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CMN_ASRCS += riscv_vectors.S riscv_testset.S
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CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
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# Specify C code within the common directory to be included
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CMN_CSRCS += riscv_initialize.c riscv_swint.c
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@ -34,8 +34,6 @@
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* Public Symbols
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****************************************************************************/
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.global exception_common
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/* Imported symbols */
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.extern __trap_vec
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@ -108,145 +106,3 @@ _fini:
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/* These don't have to do anything since we use init_array/fini_array. */
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ret
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/****************************************************************************
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* Name: exception_common
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****************************************************************************/
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exception_common:
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addi sp, sp, -XCPTCONTEXT_SIZE
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sd x1, 1*8(sp) /* ra */
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/* leave gp(x3) in 3*8(sp) untouched */
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sd x4, 4*8(sp) /* tp */
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sd x5, 5*8(sp) /* t0 */
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sd x6, 6*8(sp) /* t1 */
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sd x7, 7*8(sp) /* t2 */
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sd x8, 8*8(sp) /* s0 */
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sd x9, 9*8(sp) /* s1 */
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sd x10, 10*8(sp) /* a0 */
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sd x11, 11*8(sp) /* a1 */
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sd x12, 12*8(sp) /* a2 */
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sd x13, 13*8(sp) /* a3 */
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sd x14, 14*8(sp) /* a4 */
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sd x15, 15*8(sp) /* a5 */
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sd x16, 16*8(sp) /* a6 */
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sd x17, 17*8(sp) /* a7 */
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sd x18, 18*8(sp) /* s2 */
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sd x19, 19*8(sp) /* s3 */
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sd x20, 20*8(sp) /* s4 */
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sd x21, 21*8(sp) /* s5 */
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sd x22, 22*8(sp) /* s6 */
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sd x23, 23*8(sp) /* s7 */
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sd x24, 24*8(sp) /* s8 */
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sd x25, 25*8(sp) /* s9 */
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sd x26, 26*8(sp) /* s10 */
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sd x27, 27*8(sp) /* s11 */
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sd x28, 28*8(sp) /* t3 */
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sd x29, 29*8(sp) /* t4 */
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sd x30, 30*8(sp) /* t5 */
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sd x31, 31*8(sp) /* t6 */
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csrr s0, mstatus
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sd s0, 32*8(sp) /* mstatus */
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addi s0, sp, XCPTCONTEXT_SIZE
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sd s0, 2*8(sp) /* original SP */
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/* Setup arg0(exception cause), arg1(context) */
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csrr a0, mcause /* exception cause */
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csrr s0, mepc
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sd s0, 0(sp) /* exception PC */
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mv a1, sp /* context = sp */
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#if CONFIG_ARCH_INTERRUPTSTACK > 15
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/* Load mhartid (cpuid) */
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csrr s0, mhartid
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/* Switch to interrupt stack */
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bnez s0, 3f
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la sp, g_intstacktop
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j 4f
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3:
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la sp, g_intstacktop
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addi sp, sp, -(CONFIG_ARCH_INTERRUPTSTACK & ~15)
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4:
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#endif
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/* Call interrupt handler in C */
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jal x1, c906_dispatch_irq
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/* If context switch is needed, return a new sp */
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mv sp, a0
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ld s0, 0(sp) /* restore mepc */
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csrw mepc, s0
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ld s0, 32*8(sp) /* restore mstatus */
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csrw mstatus, s0
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/* leave gp(x3) in 3*8(sp) untouched */
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ld x4, 4*8(sp) /* tp */
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ld x5, 5*8(sp) /* t0 */
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ld x6, 6*8(sp) /* t1 */
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ld x7, 7*8(sp) /* t2 */
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ld x8, 8*8(sp) /* s0 */
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ld x9, 9*8(sp) /* s1 */
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ld x10, 10*8(sp) /* a0 */
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ld x11, 11*8(sp) /* a1 */
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ld x12, 12*8(sp) /* a2 */
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ld x13, 13*8(sp) /* a3 */
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ld x14, 14*8(sp) /* a4 */
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ld x15, 15*8(sp) /* a5 */
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ld x16, 16*8(sp) /* a6 */
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ld x17, 17*8(sp) /* a7 */
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ld x18, 18*8(sp) /* s2 */
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ld x19, 19*8(sp) /* s3 */
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ld x20, 20*8(sp) /* s4 */
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ld x21, 21*8(sp) /* s5 */
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ld x22, 22*8(sp) /* s6 */
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ld x23, 23*8(sp) /* s7 */
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ld x24, 24*8(sp) /* s8 */
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ld x25, 25*8(sp) /* s9 */
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ld x26, 26*8(sp) /* s10 */
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ld x27, 27*8(sp) /* s11 */
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ld x28, 28*8(sp) /* t3 */
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ld x29, 29*8(sp) /* t4 */
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ld x30, 30*8(sp) /* t5 */
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ld x31, 31*8(sp) /* t6 */
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ld x1, 1*8(sp) /* ra */
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ld sp, 2*8(sp) /* restore original sp */
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/* Return from Machine Interrupt */
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mret
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/************************************************************************************
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* Name: g_intstackalloc and g_intstacktop
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************************************************************************************/
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#if CONFIG_ARCH_INTERRUPTSTACK > 15
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.bss
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.balign 16
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.global g_intstackalloc
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.global g_intstacktop
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.type g_intstackalloc, object
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.type g_intstacktop, object
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g_intstackalloc:
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.skip ((CONFIG_ARCH_INTERRUPTSTACK + 8) & ~15)
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g_intstacktop:
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.size g_intstacktop, 0
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.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~15)
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#endif
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@ -48,10 +48,10 @@ extern void up_fault(int irq, uint64_t *regs);
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****************************************************************************/
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/****************************************************************************
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* c906_dispatch_irq
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* riscv_dispatch_irq
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****************************************************************************/
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void *c906_dispatch_irq(uint64_t vector, uint64_t *regs)
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void *riscv_dispatch_irq(uint64_t vector, uint64_t *regs)
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{
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uint32_t irq = (vector >> (27 + 32)) | (vector & 0xf);
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uint64_t *mepc = regs;
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193
arch/risc-v/src/common/riscv_exception_common.S
Normal file
193
arch/risc-v/src/common/riscv_exception_common.S
Normal file
@ -0,0 +1,193 @@
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/****************************************************************************
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* arch/risc-v/src/common/riscv_exception_common.S
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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* License for the specific language governing permissions and limitations
|
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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/****************************************************************************
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* Public Symbols
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****************************************************************************/
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#ifdef CONFIG_ARCH_RV32
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# define REGLOAD lw
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# define REGSTORE sw
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#else
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# define REGLOAD ld
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# define REGSTORE sd
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#endif
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/****************************************************************************
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* Name: exception_common
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****************************************************************************/
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.section .text
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.global exception_common
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exception_common:
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addi sp, sp, -XCPTCONTEXT_SIZE
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REGSTORE x1, REG_X1(sp) /* ra */
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REGSTORE x3, REG_X3(sp) /* gp */
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REGSTORE x4, REG_X4(sp) /* tp */
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REGSTORE x5, REG_X5(sp) /* t0 */
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REGSTORE x6, REG_X6(sp) /* t1 */
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REGSTORE x7, REG_X7(sp) /* t2 */
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REGSTORE x8, REG_X8(sp) /* s0 */
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REGSTORE x9, REG_X9(sp) /* s1 */
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REGSTORE x10, REG_X10(sp) /* a0 */
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REGSTORE x11, REG_X11(sp) /* a1 */
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REGSTORE x12, REG_X12(sp) /* a2 */
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REGSTORE x13, REG_X13(sp) /* a3 */
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REGSTORE x14, REG_X14(sp) /* a4 */
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REGSTORE x15, REG_X15(sp) /* a5 */
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REGSTORE x16, REG_X16(sp) /* a6 */
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REGSTORE x17, REG_X17(sp) /* a7 */
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REGSTORE x18, REG_X18(sp) /* s2 */
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REGSTORE x19, REG_X19(sp) /* s3 */
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REGSTORE x20, REG_X20(sp) /* s4 */
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REGSTORE x21, REG_X21(sp) /* s5 */
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REGSTORE x22, REG_X22(sp) /* s6 */
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REGSTORE x23, REG_X23(sp) /* s7 */
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REGSTORE x24, REG_X24(sp) /* s8 */
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REGSTORE x25, REG_X25(sp) /* s9 */
|
||||
REGSTORE x26, REG_X26(sp) /* s10 */
|
||||
REGSTORE x27, REG_X27(sp) /* s11 */
|
||||
REGSTORE x28, REG_X28(sp) /* t3 */
|
||||
REGSTORE x29, REG_X29(sp) /* t4 */
|
||||
REGSTORE x30, REG_X30(sp) /* t5 */
|
||||
REGSTORE x31, REG_X31(sp) /* t6 */
|
||||
|
||||
csrr s0, mstatus
|
||||
REGSTORE s0, REG_INT_CTX(sp) /* mstatus */
|
||||
|
||||
addi s0, sp, XCPTCONTEXT_SIZE
|
||||
REGSTORE s0, REG_X2(sp) /* original SP */
|
||||
|
||||
/* Setup arg0(exception cause), arg1(context) */
|
||||
|
||||
csrr a0, mcause /* exception cause */
|
||||
csrr s0, mepc
|
||||
REGSTORE s0, REG_EPC(sp) /* exception PC */
|
||||
|
||||
mv a1, sp /* context = sp */
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 15
|
||||
/* Load mhartid (cpuid) */
|
||||
|
||||
csrr s0, mhartid
|
||||
|
||||
/* Switch to interrupt stack */
|
||||
|
||||
bnez s0, 1f
|
||||
la sp, g_intstacktop
|
||||
j 2f
|
||||
1:
|
||||
la sp, g_intstacktop
|
||||
li t0, -(CONFIG_ARCH_INTERRUPTSTACK & ~15)
|
||||
add sp, sp, t0
|
||||
2:
|
||||
|
||||
#endif
|
||||
|
||||
/* Call interrupt handler in C */
|
||||
|
||||
jal x1, riscv_dispatch_irq
|
||||
|
||||
/* If context switch is needed, return a new sp */
|
||||
|
||||
mv sp, a0
|
||||
REGLOAD s0, REG_EPC(sp) /* restore mepc */
|
||||
csrw mepc, s0
|
||||
|
||||
REGLOAD s0, REG_INT_CTX(sp) /* restore mstatus */
|
||||
csrw mstatus, s0
|
||||
|
||||
REGLOAD x3, REG_X3(sp) /* gp */
|
||||
REGLOAD x4, REG_X4(sp) /* tp */
|
||||
REGLOAD x5, REG_X5(sp) /* t0 */
|
||||
REGLOAD x6, REG_X6(sp) /* t1 */
|
||||
REGLOAD x7, REG_X7(sp) /* t2 */
|
||||
REGLOAD x8, REG_X8(sp) /* s0 */
|
||||
REGLOAD x9, REG_X9(sp) /* s1 */
|
||||
REGLOAD x10, REG_X10(sp) /* a0 */
|
||||
REGLOAD x11, REG_X11(sp) /* a1 */
|
||||
REGLOAD x12, REG_X12(sp) /* a2 */
|
||||
REGLOAD x13, REG_X13(sp) /* a3 */
|
||||
REGLOAD x14, REG_X14(sp) /* a4 */
|
||||
REGLOAD x15, REG_X15(sp) /* a5 */
|
||||
REGLOAD x16, REG_X16(sp) /* a6 */
|
||||
REGLOAD x17, REG_X17(sp) /* a7 */
|
||||
REGLOAD x18, REG_X18(sp) /* s2 */
|
||||
REGLOAD x19, REG_X19(sp) /* s3 */
|
||||
REGLOAD x20, REG_X20(sp) /* s4 */
|
||||
REGLOAD x21, REG_X21(sp) /* s5 */
|
||||
REGLOAD x22, REG_X22(sp) /* s6 */
|
||||
REGLOAD x23, REG_X23(sp) /* s7 */
|
||||
REGLOAD x24, REG_X24(sp) /* s8 */
|
||||
REGLOAD x25, REG_X25(sp) /* s9 */
|
||||
REGLOAD x26, REG_X26(sp) /* s10 */
|
||||
REGLOAD x27, REG_X27(sp) /* s11 */
|
||||
REGLOAD x28, REG_X28(sp) /* t3 */
|
||||
REGLOAD x29, REG_X29(sp) /* t4 */
|
||||
REGLOAD x30, REG_X30(sp) /* t5 */
|
||||
REGLOAD x31, REG_X31(sp) /* t6 */
|
||||
|
||||
REGLOAD x1, REG_X1(sp) /* ra */
|
||||
|
||||
REGLOAD sp, REG_X2(sp) /* restore original sp */
|
||||
|
||||
/* Return from Machine Interrupt */
|
||||
|
||||
mret
|
||||
|
||||
/************************************************************************************
|
||||
* Name: g_intstackalloc and g_intstacktop
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: g_intstackalloc and g_intstacktop
|
||||
************************************************************************************/
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 15
|
||||
.bss
|
||||
.balign 16
|
||||
.global g_intstackalloc
|
||||
.global g_intstacktop
|
||||
.type g_intstackalloc, object
|
||||
.type g_intstacktop, object
|
||||
g_intstackalloc:
|
||||
#ifndef CONFIG_SMP
|
||||
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 8) & ~15)
|
||||
#else
|
||||
.skip (((CONFIG_ARCH_INTERRUPTSTACK * CONFIG_SMP_NCPUS) + 8) & ~15)
|
||||
#endif
|
||||
g_intstacktop:
|
||||
.size g_intstacktop, 0
|
||||
#ifndef CONFIG_SMP
|
||||
.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~15)
|
||||
#else
|
||||
.size g_intstackalloc, ((CONFIG_ARCH_INTERRUPTSTACK * CONFIG_SMP_NCPUS) & ~15)
|
||||
#endif
|
||||
#endif
|
||||
@ -23,7 +23,7 @@
|
||||
HEAD_ASRC = fe310_head.S
|
||||
|
||||
# Specify our general Assembly files
|
||||
CMN_ASRCS += riscv_vectors.S riscv_testset.S
|
||||
CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
|
||||
|
||||
# Specify C code within the common directory to be included
|
||||
CMN_CSRCS += riscv_initialize.c riscv_swint.c
|
||||
|
||||
@ -33,8 +33,6 @@
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.global exception_common
|
||||
|
||||
/* Imported symbols */
|
||||
|
||||
.extern __trap_vec
|
||||
@ -73,131 +71,3 @@ _fini:
|
||||
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Name: exception_common
|
||||
****************************************************************************/
|
||||
|
||||
exception_common:
|
||||
|
||||
addi sp, sp, -XCPTCONTEXT_SIZE
|
||||
|
||||
sw x1, 1*4(sp) /* ra */
|
||||
sw x3, 3*4(sp) /* gp */
|
||||
sw x4, 4*4(sp) /* tp */
|
||||
sw x5, 5*4(sp) /* t0 */
|
||||
sw x6, 6*4(sp) /* t1 */
|
||||
sw x7, 7*4(sp) /* t2 */
|
||||
sw x8, 8*4(sp) /* s0 */
|
||||
sw x9, 9*4(sp) /* s1 */
|
||||
sw x10, 10*4(sp) /* a0 */
|
||||
sw x11, 11*4(sp) /* a1 */
|
||||
sw x12, 12*4(sp) /* a2 */
|
||||
sw x13, 13*4(sp) /* a3 */
|
||||
sw x14, 14*4(sp) /* a4 */
|
||||
sw x15, 15*4(sp) /* a5 */
|
||||
sw x16, 16*4(sp) /* a6 */
|
||||
sw x17, 17*4(sp) /* a7 */
|
||||
sw x18, 18*4(sp) /* s2 */
|
||||
sw x19, 19*4(sp) /* s3 */
|
||||
sw x20, 20*4(sp) /* s4 */
|
||||
sw x21, 21*4(sp) /* s5 */
|
||||
sw x22, 22*4(sp) /* s6 */
|
||||
sw x23, 23*4(sp) /* s7 */
|
||||
sw x24, 24*4(sp) /* s8 */
|
||||
sw x25, 25*4(sp) /* s9 */
|
||||
sw x26, 26*4(sp) /* s10 */
|
||||
sw x27, 27*4(sp) /* s11 */
|
||||
sw x28, 28*4(sp) /* t3 */
|
||||
sw x29, 29*4(sp) /* t4 */
|
||||
sw x30, 30*4(sp) /* t5 */
|
||||
sw x31, 31*4(sp) /* t6 */
|
||||
|
||||
csrr s0, mstatus
|
||||
sw s0, 32*4(sp) /* mstatus */
|
||||
|
||||
addi s0, sp, XCPTCONTEXT_SIZE
|
||||
sw s0, 2*4(sp) /* original SP */
|
||||
|
||||
/* Setup arg0(exception cause), arg1(context) */
|
||||
|
||||
csrr a0, mcause /* exception cause */
|
||||
csrr s0, mepc
|
||||
sw s0, 0(sp) /* exception PC */
|
||||
|
||||
mv a1, sp /* context = sp */
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 15
|
||||
/* Switch to interrupt stack */
|
||||
|
||||
lui sp, %hi(g_intstacktop)
|
||||
addi sp, sp, %lo(g_intstacktop)
|
||||
#endif
|
||||
|
||||
/* Call interrupt handler in C */
|
||||
|
||||
jal x1, fe310_dispatch_irq
|
||||
|
||||
/* If context switch is needed, return a new sp */
|
||||
|
||||
mv sp, a0
|
||||
lw s0, 0(sp) /* restore mepc */
|
||||
csrw mepc, s0
|
||||
|
||||
lw s0, 32*4(sp) /* restore mstatus */
|
||||
csrw mstatus, s0
|
||||
|
||||
lw x3, 3*4(sp) /* gp */
|
||||
lw x4, 4*4(sp) /* tp */
|
||||
lw x5, 5*4(sp) /* t0 */
|
||||
lw x6, 6*4(sp) /* t1 */
|
||||
lw x7, 7*4(sp) /* t2 */
|
||||
lw x8, 8*4(sp) /* s0 */
|
||||
lw x9, 9*4(sp) /* s1 */
|
||||
lw x10, 10*4(sp) /* a0 */
|
||||
lw x11, 11*4(sp) /* a1 */
|
||||
lw x12, 12*4(sp) /* a2 */
|
||||
lw x13, 13*4(sp) /* a3 */
|
||||
lw x14, 14*4(sp) /* a4 */
|
||||
lw x15, 15*4(sp) /* a5 */
|
||||
lw x16, 16*4(sp) /* a6 */
|
||||
lw x17, 17*4(sp) /* a7 */
|
||||
lw x18, 18*4(sp) /* s2 */
|
||||
lw x19, 19*4(sp) /* s3 */
|
||||
lw x20, 20*4(sp) /* s4 */
|
||||
lw x21, 21*4(sp) /* s5 */
|
||||
lw x22, 22*4(sp) /* s6 */
|
||||
lw x23, 23*4(sp) /* s7 */
|
||||
lw x24, 24*4(sp) /* s8 */
|
||||
lw x25, 25*4(sp) /* s9 */
|
||||
lw x26, 26*4(sp) /* s10 */
|
||||
lw x27, 27*4(sp) /* s11 */
|
||||
lw x28, 28*4(sp) /* t3 */
|
||||
lw x29, 29*4(sp) /* t4 */
|
||||
lw x30, 30*4(sp) /* t5 */
|
||||
lw x31, 31*4(sp) /* t6 */
|
||||
|
||||
lw x1, 1*4(sp) /* ra */
|
||||
|
||||
lw sp, 2*4(sp) /* restore original sp */
|
||||
|
||||
/* Return from Machine Interrupt */
|
||||
|
||||
mret
|
||||
|
||||
/************************************************************************************
|
||||
* Name: g_intstackalloc and g_intstacktop
|
||||
************************************************************************************/
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 15
|
||||
.bss
|
||||
.balign 16
|
||||
.global g_intstackalloc
|
||||
.global g_intstacktop
|
||||
.type g_intstackalloc, object
|
||||
.type g_intstacktop, object
|
||||
g_intstackalloc:
|
||||
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 8) & ~15)
|
||||
g_intstacktop:
|
||||
.size g_intstacktop, 0
|
||||
.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~15)
|
||||
#endif
|
||||
|
||||
@ -49,10 +49,10 @@ volatile uintptr_t *g_current_regs[1];
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* fe310_dispatch_irq
|
||||
* riscv_dispatch_irq
|
||||
****************************************************************************/
|
||||
|
||||
void *fe310_dispatch_irq(uintptr_t vector, uintptr_t *regs)
|
||||
void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
|
||||
{
|
||||
uintptr_t irq = (vector >> 27) | (vector & 0xf);
|
||||
uintptr_t *mepc = regs;
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
HEAD_ASRC = k210_head.S
|
||||
|
||||
# Specify our general Assembly files
|
||||
CMN_ASRCS += riscv_vectors.S riscv_testset.S
|
||||
CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
|
||||
|
||||
# Specify C code within the common directory to be included
|
||||
CMN_CSRCS += riscv_initialize.c riscv_swint.c
|
||||
|
||||
@ -33,8 +33,6 @@
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.global exception_common
|
||||
|
||||
/* Imported symbols */
|
||||
|
||||
.extern __trap_vec
|
||||
@ -87,160 +85,3 @@ _fini:
|
||||
/* These don't have to do anything since we use init_array/fini_array. */
|
||||
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Name: exception_common
|
||||
****************************************************************************/
|
||||
|
||||
exception_common:
|
||||
|
||||
#if 0
|
||||
csrr gp, mcause /* exception cause */
|
||||
addi tp, zero, 10 /* 10 = machine ecall */
|
||||
bgtu gp, tp, normal_irq
|
||||
ld sp, g_fstack_top /* Set sp to fault stack */
|
||||
|
||||
normal_irq:
|
||||
addi gp, zero, 0 /* clear */
|
||||
#endif
|
||||
|
||||
addi sp, sp, -XCPTCONTEXT_SIZE
|
||||
|
||||
sd x1, 1*8(sp) /* ra */
|
||||
sd x3, 3*8(sp) /* gp */
|
||||
sd x4, 4*8(sp) /* tp */
|
||||
sd x5, 5*8(sp) /* t0 */
|
||||
sd x6, 6*8(sp) /* t1 */
|
||||
sd x7, 7*8(sp) /* t2 */
|
||||
sd x8, 8*8(sp) /* s0 */
|
||||
sd x9, 9*8(sp) /* s1 */
|
||||
sd x10, 10*8(sp) /* a0 */
|
||||
sd x11, 11*8(sp) /* a1 */
|
||||
sd x12, 12*8(sp) /* a2 */
|
||||
sd x13, 13*8(sp) /* a3 */
|
||||
sd x14, 14*8(sp) /* a4 */
|
||||
sd x15, 15*8(sp) /* a5 */
|
||||
sd x16, 16*8(sp) /* a6 */
|
||||
sd x17, 17*8(sp) /* a7 */
|
||||
sd x18, 18*8(sp) /* s2 */
|
||||
sd x19, 19*8(sp) /* s3 */
|
||||
sd x20, 20*8(sp) /* s4 */
|
||||
sd x21, 21*8(sp) /* s5 */
|
||||
sd x22, 22*8(sp) /* s6 */
|
||||
sd x23, 23*8(sp) /* s7 */
|
||||
sd x24, 24*8(sp) /* s8 */
|
||||
sd x25, 25*8(sp) /* s9 */
|
||||
sd x26, 26*8(sp) /* s10 */
|
||||
sd x27, 27*8(sp) /* s11 */
|
||||
sd x28, 28*8(sp) /* t3 */
|
||||
sd x29, 29*8(sp) /* t4 */
|
||||
sd x30, 30*8(sp) /* t5 */
|
||||
sd x31, 31*8(sp) /* t6 */
|
||||
|
||||
csrr s0, mstatus
|
||||
sd s0, 32*8(sp) /* mstatus */
|
||||
|
||||
addi s0, sp, XCPTCONTEXT_SIZE
|
||||
sd s0, 2*8(sp) /* original SP */
|
||||
|
||||
/* Setup arg0(exception cause), arg1(context) */
|
||||
|
||||
csrr a0, mcause /* exception cause */
|
||||
csrr s0, mepc
|
||||
sd s0, 0(sp) /* exception PC */
|
||||
|
||||
mv a1, sp /* context = sp */
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 15
|
||||
/* Load mhartid (cpuid) */
|
||||
|
||||
csrr s0, mhartid
|
||||
|
||||
/* Switch to interrupt stack */
|
||||
|
||||
bnez s0, 3f
|
||||
la sp, g_intstacktop
|
||||
j 4f
|
||||
3:
|
||||
la sp, g_intstacktop
|
||||
addi sp, sp, -(CONFIG_ARCH_INTERRUPTSTACK & ~15)
|
||||
4:
|
||||
|
||||
#endif
|
||||
|
||||
/* Call interrupt handler in C */
|
||||
|
||||
jal x1, k210_dispatch_irq
|
||||
|
||||
/* If context switch is needed, return a new sp */
|
||||
|
||||
mv sp, a0
|
||||
ld s0, 0(sp) /* restore mepc */
|
||||
csrw mepc, s0
|
||||
|
||||
ld s0, 32*8(sp) /* restore mstatus */
|
||||
csrw mstatus, s0
|
||||
|
||||
ld x3, 3*8(sp) /* gp */
|
||||
ld x4, 4*8(sp) /* tp */
|
||||
ld x5, 5*8(sp) /* t0 */
|
||||
ld x6, 6*8(sp) /* t1 */
|
||||
ld x7, 7*8(sp) /* t2 */
|
||||
ld x8, 8*8(sp) /* s0 */
|
||||
ld x9, 9*8(sp) /* s1 */
|
||||
ld x10, 10*8(sp) /* a0 */
|
||||
ld x11, 11*8(sp) /* a1 */
|
||||
ld x12, 12*8(sp) /* a2 */
|
||||
ld x13, 13*8(sp) /* a3 */
|
||||
ld x14, 14*8(sp) /* a4 */
|
||||
ld x15, 15*8(sp) /* a5 */
|
||||
ld x16, 16*8(sp) /* a6 */
|
||||
ld x17, 17*8(sp) /* a7 */
|
||||
ld x18, 18*8(sp) /* s2 */
|
||||
ld x19, 19*8(sp) /* s3 */
|
||||
ld x20, 20*8(sp) /* s4 */
|
||||
ld x21, 21*8(sp) /* s5 */
|
||||
ld x22, 22*8(sp) /* s6 */
|
||||
ld x23, 23*8(sp) /* s7 */
|
||||
ld x24, 24*8(sp) /* s8 */
|
||||
ld x25, 25*8(sp) /* s9 */
|
||||
ld x26, 26*8(sp) /* s10 */
|
||||
ld x27, 27*8(sp) /* s11 */
|
||||
ld x28, 28*8(sp) /* t3 */
|
||||
ld x29, 29*8(sp) /* t4 */
|
||||
ld x30, 30*8(sp) /* t5 */
|
||||
ld x31, 31*8(sp) /* t6 */
|
||||
|
||||
ld x1, 1*8(sp) /* ra */
|
||||
|
||||
ld sp, 2*8(sp) /* restore original sp */
|
||||
|
||||
/* Return from Machine Interrupt */
|
||||
|
||||
mret
|
||||
|
||||
/************************************************************************************
|
||||
* Name: g_intstackalloc and g_intstacktop
|
||||
************************************************************************************/
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 15
|
||||
.bss
|
||||
.balign 16
|
||||
.global g_intstackalloc
|
||||
.global g_intstacktop
|
||||
.type g_intstackalloc, object
|
||||
.type g_intstacktop, object
|
||||
g_intstackalloc:
|
||||
#ifndef CONFIG_SMP
|
||||
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 8) & ~15)
|
||||
#else
|
||||
.skip (((CONFIG_ARCH_INTERRUPTSTACK * CONFIG_SMP_NCPUS) + 8) & ~15)
|
||||
#endif
|
||||
g_intstacktop:
|
||||
.size g_intstacktop, 0
|
||||
#ifndef CONFIG_SMP
|
||||
.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~15)
|
||||
#else
|
||||
.size g_intstackalloc, ((CONFIG_ARCH_INTERRUPTSTACK * CONFIG_SMP_NCPUS) & ~15)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
@ -48,10 +48,10 @@ extern void up_fault(int irq, uintptr_t *regs);
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* k210_dispatch_irq
|
||||
* riscv_dispatch_irq
|
||||
****************************************************************************/
|
||||
|
||||
void *k210_dispatch_irq(uintptr_t vector, uintptr_t *regs)
|
||||
void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
|
||||
{
|
||||
uintptr_t irq = (vector >> (27 + 32)) | (vector & 0xf);
|
||||
uintptr_t *mepc = regs;
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
HEAD_ASRC = litex_head.S
|
||||
|
||||
# Specify our general Assembly files
|
||||
CMN_ASRCS += riscv_vectors.S riscv_testset.S
|
||||
CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
|
||||
|
||||
# Specify C code within the common directory to be included
|
||||
CMN_CSRCS += riscv_initialize.c riscv_swint.c
|
||||
|
||||
@ -31,8 +31,6 @@
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.global exception_common
|
||||
|
||||
/* Imported symbols */
|
||||
|
||||
.extern __trap_vec
|
||||
@ -72,132 +70,3 @@ _fini:
|
||||
/* These don't have to do anything since we use init_array/fini_array. */
|
||||
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Name: exception_common
|
||||
****************************************************************************/
|
||||
|
||||
exception_common:
|
||||
|
||||
addi sp, sp, -XCPTCONTEXT_SIZE
|
||||
|
||||
sw x1, 1*4(sp) /* ra */
|
||||
sw x3, 3*4(sp) /* gp */
|
||||
sw x4, 4*4(sp) /* tp */
|
||||
sw x5, 5*4(sp) /* t0 */
|
||||
sw x6, 6*4(sp) /* t1 */
|
||||
sw x7, 7*4(sp) /* t2 */
|
||||
sw x8, 8*4(sp) /* s0 */
|
||||
sw x9, 9*4(sp) /* s1 */
|
||||
sw x10, 10*4(sp) /* a0 */
|
||||
sw x11, 11*4(sp) /* a1 */
|
||||
sw x12, 12*4(sp) /* a2 */
|
||||
sw x13, 13*4(sp) /* a3 */
|
||||
sw x14, 14*4(sp) /* a4 */
|
||||
sw x15, 15*4(sp) /* a5 */
|
||||
sw x16, 16*4(sp) /* a6 */
|
||||
sw x17, 17*4(sp) /* a7 */
|
||||
sw x18, 18*4(sp) /* s2 */
|
||||
sw x19, 19*4(sp) /* s3 */
|
||||
sw x20, 20*4(sp) /* s4 */
|
||||
sw x21, 21*4(sp) /* s5 */
|
||||
sw x22, 22*4(sp) /* s6 */
|
||||
sw x23, 23*4(sp) /* s7 */
|
||||
sw x24, 24*4(sp) /* s8 */
|
||||
sw x25, 25*4(sp) /* s9 */
|
||||
sw x26, 26*4(sp) /* s10 */
|
||||
sw x27, 27*4(sp) /* s11 */
|
||||
sw x28, 28*4(sp) /* t3 */
|
||||
sw x29, 29*4(sp) /* t4 */
|
||||
sw x30, 30*4(sp) /* t5 */
|
||||
sw x31, 31*4(sp) /* t6 */
|
||||
|
||||
csrr s0, mstatus
|
||||
sw s0, 32*4(sp) /* mstatus */
|
||||
|
||||
addi s0, sp, XCPTCONTEXT_SIZE
|
||||
sw s0, 2*4(sp) /* original SP */
|
||||
|
||||
/* Setup arg0(exception cause), arg1(context) */
|
||||
|
||||
csrr a0, mcause /* exception cause */
|
||||
csrr s0, mepc
|
||||
sw s0, 0(sp) /* exception PC */
|
||||
|
||||
mv a1, sp /* context = sp */
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 15
|
||||
/* Switch to interrupt stack */
|
||||
|
||||
lui sp, %hi(g_intstacktop)
|
||||
addi sp, sp, %lo(g_intstacktop)
|
||||
#endif
|
||||
|
||||
/* Call interrupt handler in C */
|
||||
|
||||
jal x1, litex_dispatch_irq
|
||||
|
||||
/* If context switch is needed, return a new sp */
|
||||
|
||||
mv sp, a0
|
||||
lw s0, 0(sp) /* restore mepc */
|
||||
csrw mepc, s0
|
||||
|
||||
lw s0, 32*4(sp) /* restore mstatus */
|
||||
csrw mstatus, s0
|
||||
|
||||
lw x3, 3*4(sp) /* gp */
|
||||
lw x4, 4*4(sp) /* tp */
|
||||
lw x5, 5*4(sp) /* t0 */
|
||||
lw x6, 6*4(sp) /* t1 */
|
||||
lw x7, 7*4(sp) /* t2 */
|
||||
lw x8, 8*4(sp) /* s0 */
|
||||
lw x9, 9*4(sp) /* s1 */
|
||||
lw x10, 10*4(sp) /* a0 */
|
||||
lw x11, 11*4(sp) /* a1 */
|
||||
lw x12, 12*4(sp) /* a2 */
|
||||
lw x13, 13*4(sp) /* a3 */
|
||||
lw x14, 14*4(sp) /* a4 */
|
||||
lw x15, 15*4(sp) /* a5 */
|
||||
lw x16, 16*4(sp) /* a6 */
|
||||
lw x17, 17*4(sp) /* a7 */
|
||||
lw x18, 18*4(sp) /* s2 */
|
||||
lw x19, 19*4(sp) /* s3 */
|
||||
lw x20, 20*4(sp) /* s4 */
|
||||
lw x21, 21*4(sp) /* s5 */
|
||||
lw x22, 22*4(sp) /* s6 */
|
||||
lw x23, 23*4(sp) /* s7 */
|
||||
lw x24, 24*4(sp) /* s8 */
|
||||
lw x25, 25*4(sp) /* s9 */
|
||||
lw x26, 26*4(sp) /* s10 */
|
||||
lw x27, 27*4(sp) /* s11 */
|
||||
lw x28, 28*4(sp) /* t3 */
|
||||
lw x29, 29*4(sp) /* t4 */
|
||||
lw x30, 30*4(sp) /* t5 */
|
||||
lw x31, 31*4(sp) /* t6 */
|
||||
|
||||
lw x1, 1*4(sp) /* ra */
|
||||
|
||||
lw sp, 2*4(sp) /* restore original sp */
|
||||
|
||||
/* Return from Machine Interrupt */
|
||||
|
||||
mret
|
||||
|
||||
/************************************************************************************
|
||||
* Name: g_intstackalloc and g_intstacktop
|
||||
************************************************************************************/
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 15
|
||||
.bss
|
||||
.balign 16
|
||||
.global g_intstackalloc
|
||||
.global g_intstacktop
|
||||
.type g_intstackalloc, object
|
||||
.type g_intstacktop, object
|
||||
g_intstackalloc:
|
||||
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 8) & ~15)
|
||||
g_intstacktop:
|
||||
.size g_intstacktop, 0
|
||||
.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~15)
|
||||
#endif
|
||||
|
||||
@ -48,10 +48,10 @@ volatile uintptr_t *g_current_regs[1];
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* litex_dispatch_irq
|
||||
* riscv_dispatch_irq
|
||||
****************************************************************************/
|
||||
|
||||
void *litex_dispatch_irq(uintptr_t vector, uintptr_t *regs)
|
||||
void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
|
||||
{
|
||||
uintptr_t irq = (vector >> 27) | (vector & 0xf);
|
||||
uintptr_t *mepc = regs;
|
||||
|
||||
@ -23,7 +23,7 @@
|
||||
HEAD_ASRC = qemu_rv32_head.S
|
||||
|
||||
# Specify our general Assembly files
|
||||
CMN_ASRCS += riscv_vectors.S riscv_testset.S
|
||||
CMN_ASRCS += riscv_vectors.S riscv_testset.S riscv_exception_common.S
|
||||
|
||||
# Specify C code within the common directory to be included
|
||||
CMN_CSRCS += riscv_initialize.c riscv_swint.c
|
||||
|
||||
@ -33,10 +33,8 @@
|
||||
|
||||
/* Exported Symbols */
|
||||
|
||||
.global exception_common
|
||||
.global __start
|
||||
|
||||
.section .text
|
||||
.global __start
|
||||
|
||||
__start:
|
||||
|
||||
@ -65,133 +63,3 @@ _fini:
|
||||
/* These don't have to do anything since we use init_array/fini_array. */
|
||||
|
||||
ret
|
||||
|
||||
/****************************************************************************
|
||||
* Name: exception_common
|
||||
****************************************************************************/
|
||||
|
||||
exception_common:
|
||||
|
||||
addi sp, sp, -XCPTCONTEXT_SIZE
|
||||
|
||||
sw x1, 1*4(sp) /* ra */
|
||||
sw x3, 3*4(sp) /* gp */
|
||||
sw x4, 4*4(sp) /* tp */
|
||||
sw x5, 5*4(sp) /* t0 */
|
||||
sw x6, 6*4(sp) /* t1 */
|
||||
sw x7, 7*4(sp) /* t2 */
|
||||
sw x8, 8*4(sp) /* s0 */
|
||||
sw x9, 9*4(sp) /* s1 */
|
||||
sw x10, 10*4(sp) /* a0 */
|
||||
sw x11, 11*4(sp) /* a1 */
|
||||
sw x12, 12*4(sp) /* a2 */
|
||||
sw x13, 13*4(sp) /* a3 */
|
||||
sw x14, 14*4(sp) /* a4 */
|
||||
sw x15, 15*4(sp) /* a5 */
|
||||
sw x16, 16*4(sp) /* a6 */
|
||||
sw x17, 17*4(sp) /* a7 */
|
||||
sw x18, 18*4(sp) /* s2 */
|
||||
sw x19, 19*4(sp) /* s3 */
|
||||
sw x20, 20*4(sp) /* s4 */
|
||||
sw x21, 21*4(sp) /* s5 */
|
||||
sw x22, 22*4(sp) /* s6 */
|
||||
sw x23, 23*4(sp) /* s7 */
|
||||
sw x24, 24*4(sp) /* s8 */
|
||||
sw x25, 25*4(sp) /* s9 */
|
||||
sw x26, 26*4(sp) /* s10 */
|
||||
sw x27, 27*4(sp) /* s11 */
|
||||
sw x28, 28*4(sp) /* t3 */
|
||||
sw x29, 29*4(sp) /* t4 */
|
||||
sw x30, 30*4(sp) /* t5 */
|
||||
sw x31, 31*4(sp) /* t6 */
|
||||
|
||||
csrr s0, mstatus
|
||||
sw s0, 32*4(sp) /* mstatus */
|
||||
|
||||
addi s0, sp, XCPTCONTEXT_SIZE
|
||||
sw s0, 2*4(sp) /* original SP */
|
||||
|
||||
/* Setup arg0(exception cause), arg1(context) */
|
||||
|
||||
csrr a0, mcause /* exception cause */
|
||||
csrr s0, mepc
|
||||
sw s0, 0(sp) /* exception PC */
|
||||
|
||||
mv a1, sp /* context = sp */
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 15
|
||||
/* Switch to interrupt stack */
|
||||
|
||||
lui sp, %hi(g_intstacktop)
|
||||
addi sp, sp, %lo(g_intstacktop)
|
||||
#endif
|
||||
|
||||
/* Call interrupt handler in C */
|
||||
|
||||
jal x1, qemu_rv32_dispatch_irq
|
||||
|
||||
/* If context switch is needed, return a new sp */
|
||||
|
||||
mv sp, a0
|
||||
lw s0, 0(sp) /* restore mepc */
|
||||
csrw mepc, s0
|
||||
|
||||
lw s0, 32*4(sp) /* restore mstatus */
|
||||
csrw mstatus, s0
|
||||
|
||||
lw x3, 3*4(sp) /* gp */
|
||||
lw x4, 4*4(sp) /* tp */
|
||||
lw x5, 5*4(sp) /* t0 */
|
||||
lw x6, 6*4(sp) /* t1 */
|
||||
lw x7, 7*4(sp) /* t2 */
|
||||
lw x8, 8*4(sp) /* s0 */
|
||||
lw x9, 9*4(sp) /* s1 */
|
||||
lw x10, 10*4(sp) /* a0 */
|
||||
lw x11, 11*4(sp) /* a1 */
|
||||
lw x12, 12*4(sp) /* a2 */
|
||||
lw x13, 13*4(sp) /* a3 */
|
||||
lw x14, 14*4(sp) /* a4 */
|
||||
lw x15, 15*4(sp) /* a5 */
|
||||
lw x16, 16*4(sp) /* a6 */
|
||||
lw x17, 17*4(sp) /* a7 */
|
||||
lw x18, 18*4(sp) /* s2 */
|
||||
lw x19, 19*4(sp) /* s3 */
|
||||
lw x20, 20*4(sp) /* s4 */
|
||||
lw x21, 21*4(sp) /* s5 */
|
||||
lw x22, 22*4(sp) /* s6 */
|
||||
lw x23, 23*4(sp) /* s7 */
|
||||
lw x24, 24*4(sp) /* s8 */
|
||||
lw x25, 25*4(sp) /* s9 */
|
||||
lw x26, 26*4(sp) /* s10 */
|
||||
lw x27, 27*4(sp) /* s11 */
|
||||
lw x28, 28*4(sp) /* t3 */
|
||||
lw x29, 29*4(sp) /* t4 */
|
||||
lw x30, 30*4(sp) /* t5 */
|
||||
lw x31, 31*4(sp) /* t6 */
|
||||
|
||||
lw x1, 1*4(sp) /* ra */
|
||||
|
||||
lw sp, 2*4(sp) /* restore original sp */
|
||||
|
||||
/* Return from Machine Interrupt */
|
||||
|
||||
mret
|
||||
|
||||
/*******************************************************************************
|
||||
* Name: g_intstackalloc and g_intstacktop
|
||||
*******************************************************************************/
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 15
|
||||
.bss
|
||||
.balign 16
|
||||
.global g_intstackalloc
|
||||
.global g_intstacktop
|
||||
.type g_intstackalloc, object
|
||||
.type g_intstacktop, object
|
||||
g_intstackalloc:
|
||||
.skip ((CONFIG_ARCH_INTERRUPTSTACK + 8) & ~15)
|
||||
g_intstacktop:
|
||||
.skip 4
|
||||
.size g_intstacktop, 4
|
||||
.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~15)
|
||||
#endif
|
||||
|
||||
@ -49,10 +49,10 @@ volatile uintptr_t *g_current_regs[1];
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* qemu_rv32_dispatch_irq
|
||||
* riscv_dispatch_irq
|
||||
****************************************************************************/
|
||||
|
||||
void *qemu_rv32_dispatch_irq(uintptr_t vector, uintptr_t *regs)
|
||||
void *riscv_dispatch_irq(uintptr_t vector, uintptr_t *regs)
|
||||
{
|
||||
uintptr_t irq = (vector >> 27) | (vector & 0xf);
|
||||
uintptr_t *mepc = regs;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user