Add exception handling basics
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2990 42af7a65-404d-4744-a932-0658087f49c3
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@ -1300,5 +1300,5 @@
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* include/stdlib.h, lib/Makefile, lib/lib_abs.c, lib/lib_labs.c,
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lib_labs.c, lib_llabs.c, lib_imaxabs.c - Add abs(), labs(), llabs(), and
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imaxabs().
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* Add include/inttypes.h
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@ -66,24 +66,24 @@
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#define AVR32_IRQ_UNREC 0 /* EVBA+0x00 Unrecoverable exception */
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#define AVR32_IRQ_TLBMULT 1 /* EVBA+0x04 TLB multiple hit */
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#define AVR32_IRQ_BUSDATA 2 /* EVBA+0x08 Bus error data fetch */
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#define AVR32_IRQ_BUSINST 3 /* EVBA+0x0C Bus error instruction fetch */
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#define AVR32_IRQ_BUSINST 3 /* EVBA+0x0c Bus error instruction fetch */
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#define AVR32_IRQ_NMI 4 /* EVBA+0x10 NMI */
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#define AVR32_IRQ_INSTADDR 5 /* EVBA+0x14 Instruction Address */
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#define AVR32_IRQ_ITLBMISS 6 /* EVBA+0x50 ITLB Miss */
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#define AVR32_IRQ_ITLBPROT 7 /* EVBA+0x18 ITLB Protection */
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#define AVR32_IRQ_BP 8 /* EVBA+0x1C Breakpoint */
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#define AVR32_IRQ_INVINST 9 /* EVBA+0x20 Illegal Opcode */
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#define AVR32_IRQ_UNIMPINST 10 /* EVBA+0x24 Unimplemented instruction */
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#define AVR32_IRQ_PRIV 11 /* EVBA+0x28 Privilege violation */
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#define AVR32_IRQ_FP 12 /* EVBA+0x2C Floating-point */
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#define AVR32_IRQ_COP 13 /* EVBA+0x30 Coprocessor absent */
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#define AVR32_IRQ_RDDATA 14 /* EVBA+0x34 Data Address (Read) */
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#define AVR32_IRQ_WRDATA 15 /* EVBA+0x38 Data Address (Write) */
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#define AVR32_IRQ_RDDTLB 16 /* EVBA+0x60 DTLB Miss (Read) */
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#define AVR32_IRQ_WRDTLB 17 /* EVBA+0x70 DTLB Miss (Write) */
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#define AVR32_IRQ_RDDTLBPROT 18 /* EVBA+0x3C DTLB Protection (Read) */
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#define AVR32_IRQ_WRDTLBPROT 19 /* EVBA+0x40 DTLB Protection (Write) */
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#define AVR32_IRQ_DLTBMOD 20 /* EVBA+0x44 DTLB Modified */
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#define AVR32_IRQ_ITLBPROT 6 /* EVBA+0x18 ITLB Protection */
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#define AVR32_IRQ_BP 7 /* EVBA+0x1c Breakpoint */
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#define AVR32_IRQ_INVINST 8 /* EVBA+0x20 Illegal Opcode */
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#define AVR32_IRQ_UNIMPINST 9 /* EVBA+0x24 Unimplemented instruction */
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#define AVR32_IRQ_PRIV 10 /* EVBA+0x28 Privilege violation */
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#define AVR32_IRQ_FP 11 /* EVBA+0x2c Floating-point */
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#define AVR32_IRQ_COP 12 /* EVBA+0x30 Coprocessor absent */
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#define AVR32_IRQ_RDDATA 13 /* EVBA+0x34 Data Address (Read) */
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#define AVR32_IRQ_WRDATA 14 /* EVBA+0x38 Data Address (Write) */
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#define AVR32_IRQ_RDDTLBPROT 15 /* EVBA+0x3c DTLB Protection (Read) */
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#define AVR32_IRQ_WRDTLBPROT 16 /* EVBA+0x40 DTLB Protection (Write) */
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#define AVR32_IRQ_DLTBMOD 17 /* EVBA+0x44 DTLB Modified */
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#define AVR32_IRQ_ITLBMISS 18 /* EVBA+0x50 ITLB Miss */
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#define AVR32_IRQ_RDDTLB 19 /* EVBA+0x60 DTLB Miss (Read) */
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#define AVR32_IRQ_WRDTLB 20 /* EVBA+0x70 DTLB Miss (Write) */
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#define AVR32_IRQ_SUPER 21 /* EVBA+0x100 Supervisor call */
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#define AVR32_IRQ_NEVENTS 22
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@ -219,6 +219,7 @@
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/* Total number of IRQ numbers */
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#define AVR32_IRQ_BADVECTOR 61 /* Not a real IRQ number */
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#define NR_IRQS 61
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/****************************************************************************
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@ -39,7 +39,7 @@ HEAD_ASRC = up_nommuhead.S
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# Common AVR/AVR32 files
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CMN_ASRCS =
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CMN_ASRCS = up_exceptions.S
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CMN_CSRCS = up_assert.c up_allocateheap.c up_blocktask.c up_copystate.c \
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up_createstack.c up_mdelay.c up_udelay.c up_exit.c up_idle.c \
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up_initialize.c up_initialstate.c up_interruptcontext.c \
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209
arch/avr/src/avr32/up_exceptions.S
Executable file
209
arch/avr/src/avr32/up_exceptions.S
Executable file
@ -0,0 +1,209 @@
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/****************************************************************************
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* arch/avr32/src/avr32/up_exceptions.S
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/avr32/avr32.h>
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#include "up_internal.h"
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#include "up_arch.h"
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/****************************************************************************
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* External Symbols
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****************************************************************************/
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.global avr32_getirqno
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/****************************************************************************
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* Macros
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****************************************************************************/
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#warning "Missing Logic"
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.macro HANDLER, label, irqno
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\label:
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rjmp avr32_excptcommon /* FIXME!!! Need IRQ in a register */
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.endm
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/****************************************************************************
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* Exception Vector Table
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****************************************************************************/
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/* The Exception Vector Base Address (EVBA) register will contain "a pointer
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* to the exception routines. All exception routines start at this address,
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* or at a defined offset relative to the address. Special alignment
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* requirements may apply for EVBA, depending on the implementation of the
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* interrupt controller."
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*/
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/* REVISIT: This alignment requirement may be different on other AVR32s */
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.text
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.balign 0x200
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.global vectortab
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.type vectortab, @function
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vectortab:
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lda.w pc, avr32_unrec /* EVBA+0x00 Unrecoverable exception */
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lda.w pc, avr32_tlbmult /* EVBA+0x04 TLB multiple hit */
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lda.w pc, avr32_busdata /* EVBA+0x08 Bus error data fetch */
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lda.w pc, avr32_businst /* EVBA+0x0c Bus error instruction fetch */
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lda.w pc, avr32_nmi /* EVBA+0x10 NMI */
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lda.w pc, avr32_instaddr /* EVBA+0x14 Instruction Address */
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lda.w pc, avr32_itlbrot /* EVBA+0x18 ITLB Protection */
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lda.w pc, avr32_bp /* EVBA+0x1c Breakpoint */
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lda.w pc, avr32_invinst /* EVBA+0x20 Illegal Opcode */
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lda.w pc, avr32_unimpinst /* EVBA+0x24 Unimplemented instruction */
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lda.w pc, avr32_priv /* EVBA+0x28 Privilege violation */
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lda.w pc, avr32_fp /* EVBA+0x2c Floating-point */
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lda.w pc, avr32_cop /* EVBA+0x30 Coprocessor absent */
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lda.w pc, avr32_rddata /* EVBA+0x34 Data Address (Read) */
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lda.w pc, avr32_wrdata /* EVBA+0x38 Data Address (Write) */
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lda.w pc, avr32_tddtlbprot /* EVBA+0x3c DTLB Protection (Read) */
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lda.w pc, avr32_wrdtlbprot /* EVBA+0x40 DTLB Protection (Write) */
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lda.w pc, avr32_dltbmod /* EVBA+0x44 DTLB Modified */
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.rept 2
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lda.w pc, avr32_badvector /* EVBA+0x48-0x4c No such vector */
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.endr
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lda.w pc, avr32_itlbmiss /* EVBA+0x50 ITLB Miss */
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.rept 3
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lda.w pc, avr32_badvector /* EVBA+0x54-0x5c No such vector */
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.endr
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lda.w pc, avr32_rddtlb /* EVBA+0x60 DTLB Miss (Read) */
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.rept 3
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lda.w pc, avr32_badvector /* EVBA+0x64-0x6c No such vector */
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.endr
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lda.w pc, avr32_wrdtlb /* EVBA+0x70 DTLB Miss (Write) */
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.rept (3+4*8)
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lda.w pc, avr32_badvector /* EVBA+0x74-0xfc No such vector */
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.endr
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lda.w pc, avr32_super /* EVBA+0x100 Supervisor call */
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/****************************************************************************
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* Interrupts
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****************************************************************************/
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/* The interrupt controller must provide an address that is relative to the
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* the EVBA so it is natural to define these interrupt vectors just after
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* the exception table.
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* On entry to each interrupt handler, R8-R12, LR, PC and SR have already been
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* pushed onto the system stack by the MCU.
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*/
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.balign 4
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avr32_int0:
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mov r12, 0 /* r12=interrupt level parameter */
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rjmp avr32_intcommon /* Jump to common interrupt logic */
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.balign 4
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avr32_int1:
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mov r12, 1 /* r12=interrupt level parameter */
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rjmp avr32_intcommon /* Jump to common interrupt logic */
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.balign 4
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avr32_int2:
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mov r12, 2 /* r12=interrupt level parameter */
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rjmp avr32_intcommon /* Jump to common interrupt logic */
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avr32_int3:
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mov r12, 2 /* r12=interrupt level parameter */
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/* Common interrupt handling logic */
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avr32_intcommon:
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call avr32_getirqno /* Get the IRQ number of the interrupt to process */
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rjmp avr32_common /* Then go to the common exception handling logic */
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/****************************************************************************
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* Exception Vector Handlers
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****************************************************************************/
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/* Exception Handlers */
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HANDLER avr32_unrec, AVR32_IRQ_UNREC /* Unrecoverable exception */
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HANDLER avr32_tlbmult, AVR32_IRQ_TLBMULT /* TLB multiple hit */
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HANDLER avr32_busdata, AVR32_IRQ_BUSDATA /* Bus error data fetch */
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HANDLER avr32_businst, AVR32_IRQ_BUSINST /* Bus error instruction fetch */
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HANDLER avr32_nmi, AVR32_IRQ_NMI /* NMI */
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HANDLER avr32_instaddr, AVR32_IRQ_INSTADDR /* Instruction Address */
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HANDLER avr32_itlbrot, AVR32_IRQ_ITLBPROT /* ITLB Protection */
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HANDLER avr32_bp, AVR32_IRQ_BP /* Breakpoint */
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HANDLER avr32_invinst, AVR32_IRQ_INVINST /* Illegal Opcode */
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HANDLER avr32_unimpinst, AVR32_IRQ_UNIMPINST /* Unimplemented instruction */
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HANDLER avr32_priv, AVR32_IRQ_PRIV /* Privilege violation */
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HANDLER avr32_fp, AVR32_IRQ_FP /* Floating-point */
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HANDLER avr32_cop, AVR32_IRQ_COP /* Coprocessor absent */
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HANDLER avr32_rddata, AVR32_IRQ_RDDATA /* Data Address (Read) */
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HANDLER avr32_wrdata, AVR32_IRQ_WRDATA /* Data Address (Write) */
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HANDLER avr32_tddtlbprot, AVR32_IRQ_RDDTLBPROT /* DTLB Protection (Read) */
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HANDLER avr32_wrdtlbprot, AVR32_IRQ_WRDTLBPROT /* DTLB Protection (Write) */
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HANDLER avr32_dltbmod, AVR32_IRQ_DLTBMOD /* DTLB Modified */
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HANDLER avr32_itlbmiss, AVR32_IRQ_ITLBMISS /* ITLB Miss */
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HANDLER avr32_rddtlb, AVR32_IRQ_RDDTLB /* DTLB Miss (Read) */
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HANDLER avr32_wrdtlb, AVR32_IRQ_WRDTLB /* DTLB Miss (Write) */
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HANDLER avr32_super, AVR32_IRQ_SUPER /* Supervisor call */
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HANDLER avr32_badvector, AVR32_IRQ_BADVECTOR /* No such vector */
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/* Common exception handling logic. Unlike the interrupt handlers, the
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* exception handlers do not save R8-R12, and LR on the stack. Only the PC
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* and SR have been pushed onto the system stack by the MCU. The following
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* loic creates a common stack frame for exception handlers prior to joining
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* to the common interrupt/exception logic below.
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*/
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avr32_excptcommon:
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#warning "Missing Logic"
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/****************************************************************************
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* Common Event Handling Logic
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****************************************************************************/
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/* After this point, logic to manage interrupts and exceptions is equivalent.
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* Here we have:
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*
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* R8-R12, LR, SR, and the PC on the stack.
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* R12 holds the IRQ number to be dispatched.
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*
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* This function will finish construction of the register save structure and
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* call the IRQ dispatching logic.
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*/
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avr32_common:
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#warning "Missing Logic"
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rjmp $
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.end
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@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/avr32/src/arm/up_nommuhead.S
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* arch/avr32/src/avr32/up_nommuhead.S
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*
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* Copyright (C) 2010 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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