From c6d2d6af88f38e2383360c1ab337a3d6db483a74 Mon Sep 17 00:00:00 2001 From: patacongo Date: Mon, 10 Oct 2011 02:11:08 +0000 Subject: [PATCH] Starting support for PICMX324xx/5xx/7xx and PIC32 Ethernet Starter Kit git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4033 42af7a65-404d-4744-a932-0658087f49c3 --- arch/mips/src/pic32mx/Make.defs | 0 arch/mips/src/pic32mx/chip.h | 1875 +++++++++++++++------ arch/mips/src/pic32mx/excptmacros.h | 0 arch/mips/src/pic32mx/pic32mx-adc.h | 0 arch/mips/src/pic32mx/pic32mx-bmx.h | 0 arch/mips/src/pic32mx/pic32mx-che.h | 0 arch/mips/src/pic32mx/pic32mx-cm.h | 0 arch/mips/src/pic32mx/pic32mx-config.h | 0 arch/mips/src/pic32mx/pic32mx-cvr.h | 0 arch/mips/src/pic32mx/pic32mx-ddp.h | 0 arch/mips/src/pic32mx/pic32mx-devcfg.h | 0 arch/mips/src/pic32mx/pic32mx-dma.h | 0 arch/mips/src/pic32mx/pic32mx-flash.h | 0 arch/mips/src/pic32mx/pic32mx-i2c.h | 0 arch/mips/src/pic32mx/pic32mx-ic.h | 0 arch/mips/src/pic32mx/pic32mx-int.h | 0 arch/mips/src/pic32mx/pic32mx-internal.h | 0 arch/mips/src/pic32mx/pic32mx-ioport.h | 0 arch/mips/src/pic32mx/pic32mx-irq.c | 0 arch/mips/src/pic32mx/pic32mx-memorymap.h | 486 +++--- arch/mips/src/pic32mx/pic32mx-oc.h | 0 arch/mips/src/pic32mx/pic32mx-osc.h | 0 arch/mips/src/pic32mx/pic32mx-pmp.h | 0 arch/mips/src/pic32mx/pic32mx-reset.h | 0 arch/mips/src/pic32mx/pic32mx-rtcc.h | 0 arch/mips/src/pic32mx/pic32mx-spi.h | 0 arch/mips/src/pic32mx/pic32mx-timer.h | 0 arch/mips/src/pic32mx/pic32mx-timerisr.c | 0 arch/mips/src/pic32mx/pic32mx-uart.h | 0 arch/mips/src/pic32mx/pic32mx-usbotg.h | 0 arch/mips/src/pic32mx/pic32mx-wdt.h | 0 31 files changed, 1633 insertions(+), 728 deletions(-) mode change 100755 => 100644 arch/mips/src/pic32mx/Make.defs mode change 100755 => 100644 arch/mips/src/pic32mx/chip.h mode change 100755 => 100644 arch/mips/src/pic32mx/excptmacros.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-adc.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-bmx.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-che.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-cm.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-config.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-cvr.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-ddp.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-devcfg.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-dma.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-flash.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-i2c.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-ic.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-int.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-internal.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-ioport.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-irq.c mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-memorymap.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-oc.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-osc.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-pmp.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-reset.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-rtcc.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-spi.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-timer.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-timerisr.c mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-uart.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-usbotg.h mode change 100755 => 100644 arch/mips/src/pic32mx/pic32mx-wdt.h diff --git a/arch/mips/src/pic32mx/Make.defs b/arch/mips/src/pic32mx/Make.defs old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/chip.h b/arch/mips/src/pic32mx/chip.h old mode 100755 new mode 100644 index 0dac54c2dd..e269fb6890 --- a/arch/mips/src/pic32mx/chip.h +++ b/arch/mips/src/pic32mx/chip.h @@ -1,489 +1,1386 @@ -/**************************************************************************** - * arch/mips/src/pic32mx/chip.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************/ - -#ifndef __ARCH_MIPS_SRC_PIC32MX_CHIP_H -#define __ARCH_MIPS_SRC_PIC32MX_CHIP_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -/**************************************************************************** - * Pre-Processor Definitions - ****************************************************************************/ -/* Configuration ************************************************************/ - -#if defined(CONFIG_ARCH_CHIP_PIC32MX320F032H) -# define CHIP_PIC32MX3 1 -# undef CHIP_PIC32MX4 -# define CHIP_NPINS 64 /* Package PT, MR */ -# define CHIP_MHZ 40 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 32 -# define CHIP_DATAMEM_KB 8 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 0 -# define CHIP_NUSBDMACHAN 0 -# define CHIP_CVR -# undef CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 2 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F064H) -# define CHIP_PIC32MX3 1 -# undef CHIP_PIC32MX4 -# define CHIP_NPINS 64 /* Package PT, MR */ -# define CHIP_MHZ 80 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 64 -# define CHIP_DATAMEM_KB 16 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 0 -# define CHIP_NUSBDMACHAN 0 -# define CHIP_CVR -# undef CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 2 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F128H) -# define CHIP_PIC32MX3 1 -# undef CHIP_PIC32MX4 -# define CHIP_NPINS 64 /* Package PT, MR */ -# define CHIP_MHZ 80 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 128 -# define CHIP_DATAMEM_KB 16 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 0 -# define CHIP_NUSBDMACHAN 0 -# define CHIP_CVR -# undef CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 2 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F128H) -# define CHIP_PIC32MX3 1 -# undef CHIP_PIC32MX4 -# define CHIP_NPINS 64 /* Package PT, MR */ -# define CHIP_MHZ 80 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 128 -# define CHIP_DATAMEM_KB 32 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 4 -# define CHIP_NUSBDMACHAN 0 -# define CHIP_CVR -# undef CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 2 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F256H) -# define CHIP_PIC32MX3 1 -# undef CHIP_PIC32MX4 -# define CHIP_NPINS 64 /* Package PT, MR */ -# define CHIP_MHZ 80 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 256 -# define CHIP_DATAMEM_KB 32 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 4 -# define CHIP_NUSBDMACHAN 0 -# define CHIP_CVR -# undef CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 2 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F512H) -# define CHIP_PIC32MX3 1 -# undef CHIP_PIC32MX4 -# define CHIP_NPINS 64 /* Package PT, MR */ -# define CHIP_MHZ 80 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 512 -# define CHIP_DATAMEM_KB 32 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 4 -# define CHIP_NUSBDMACHAN 0 -# define CHIP_CVR -# undef CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 2 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F128L) -# define CHIP_PIC32MX3 1 -# undef CHIP_PIC32MX4 -# define CHIP_NPINS 100 /* Package PT=100 BG=121 */ -# define CHIP_MHZ 80 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 128 -# define CHIP_DATAMEM_KB 16 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 0 -# define CHIP_NUSBDMACHAN 0 -# define CHIP_CVR -# undef CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 2 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F128L) -# undef CHIP_PIC32MX3 -# define CHIP_PIC32MX4 1 -# define CHIP_NPINS 100 /* Package PT=100 BG=121 */ -# define CHIP_MHZ 80 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 128 -# define CHIP_DATAMEM_KB 32 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 4 -# define CHIP_NUSBDMACHAN 0 -# define CHIP_CVR -# undef CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 2 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX360F256L) -# undef CHIP_PIC32MX3 -# define CHIP_PIC32MX4 1 -# define CHIP_NPINS 100 /* Package PT=100 BG=121 */ -# define CHIP_MHZ 80 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 256 -# define CHIP_DATAMEM_KB 32 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 4 -# define CHIP_NUSBDMACHAN 0 -# define CHIP_CVR -# define CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 2 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX360F512L) -# undef CHIP_PIC32MX3 -# define CHIP_PIC32MX4 1 -# define CHIP_NPINS 100 /* Package PT=100 BG=121 */ -# define CHIP_MHZ 80 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 512 -# define CHIP_DATAMEM_KB 32 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 4 -# define CHIP_NUSBDMACHAN 0 -# define CHIP_CVR -# define CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 2 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX420F032H) -# undef CHIP_PIC32MX3 -# define CHIP_PIC32MX4 1 -# define CHIP_NPINS 64 /* Package PT, MR */ -# define CHIP_MHZ 40 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 32 -# define CHIP_DATAMEM_KB 8 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 0 -# define CHIP_NUSBDMACHAN 2 -# define CHIP_CVR -# undef CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 1 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F128H) -# undef CHIP_PIC32MX3 -# define CHIP_PIC32MX4 1 -# define CHIP_NPINS 64 /* Package PT, MR */ -# define CHIP_MHZ 40 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 128 -# define CHIP_DATAMEM_KB 32 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 4 -# define CHIP_NUSBDMACHAN 2 -# define CHIP_CVR -# undef CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 1 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F256H) -# undef CHIP_PIC32MX3 -# define CHIP_PIC32MX4 1 -# define CHIP_NPINS 64 /* Package PT, MR */ -# define CHIP_MHZ 80 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 256 -# define CHIP_DATAMEM_KB 32 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 4 -# define CHIP_NUSBDMACHAN 2 -# define CHIP_CVR -# undef CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 1 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F512H) -# undef CHIP_PIC32MX3 -# define CHIP_PIC32MX4 1 -# define CHIP_NPINS 64 /* Package PT, MR */ -# define CHIP_MHZ 80 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 512 -# define CHIP_DATAMEM_KB 32 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 4 -# define CHIP_NUSBDMACHAN 2 -# define CHIP_CVR -# undef CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 1 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F128L) -# undef CHIP_PIC32MX3 -# define CHIP_PIC32MX4 1 -# define CHIP_NPINS 100 /* Package PT=100 BG=121 */ -# define CHIP_MHZ 80 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 128 -# define CHIP_DATAMEM_KB 32 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 4 -# define CHIP_NUSBDMACHAN 2 -# define CHIP_CVR -# undef CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 2 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX460F256L) -# undef CHIP_PIC32MX3 -# define CHIP_PIC32MX4 1 -# define CHIP_NPINS 100 /* Package PT=100 BG=121 */ -# define CHIP_MHZ 80 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 256 -# define CHIP_DATAMEM_KB 32 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 4 -# define CHIP_NUSBDMACHAN 2 -# define CHIP_CVR -# define CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 2 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#elif defined(CONFIG_ARCH_CHIP_PIC32MX460F512L) -# undef CHIP_PIC32MX3 -# define CHIP_PIC32MX4 1 -# define CHIP_NPINS 100 /* Package PT=100 BG=121 */ -# define CHIP_MHZ 80 -# define CHIP_BOOTFLASH_KB 12 -# define CHIP_PROGFLASH_KB 512 -# define CHIP_DATAMEM_KB 32 -# define CHIP_NTIMERS 5 -# define CHIP_NIC 5 -# define CHIP_NOC 5 -# define CHIP_NDMACH 4 -# define CHIP_NUSBDMACHAN 2 -# define CHIP_CVR -# define CHIP_TRACE -# define CHIP_NEUARTS 2 -# define CHIP_UARTFIFOD 4 -# define CHIP_NSPI 2 -# define CHIP_NI2C 2 -# define CHIP_NADC10 16 -# define CHIP_NCM 2 -# define CHIP_PMP -# define CHIP_PSP -# define CHIP_JTAH -#else -# error "Unrecognized PIC32 device -#endif - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_MIPS_SRC_PIC32MX_CHIP_H */ +/**************************************************************************** + * arch/mips/src/pic32mx/chip.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_CHIP_H +#define __ARCH_MIPS_SRC_PIC32MX_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-Processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +#if defined(CONFIG_ARCH_CHIP_PIC32MX320F032H) +# define CHIP_PIC32MX3 1 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT, MR */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */ +# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 0 /* No programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 2 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F064H) +# define CHIP_PIC32MX3 1 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT, MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */ +# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 0 /* No programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 2 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F128H) +# define CHIP_PIC32MX3 1 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT, MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 0 /* No programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 2 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F128H) +# define CHIP_PIC32MX3 1 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT, MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 2 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F256H) +# define CHIP_PIC32MX3 1 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT, MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 2 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F512H) +# define CHIP_PIC32MX3 1 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT, MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 2 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F128L) +# define CHIP_PIC32MX3 1 +# undef CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT=100 BG=121 */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 0 /* No programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 2 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F128L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 1 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT=100 BG=121 */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 2 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX360F256L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 1 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT=100 BG=121 */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 2 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX360F512L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 1 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT=100 BG=121 */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 0 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 2 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX420F032H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 1 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT, MR */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */ +# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 0 /* No programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 1 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F128H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 1 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT, MR */ +# define CHIP_MHZ 40 /* 40MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 1 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F256H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 1 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT, MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 1 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F512H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 1 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT, MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 1 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F128L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 1 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT=100 BG=121 */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 2 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX460F256L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 1 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT=100 BG=121 */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 2 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX460F512L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 1 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT=100 BG=121 */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels */ +# define CHIP_NUSBDMACHAN 2 +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 2 /* 2 UARTS */ +# define CHIP_UARTFIFOD 4 +# define CHIP_NSPI 2 /* 2 SPI interfaces */ +# define CHIP_NI2C 2 /* 2 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX534F064H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 1 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT,MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */ +# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 3 /* 3 SPI interfaces */ +# define CHIP_NI2C 4 /* 4 I2C interfaces */ +# define CHIP_NCAN 1 /* 1 CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F064H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 1 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT,MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 3 /* 3 SPI interfaces */ +# define CHIP_NI2C 4 /* 4 I2C interfaces */ +# define CHIP_NCAN 1 /* 1 CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F128H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 1 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT,MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 3 /* 3 SPI interfaces */ +# define CHIP_NI2C 4 /* 4 I2C interfaces */ +# define CHIP_NCAN 1 /* 1 CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F256H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 1 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT,MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */ +# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# undef CHIP_CVR /* No comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 3 /* 3 SPI interfaces */ +# define CHIP_NI2C 4 /* 4 I2C interfaces */ +# define CHIP_NCAN 1 /* 1 CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F512H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 1 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT,MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */ +# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# undef CHIP_CVR /* No comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 3 /* 3 SPI interfaces */ +# define CHIP_NI2C 4 /* 4 I2C interfaces */ +# define CHIP_NCAN 1 /* 1 CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX534F064L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 1 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT,PF,BG */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */ +# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 4 /* 4 SPI interfaces */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NCAN 1 /* 1 CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F064L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 1 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT,PF,BG */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 4 /* 4 SPI interfaces */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NCAN 1 /* 1 CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F128L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 1 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT,PF,BG */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 4 /* 4 SPI interfaces */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NCAN 1 /* 1 CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F256L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 1 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT,PF,BG */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */ +# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# undef CHIP_CVR /* No comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 4 /* 4 SPI interfaces */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NCAN 1 /* 1 CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F512L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 1 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT,PF,BG */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */ +# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# undef CHIP_CVR /* No comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 4 /* 4 SPI interfaces */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NCAN 1 /* 1 CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 0 /* No Ethernet */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F064H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 1 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT,MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 3 /* 3 SPI interfaces */ +# define CHIP_NI2C 4 /* 4 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernett interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F128H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 1 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT,MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 3 /* 3 SPI interfaces */ +# define CHIP_NI2C 4 /* 4 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernett interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F256H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 1 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT,MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */ +# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# undef CHIP_CVR /* No comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 3 /* 3 SPI interfaces */ +# define CHIP_NI2C 4 /* 4 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernett interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F512H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 1 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT,MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */ +# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# undef CHIP_CVR /* No comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 3 /* 3 SPI interfaces */ +# define CHIP_NI2C 4 /* 4 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernett interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX695F512H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 1 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 64 /* Package PT,MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */ +# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 3 /* 3 SPI interfaces */ +# define CHIP_NI2C 4 /* 4 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernett interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F064L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 1 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT,PF,BG */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 4 /* 4 SPI interfaces */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernett interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F128L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 1 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT,PF,BG */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 4 /* 4 SPI interfaces */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernett interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F256L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 1 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT,PF,BG */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */ +# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# undef CHIP_CVR /* No comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 4 /* 4 SPI interfaces */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernett interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F512L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 1 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT,PF,BG */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */ +# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# undef CHIP_CVR /* No comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 4 /* 4 SPI interfaces */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernett interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX695F512L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 1 +# undef CHIP_PIC32MX7 +# define CHIP_NPINS 100 /* Package PT,PF,BG */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */ +# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* xx programmable DMA channels (4 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 4 /* 4 SPI interfaces */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NCAN 0 /* No CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernett interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX764F128H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 1 +# define CHIP_NPINS 64 /* Package PT,MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels (6 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 3 /* 3 SPI interfaces */ +# define CHIP_NI2C 4 /* 4 I2C interfaces */ +# define CHIP_NCAN 1 /* 1 CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernett interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F256H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 1 +# define CHIP_NPINS 64 /* Package PT,MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */ +# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (8 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# undef CHIP_CVR /* No comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 3 /* 3 SPI interfaces */ +# define CHIP_NI2C 4 /* 4 I2C interfaces */ +# define CHIP_NCAN 2 /* 2 CAN interfaces */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernet interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F512H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 1 +# define CHIP_NPINS 64 /* Package PT,MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */ +# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (8 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# undef CHIP_CVR /* No comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 3 /* 3 SPI interfaces */ +# define CHIP_NI2C 4 /* 4 I2C interfaces */ +# define CHIP_NCAN 2 /* 2 CAN interfaces */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernet interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX795F512H) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 1 +# define CHIP_NPINS 64 /* Package PT,MR */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */ +# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (8 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# undef CHIP_TRACE /* No trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 3 /* 3 SPI interfaces */ +# define CHIP_NI2C 4 /* 4 I2C interfaces */ +# define CHIP_NCAN 2 /* 2 CAN interfaces */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernet interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX764F128L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 1 +# define CHIP_NPINS 100 /* Package PT,PF,BG */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */ +# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 4 /* 4 programmable DMA channels (6 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 4 /* 4 SPI interfaces */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NCAN 1 /* 1 CAN interface */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernet interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F256L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 1 +# define CHIP_NPINS 100 /* Package PT,PF,BG */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */ +# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (8 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# undef CHIP_CVR /* No comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 4 /* 4 SPI interfaces */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NCAN 2 /* 2 CAN interfaces */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernet interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F512L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 1 +# define CHIP_NPINS 100 /* Package PT,PF,BG */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */ +# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (8 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# undef CHIP_CVR /* No comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 4 /* 4 SPI interfaces */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NCAN 2 /* 2 CAN interfaces */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernet interface */ +# define CHIP_JTAG +#elif defined(CONFIG_ARCH_CHIP_PIC32MX795F512L) +# undef CHIP_PIC32MX3 +# define CHIP_PIC32MX4 +# undef CHIP_PIC32MX5 +# undef CHIP_PIC32MX6 +# undef CHIP_PIC32MX7 1 +# define CHIP_NPINS 100 /* Package PT,PF,BG */ +# define CHIP_MHZ 80 /* 80MHz maximum frequency */ +# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */ +# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */ +# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */ +# define CHIP_NTIMERS 5 /* 5 timers */ +# define CHIP_NIC 5 /* 5 input capture */ +# define CHIP_NOC 5 /* 5 output compare */ +# define CHIP_NDMACH 8 /* 8 programmable DMA channels (8 dedicated) */ +# define CHIP_NUSBDMACHAN tbd +# define CHIP_CVR 1 /* Have comparator voltage reference */ +# define CHIP_TRACE 1 /* Have trace capability */ +# define CHIP_NEUARTS 6 /* 6 UARTS */ +# define CHIP_UARTFIFOD tbd +# define CHIP_NSPI 4 /* 4 SPI interfaces */ +# define CHIP_NI2C 5 /* 5 I2C interfaces */ +# define CHIP_NCAN 2 /* 2 CAN interfaces */ +# define CHIP_NADC10 16 /* 16 10-bit ADC channels */ +# define CHIP_NCM 2 /* 2 Comparators */ +# define CHIP_PMP 1 /* Have parallel master port */ +# define CHIP_PSP 1 /* Have parallel slave port */ +# define CHIP_NETHERNET 1 /* 1 Ethernet interface */ +# define CHIP_JTAG +#else +# error "Unrecognized PIC32 device +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_CHIP_H */ diff --git a/arch/mips/src/pic32mx/excptmacros.h b/arch/mips/src/pic32mx/excptmacros.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-adc.h b/arch/mips/src/pic32mx/pic32mx-adc.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-bmx.h b/arch/mips/src/pic32mx/pic32mx-bmx.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-che.h b/arch/mips/src/pic32mx/pic32mx-che.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-cm.h b/arch/mips/src/pic32mx/pic32mx-cm.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-config.h b/arch/mips/src/pic32mx/pic32mx-config.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-cvr.h b/arch/mips/src/pic32mx/pic32mx-cvr.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-ddp.h b/arch/mips/src/pic32mx/pic32mx-ddp.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-devcfg.h b/arch/mips/src/pic32mx/pic32mx-devcfg.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-dma.h b/arch/mips/src/pic32mx/pic32mx-dma.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-flash.h b/arch/mips/src/pic32mx/pic32mx-flash.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-i2c.h b/arch/mips/src/pic32mx/pic32mx-i2c.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-ic.h b/arch/mips/src/pic32mx/pic32mx-ic.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-int.h b/arch/mips/src/pic32mx/pic32mx-int.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-internal.h b/arch/mips/src/pic32mx/pic32mx-internal.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-ioport.h b/arch/mips/src/pic32mx/pic32mx-ioport.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-irq.c b/arch/mips/src/pic32mx/pic32mx-irq.c old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-memorymap.h b/arch/mips/src/pic32mx/pic32mx-memorymap.h old mode 100755 new mode 100644 index e883dcef6d..c6bb71ffbb --- a/arch/mips/src/pic32mx/pic32mx-memorymap.h +++ b/arch/mips/src/pic32mx/pic32mx-memorymap.h @@ -1,239 +1,247 @@ -/************************************************************************************ - * arch/mips/src/pic32mx/pic32mx-memorymap.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - **** - // *********************************************************************************/ - -#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H -#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" -#include "mips32-memorymap.h" - -/************************************************************************************ - * Pre-Processor Definitions - ************************************************************************************/ -/* This memory may be valid for other chips as well, but I don't know that */ - -#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) - -/* Physical Memory Map **************************************************************/ - -# define PIC32MX_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */ -# define PIC32MX_PROGFLASH_PBASE 0x1d000000 /* Size depends on CHIP_PROGFLASH_KB */ -# define PIC32MX_SFR_PBASE 0x1f800000 /* Special function registers */ -# define PIC32MX_BOOTFLASH_PBASE 0x1fc00000 /* Size depends on CHIP_BOOTFLASH_KB */ -# define PIC32MX_DEVCFG_PBASE 0x1fc02ff0 /* Device configuration registers */ - -/* Virtual Memory Map ***************************************************************/ - -# define PIC32MX_DATAMEM_K0BASE (KSEG0_BASE + PIC32MX_DATAMEM_PBASE) -# define PIC32MX_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MX_PROGFLASH_PBASE) -# define PIC32MX_BOOTFLASH_K0BASE (KSEG0_BASE + PIC32MX_BOOTFLASH_PBASE) -# define PIC32MX_DEVCFG_K0BASE (KSEG0_BASE + PIC32MX_DEVCFG_PBASE) - -# define PIC32MX_DATAMEM_K1BASE (KSEG1_BASE + PIC32MX_DATAMEM_PBASE) -# define PIC32MX_PROGFLASH_K1BASE (KSEG1_BASE + PIC32MX_PROGFLASH_PBASE) -# define PIC32MX_SFR_K1BASE (KSEG1_BASE + PIC32MX_SFR_PBASE) -# define PIC32MX_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MX_BOOTFLASH_PBASE) -# define PIC32MX_DEVCFG_K1BASE (KSEG1_BASE + PIC32MX_DEVCFG_PBASE) - -/* Register Base Addresses **********************************************************/ - -/* Watchdog Register Base Address */ - -# define PIC32MX_WDT_K1BASE (PIC32MX_SFR_K1BASE + 0x00000000) - -/* RTCC Register Base Address */ - -# define PIC32MX_RTCC_K1BASE (PIC32MX_SFR_K1BASE + 0x00000200) - -/* Timer 1-5 Register Base Addresses */ - -# define PIC32MX_TIMER_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00000600 + 0x200*(n-1)) -# define PIC32MX_TIMER1_K1BASE (PIC32MX_SFR_K1BASE + 0x00000600) -# define PIC32MX_TIMER2_K1BASE (PIC32MX_SFR_K1BASE + 0x00000800) -# define PIC32MX_TIMER3_K1BASE (PIC32MX_SFR_K1BASE + 0x00000a00) -# define PIC32MX_TIMER4_K1BASE (PIC32MX_SFR_K1BASE + 0x00000c00) -# define PIC32MX_TIMER5_K1BASE (PIC32MX_SFR_K1BASE + 0x00000e00) - -/* Input Capture 1-5 Register Base Addresses */ - -# define PIC32MX_IC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00002000 + 0x200*(n-1)) -# define PIC32MX_IC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00002000) -# define PIC32MX_IC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00002200) -# define PIC32MX_IC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00002400) -# define PIC32MX_IC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00002600) -# define PIC32MX_IC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00002800) - -/* Output Compare 1-5 Register Base Addresses */ - -# define PIC32MX_OC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00003000 + 0x200*(n-1)) -# define PIC32MX_OC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00003000) -# define PIC32MX_OC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00003200) -# define PIC32MX_OC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00003400) -# define PIC32MX_OC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00003600) -# define PIC32MX_OC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00003800) - -/* I2C 1-2 Register Base Addresses */ - -# define PIC32MX_I2C1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005000) -# define PIC32MX_I2C2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005200) - -/* SPI 1-2 Register Base Addresses */ - -# define PIC32MX_SPI1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005800) -# define PIC32MX_SPI2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005a00) - -/* UART 1-2 Register Base Addresses */ - -# define PIC32MX_UART1_K1BASE (PIC32MX_SFR_K1BASE + 0x00006000) -# define PIC32MX_UART2_K1BASE (PIC32MX_SFR_K1BASE + 0x00006200) - -/* Parallel Master Register Base Address */ - -# define PIC32MX_PMP_K1BASE (PIC32MX_SFR_K1BASE + 0x00007000) - -/* ADC Register Base Addresses */ - -# define PIC32MX_ADC_K1BASE (PIC32MX_SFR_K1BASE + 0x00009000) - -/* Comparator Voltage Reference Register Base Addresses */ - -# define PIC32MX_CVR_K1BASE (PIC32MX_SFR_K1BASE + 0x00009800) - -/* Comparator Register Base Addresses */ - -# define PIC32MX_CM_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000) -# define PIC32MX_CM1_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000) -# define PIC32MX_CM2_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a010) - -/* Oscillator Control Register Base Addresses */ - -# define PIC32MX_OSC_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f000) - -/* Programming and Diagnostics Register Base Addresses */ - -# define PIC32MX_DDP_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f200) - -/* FLASH Controller Register Base Addresses */ - -# define PIC32MX_FLASH_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f400) - -/* Reset Control Register Base Address */ - -# define PIC32MX_RESET_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f600) - -/* Interrupt Register Base Address */ - -# define PIC32MX_INT_K1BASE (PIC32MX_SFR_K1BASE + 0x00081000) - -/* Bus Matrix Register Base Address */ - -# define PIC32MX_BMX_K1BASE (PIC32MX_SFR_K1BASE + 0x00082000) - -/* DMA Register Base Address */ - -# define PIC32MX_DMA_K1BASE (PIC32MX_SFR_K1BASE + 0x00083000) -# define PIC32MX_DMACH_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00083060 + 0xc0*(n)) -# define PIC32MX_DMACH0_K1BASE (PIC32MX_SFR_K1BASE + 0x00083060) -# define PIC32MX_DMACH1_K1BASE (PIC32MX_SFR_K1BASE + 0x00083120) -# define PIC32MX_DMACH2_K1BASE (PIC32MX_SFR_K1BASE + 0x000831e0) -# define PIC32MX_DMACH3_K1BASE (PIC32MX_SFR_K1BASE + 0x000832a0) - -/* Prefetch Cache Register Base Address */ - -# define PIC32MX_CHE_K1BASE (PIC32MX_SFR_K1BASE + 0x00084000) - -/* USB2 Register Base Addresses */ - -# define PIC32MX_USB_K1BASE (PIC32MX_SFR_K1BASE + 0x00085000) - -/* Port Register Base Addresses */ - -# define PIC32MX_IOPORTA 0 -# define PIC32MX_IOPORTB 1 -# define PIC32MX_IOPORTC 2 -# define PIC32MX_IOPORTD 3 -# define PIC32MX_IOPORTE 4 -# define PIC32MX_IOPORTF 5 -# define PIC32MX_IOPORTG 6 -# define PIC32MX_IOPORT_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00086000 + 0x40*(n)) - -# define PIC32MX_IOPORTA_K1BASE (PIC32MX_SFR_K1BASE + 0x00086000) -# define PIC32MX_IOPORTB_K1BASE (PIC32MX_SFR_K1BASE + 0x00086040) -# define PIC32MX_IOPORTC_K1BASE (PIC32MX_SFR_K1BASE + 0x00086080) -# define PIC32MX_IOPORTD_K1BASE (PIC32MX_SFR_K1BASE + 0x000860c0) -# define PIC32MX_IOPORTE_K1BASE (PIC32MX_SFR_K1BASE + 0x00086100) -# define PIC32MX_IOPORTF_K1BASE (PIC32MX_SFR_K1BASE + 0x00086140) -# define PIC32MX_IOPORTG_K1BASE (PIC32MX_SFR_K1BASE + 0x00086180) - -# define PIC32MX_IOPORTCN_K1BASE (PIC32MX_SFR_K1BASE + 0x000861c0) - -#else -# error "Memory map unknown for this PIC32 chip" -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -#ifndef __ASSEMBLY__ - -/************************************************************************************ - * Inline Functions - ************************************************************************************/ - -/************************************************************************************ - * Public Function Prototypes - ************************************************************************************/ - -#ifdef __cplusplus -#define EXTERN extern "C" -extern "C" { -#else -#define EXTERN extern -#endif - -#undef EXTERN -#ifdef __cplusplus -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H */ +/************************************************************************************ + * arch/mips/src/pic32mx/pic32mx-memorymap.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + **** + // *********************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H +#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" +#include "mips32-memorymap.h" + +/************************************************************************************ + * Pre-Processor Definitions + ************************************************************************************/ +/* This top-level memory map is valid for the PIC32MX3xx/4xx as well as the + * PIC32MX5xx/6xx/7xx families. + */ + +#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) || defined(CHIP_PIC32MX5) || + defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) + +/* Physical Memory Map **************************************************************/ + +# define PIC32MX_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */ +# define PIC32MX_PROGFLASH_PBASE 0x1d000000 /* Size depends on CHIP_PROGFLASH_KB */ +# define PIC32MX_SFR_PBASE 0x1f800000 /* Special function registers */ +# define PIC32MX_BOOTFLASH_PBASE 0x1fc00000 /* Size depends on CHIP_BOOTFLASH_KB */ +# define PIC32MX_DEVCFG_PBASE 0x1fc02ff0 /* Device configuration registers */ + +/* Virtual Memory Map ***************************************************************/ + +# define PIC32MX_DATAMEM_K0BASE (KSEG0_BASE + PIC32MX_DATAMEM_PBASE) +# define PIC32MX_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MX_PROGFLASH_PBASE) +# define PIC32MX_BOOTFLASH_K0BASE (KSEG0_BASE + PIC32MX_BOOTFLASH_PBASE) +# define PIC32MX_DEVCFG_K0BASE (KSEG0_BASE + PIC32MX_DEVCFG_PBASE) + +# define PIC32MX_DATAMEM_K1BASE (KSEG1_BASE + PIC32MX_DATAMEM_PBASE) +# define PIC32MX_PROGFLASH_K1BASE (KSEG1_BASE + PIC32MX_PROGFLASH_PBASE) +# define PIC32MX_SFR_K1BASE (KSEG1_BASE + PIC32MX_SFR_PBASE) +# define PIC32MX_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MX_BOOTFLASH_PBASE) +# define PIC32MX_DEVCFG_K1BASE (KSEG1_BASE + PIC32MX_DEVCFG_PBASE) +#endif + +/* Register Base Addresses **********************************************************/ + +#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) + +/* Watchdog Register Base Address */ + +# define PIC32MX_WDT_K1BASE (PIC32MX_SFR_K1BASE + 0x00000000) + +/* RTCC Register Base Address */ + +# define PIC32MX_RTCC_K1BASE (PIC32MX_SFR_K1BASE + 0x00000200) + +/* Timer 1-5 Register Base Addresses */ + +# define PIC32MX_TIMER_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00000600 + 0x200*(n-1)) +# define PIC32MX_TIMER1_K1BASE (PIC32MX_SFR_K1BASE + 0x00000600) +# define PIC32MX_TIMER2_K1BASE (PIC32MX_SFR_K1BASE + 0x00000800) +# define PIC32MX_TIMER3_K1BASE (PIC32MX_SFR_K1BASE + 0x00000a00) +# define PIC32MX_TIMER4_K1BASE (PIC32MX_SFR_K1BASE + 0x00000c00) +# define PIC32MX_TIMER5_K1BASE (PIC32MX_SFR_K1BASE + 0x00000e00) + +/* Input Capture 1-5 Register Base Addresses */ + +# define PIC32MX_IC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00002000 + 0x200*(n-1)) +# define PIC32MX_IC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00002000) +# define PIC32MX_IC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00002200) +# define PIC32MX_IC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00002400) +# define PIC32MX_IC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00002600) +# define PIC32MX_IC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00002800) + +/* Output Compare 1-5 Register Base Addresses */ + +# define PIC32MX_OC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00003000 + 0x200*(n-1)) +# define PIC32MX_OC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00003000) +# define PIC32MX_OC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00003200) +# define PIC32MX_OC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00003400) +# define PIC32MX_OC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00003600) +# define PIC32MX_OC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00003800) + +/* I2C 1-2 Register Base Addresses */ + +# define PIC32MX_I2C1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005000) +# define PIC32MX_I2C2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005200) + +/* SPI 1-2 Register Base Addresses */ + +# define PIC32MX_SPI1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005800) +# define PIC32MX_SPI2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005a00) + +/* UART 1-2 Register Base Addresses */ + +# define PIC32MX_UART1_K1BASE (PIC32MX_SFR_K1BASE + 0x00006000) +# define PIC32MX_UART2_K1BASE (PIC32MX_SFR_K1BASE + 0x00006200) + +/* Parallel Master Register Base Address */ + +# define PIC32MX_PMP_K1BASE (PIC32MX_SFR_K1BASE + 0x00007000) + +/* ADC Register Base Addresses */ + +# define PIC32MX_ADC_K1BASE (PIC32MX_SFR_K1BASE + 0x00009000) + +/* Comparator Voltage Reference Register Base Addresses */ + +# define PIC32MX_CVR_K1BASE (PIC32MX_SFR_K1BASE + 0x00009800) + +/* Comparator Register Base Addresses */ + +# define PIC32MX_CM_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000) +# define PIC32MX_CM1_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000) +# define PIC32MX_CM2_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a010) + +/* Oscillator Control Register Base Addresses */ + +# define PIC32MX_OSC_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f000) + +/* Programming and Diagnostics Register Base Addresses */ + +# define PIC32MX_DDP_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f200) + +/* FLASH Controller Register Base Addresses */ + +# define PIC32MX_FLASH_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f400) + +/* Reset Control Register Base Address */ + +# define PIC32MX_RESET_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f600) + +/* Interrupt Register Base Address */ + +# define PIC32MX_INT_K1BASE (PIC32MX_SFR_K1BASE + 0x00081000) + +/* Bus Matrix Register Base Address */ + +# define PIC32MX_BMX_K1BASE (PIC32MX_SFR_K1BASE + 0x00082000) + +/* DMA Register Base Address */ + +# define PIC32MX_DMA_K1BASE (PIC32MX_SFR_K1BASE + 0x00083000) +# define PIC32MX_DMACH_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00083060 + 0xc0*(n)) +# define PIC32MX_DMACH0_K1BASE (PIC32MX_SFR_K1BASE + 0x00083060) +# define PIC32MX_DMACH1_K1BASE (PIC32MX_SFR_K1BASE + 0x00083120) +# define PIC32MX_DMACH2_K1BASE (PIC32MX_SFR_K1BASE + 0x000831e0) +# define PIC32MX_DMACH3_K1BASE (PIC32MX_SFR_K1BASE + 0x000832a0) + +/* Prefetch Cache Register Base Address */ + +# define PIC32MX_CHE_K1BASE (PIC32MX_SFR_K1BASE + 0x00084000) + +/* USB2 Register Base Addresses */ + +# define PIC32MX_USB_K1BASE (PIC32MX_SFR_K1BASE + 0x00085000) + +/* Port Register Base Addresses */ + +# define PIC32MX_IOPORTA 0 +# define PIC32MX_IOPORTB 1 +# define PIC32MX_IOPORTC 2 +# define PIC32MX_IOPORTD 3 +# define PIC32MX_IOPORTE 4 +# define PIC32MX_IOPORTF 5 +# define PIC32MX_IOPORTG 6 +# define PIC32MX_IOPORT_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00086000 + 0x40*(n)) + +# define PIC32MX_IOPORTA_K1BASE (PIC32MX_SFR_K1BASE + 0x00086000) +# define PIC32MX_IOPORTB_K1BASE (PIC32MX_SFR_K1BASE + 0x00086040) +# define PIC32MX_IOPORTC_K1BASE (PIC32MX_SFR_K1BASE + 0x00086080) +# define PIC32MX_IOPORTD_K1BASE (PIC32MX_SFR_K1BASE + 0x000860c0) +# define PIC32MX_IOPORTE_K1BASE (PIC32MX_SFR_K1BASE + 0x00086100) +# define PIC32MX_IOPORTF_K1BASE (PIC32MX_SFR_K1BASE + 0x00086140) +# define PIC32MX_IOPORTG_K1BASE (PIC32MX_SFR_K1BASE + 0x00086180) + +# define PIC32MX_IOPORTCN_K1BASE (PIC32MX_SFR_K1BASE + 0x000861c0) + +#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7) +# error "Missing definitions" +#else +# error "Memory map unknown for this PIC32 chip" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Inline Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" { +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H */ diff --git a/arch/mips/src/pic32mx/pic32mx-oc.h b/arch/mips/src/pic32mx/pic32mx-oc.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-osc.h b/arch/mips/src/pic32mx/pic32mx-osc.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-pmp.h b/arch/mips/src/pic32mx/pic32mx-pmp.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-reset.h b/arch/mips/src/pic32mx/pic32mx-reset.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-rtcc.h b/arch/mips/src/pic32mx/pic32mx-rtcc.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-spi.h b/arch/mips/src/pic32mx/pic32mx-spi.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-timer.h b/arch/mips/src/pic32mx/pic32mx-timer.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-timerisr.c b/arch/mips/src/pic32mx/pic32mx-timerisr.c old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-uart.h b/arch/mips/src/pic32mx/pic32mx-uart.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-usbotg.h b/arch/mips/src/pic32mx/pic32mx-usbotg.h old mode 100755 new mode 100644 diff --git a/arch/mips/src/pic32mx/pic32mx-wdt.h b/arch/mips/src/pic32mx/pic32mx-wdt.h old mode 100755 new mode 100644