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arch: mips:Mixed case identifier fix

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Fix for Mixed case identifier found in pic32mz_timer.h

Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
This commit is contained in:
Alin Jerpelea 2021-03-30 16:57:47 +02:00 committed by David Sidrane
parent 29529e8758
commit c6f60ad3f0
2 changed files with 17 additions and 17 deletions
arch/mips/src/pic32mz
hardware
pic32mz_timer.h
pic32mz_timer.c

28
arch/mips/src/pic32mz/hardware/pic32mz_timer.h

@ -38,7 +38,7 @@
/* Timer Peripheral Offsets *************************************************/
#define PIC32MZ_TIMERn_OFFSET(n) ((n) << 9)
#define PIC32MZ_TIMERN_OFFSET(n) ((n) << 9)
# define PIC32MZ_TIMER1_OFFSET 0x0000
# define PIC32MZ_TIMER2_OFFSET 0x0200
# define PIC32MZ_TIMER3_OFFSET 0x0400
@ -68,7 +68,7 @@
/* Timer Peripheral Addresses ***********************************************/
#define PIC32MZ_TIMERn_K1BASE(n) (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMERn_OFFSET(n))
#define PIC32MZ_TIMERN_K1BASE(n) (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMERN_OFFSET(n))
# define PIC32MZ_TIMER1_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER1_OFFSET)
# define PIC32MZ_TIMER2_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER2_OFFSET)
# define PIC32MZ_TIMER3_K1BASE (PIC32MZ_TIMER_K1BASE+PIC32MZ_TIMER3_OFFSET)
@ -81,18 +81,18 @@
/* Register Addresses *******************************************************/
#define PIC32MZ_TIMER_CON(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CON_OFFSET)
#define PIC32MZ_TIMER_CONCLR(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CONCLR_OFFSET)
#define PIC32MZ_TIMER_CONSET(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CONSET_OFFSET)
#define PIC32MZ_TIMER_CONINV(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CONINV_OFFSET)
#define PIC32MZ_TIMER_CNT(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CNT_OFFSET)
#define PIC32MZ_TIMER_CNTCLR(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CNTCLR_OFFSET)
#define PIC32MZ_TIMER_CNTSET(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CNTSET_OFFSET)
#define PIC32MZ_TIMER_CNTINV(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_CNTINV_OFFSET)
#define PIC32MZ_TIMER_PR(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_PR_OFFSET)
#define PIC32MZ_TIMER_PRCLR(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_PRCLR_OFFSET)
#define PIC32MZ_TIMER_PRSET(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_PRSET_OFFSET)
#define PIC32MZ_TIMER_PRINV(n) (PIC32MZ_TIMERn_K1BASE(n)+PIC32MZ_TIMER_PRINV_OFFSET)
#define PIC32MZ_TIMER_CON(n) (PIC32MZ_TIMERN_K1BASE(n)+PIC32MZ_TIMER_CON_OFFSET)
#define PIC32MZ_TIMER_CONCLR(n) (PIC32MZ_TIMERN_K1BASE(n)+PIC32MZ_TIMER_CONCLR_OFFSET)
#define PIC32MZ_TIMER_CONSET(n) (PIC32MZ_TIMERN_K1BASE(n)+PIC32MZ_TIMER_CONSET_OFFSET)
#define PIC32MZ_TIMER_CONINV(n) (PIC32MZ_TIMERN_K1BASE(n)+PIC32MZ_TIMER_CONINV_OFFSET)
#define PIC32MZ_TIMER_CNT(n) (PIC32MZ_TIMERN_K1BASE(n)+PIC32MZ_TIMER_CNT_OFFSET)
#define PIC32MZ_TIMER_CNTCLR(n) (PIC32MZ_TIMERN_K1BASE(n)+PIC32MZ_TIMER_CNTCLR_OFFSET)
#define PIC32MZ_TIMER_CNTSET(n) (PIC32MZ_TIMERN_K1BASE(n)+PIC32MZ_TIMER_CNTSET_OFFSET)
#define PIC32MZ_TIMER_CNTINV(n) (PIC32MZ_TIMERN_K1BASE(n)+PIC32MZ_TIMER_CNTINV_OFFSET)
#define PIC32MZ_TIMER_PR(n) (PIC32MZ_TIMERN_K1BASE(n)+PIC32MZ_TIMER_PR_OFFSET)
#define PIC32MZ_TIMER_PRCLR(n) (PIC32MZ_TIMERN_K1BASE(n)+PIC32MZ_TIMER_PRCLR_OFFSET)
#define PIC32MZ_TIMER_PRSET(n) (PIC32MZ_TIMERN_K1BASE(n)+PIC32MZ_TIMER_PRSET_OFFSET)
#define PIC32MZ_TIMER_PRINV(n) (PIC32MZ_TIMERN_K1BASE(n)+PIC32MZ_TIMER_PRINV_OFFSET)
#define PIC32MZ_TIMER1_CON (PIC32MZ_TIMER1_K1BASE+PIC32MZ_TIMER_CON_OFFSET)
#define PIC32MZ_TIMER1_CONCLR (PIC32MZ_TIMER1_K1BASE+PIC32MZ_TIMER_CONCLR_OFFSET)

6
arch/mips/src/pic32mz/pic32mz_timer.c

@ -589,14 +589,14 @@ static inline bool pic32mz_timer_mode32(FAR struct pic32mz_timer_dev_s *dev)
static inline uint32_t pic32mz_timer_oddoffset(uint32_t evenoffset)
{
/* To access the consecutive odd timer the base needs be changed.
* PIC32MZ_TIMERn_OFFSET(1) represents the offset between timers' base.
* An even timer's base + PIC32MZ_TIMERn_OFFSET(1) gives the base of
* PIC32MZ_TIMERN_OFFSET(1) represents the offset between timers' base.
* An even timer's base + PIC32MZ_TIMERN_OFFSET(1) gives the base of
* the next odd timer.
* This will allow the access of the odd timer from the dev of its
* previous even timer.
*/
return PIC32MZ_TIMERn_OFFSET(1) + evenoffset;
return PIC32MZ_TIMERN_OFFSET(1) + evenoffset;
}
/****************************************************************************