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Various changes to get SAMA5 SDRAM working. Marginally functional, but there is more to be done

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This commit is contained in:
Gregory Nutt 2013-08-02 18:30:27 -06:00
parent 08a1ff5c79
commit c7293535fe
2 changed files with 3 additions and 3 deletions
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4
arch/arm/src/sama5/chip/sam_mpddrc.h
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@ -353,8 +353,8 @@
# define MPDDRC_DLL_MOR_CLK90OFF(n) ((n) << MPDDRC_DLL_MOR_CLK90OFF_SHIFT)
#define MPDDRC_DLL_MOR_SELOFF (1 << 16) /* Bit 16: DLL Offset Selection */
#define MPDDRC_DLL_MOR_KEY_SHIFT (24) /* Bits 24-31: DLL CLK90 Delay Line Offset (REVISIT) */
#define MPDDRC_DLL_MOR_KEY_MASK (0xff << MPDDRC_DLL_MOR_CLK90OFF_SHIFT)
# define MPDDRC_DLL_MOR_KEY (0xc5 << MPDDRC_DLL_MOR_CLK90OFF_SHIFT)
#define MPDDRC_DLL_MOR_KEY_MASK (0xff << MPDDRC_DLL_MOR_KEY_SHIFT)
# define MPDDRC_DLL_MOR_KEY (0xc5 << MPDDRC_DLL_MOR_KEY_SHIFT)
/* MPDDRC DLL Slave Offset Register */

2
arch/arm/src/sama5/chip/sam_pmc.h
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@ -128,7 +128,7 @@
* Clock Status Register common bit-field definitions
*/
#define PMC_PCK (1 << 2) /* Bit 2: Processor Clock */
#define PMC_PCK (1 << 0) /* Bit 0: Processor Clock */
#define PMC_DDRCK (1 << 2) /* Bit 2: DDR Clock */
#define PMC_LCDCK (1 << 3) /* Bit 3: LCD2x Clock */
#define PMC_SMDCK (1 << 4) /* Bit 4: SMD Clock */