From c74531e0143e8f11291bd24bbd308c8db81f1676 Mon Sep 17 00:00:00 2001
From: Gregory Nutt <gnutt@nuttx.org>
Date: Sat, 19 Jul 2014 13:25:59 -0600
Subject: [PATCH] SAMA5:  Update slow clock logic.  Things work a little
 differently on the SAMA5D3

---
 ChangeLog                          | 2 ++
 arch/arm/src/sama5/chip/sam_sckc.h | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/ChangeLog b/ChangeLog
index 0a584acc47..e934c11754 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -7746,4 +7746,6 @@
 	  (2014-7-18).
 	* configs/sama5d4-ek/src/sam_wm8904.c:  Add logic to configure and
 	  initialize the WM8904 audio CODEC (2014-7-17).
+	* arch/arm/src/sama5/sam_sckc.c/.h and chip/sam_sckc.h:  Add SAMA5
+	  slow clock support.
 
diff --git a/arch/arm/src/sama5/chip/sam_sckc.h b/arch/arm/src/sama5/chip/sam_sckc.h
index 4cb70f9b8b..e9071585ae 100644
--- a/arch/arm/src/sama5/chip/sam_sckc.h
+++ b/arch/arm/src/sama5/chip/sam_sckc.h
@@ -58,6 +58,12 @@
 
 /* Slow Clock Controller Configuration Register */
 
+#ifdef ATSAMA5D3
+#  define SCKC_CR_RCEN        (1 << 0)  /* Bit 0: Internal 32 kHz RC Oscillator */
+#  define SCKC_CR_OSC32EN     (1 << 1)  /* Bit 1: 32768 Hz Oscillator */
+#  define SCKC_CR_OSC32BYP    (1 << 2)  /* Bit 2: 2768Hz Oscillator Bypass */
+#endif
+
 #define SCKC_CR_OSCSEL        (1 << 3)  /* Bit 3:  Slow Clock Selector */
 
 #endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_SCKC_H */