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Kinetis K28 USBHS USB-Host.

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This commit is contained in:
Johannes Schock 2020-08-02 17:39:47 +02:00 committed by Alan Carvalho de Assis
parent 5c67eac27f
commit c760db7fd0
10 changed files with 6113 additions and 16 deletions
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4
arch/arm/include/kinetis/kinetis_sim.h
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@ -530,8 +530,8 @@
# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */ # define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */
# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[TRNG/RNGA] */ # define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[TRNG/RNGA] */
# undef KINETIS_SIM_HAS_SCGC3_USBHS /* SoC does not have SCGC3[USBHS] */ # define KINETIS_SIM_HAS_SCGC3_USBHS 1 /* SoC has SCGC3[USBHS] */
# undef KINETIS_SIM_HAS_SCGC3_USBHSPHY /* SoC does not have SCGC3[USBHSPHY] */ # define KINETIS_SIM_HAS_SCGC3_USBHSPHY 1 /* SoC has SCGC3[USBHSPHY] */
# undef KINETIS_SIM_HAS_SCGC3_USBHSDCD /* SoC does not have SCGC3[USBHSDCD] */ # undef KINETIS_SIM_HAS_SCGC3_USBHSDCD /* SoC does not have SCGC3[USBHSDCD] */
# undef KINETIS_SIM_HAS_SCGC3_FLEXCAN1 /* SoC does not have SCGC3[FLEXCAN1] */ # undef KINETIS_SIM_HAS_SCGC3_FLEXCAN1 /* SoC does not have SCGC3[FLEXCAN1] */
# undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC does not have SCGC3[NFC] */ # undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC does not have SCGC3[NFC] */

8
arch/arm/src/kinetis/Kconfig
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@ -713,6 +713,14 @@ config KINETIS_CMT
---help--- ---help---
Support Carrier Modulator Transmitter Support Carrier Modulator Transmitter
config KINETIS_USBHS
bool "USB HS"
default n
select USBHOST_HAVE_ASYNCH if USBHOST
select USBHOST_ASYNCH
---help---
Support USB HIGH SPEED (see also USBHOST and USBDEV)
config KINETIS_USBOTG config KINETIS_USBOTG
bool "USB OTG" bool "USB OTG"
default n default n

8
arch/arm/src/kinetis/Make.defs
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@ -149,8 +149,16 @@ CHIP_CSRCS += kinetis_usbdev.c
endif endif
ifeq ($(CONFIG_USBHOST),y) ifeq ($(CONFIG_USBHOST),y)
ifneq ($(CONFIG_KINETIS_USBHS),y)
CHIP_CSRCS += kinetis_usbhost.c CHIP_CSRCS += kinetis_usbhost.c
endif endif
endif
ifeq ($(CONFIG_USBHOST),y)
ifeq ($(CONFIG_KINETIS_USBHS),y)
CHIP_CSRCS += kinetis_usbhshost.c
endif
endif
ifeq ($(CONFIG_KINETIS_DMA),y) ifeq ($(CONFIG_KINETIS_DMA),y)
CHIP_CSRCS += kinetis_dma.c kinetis_pindma.c CHIP_CSRCS += kinetis_dma.c kinetis_pindma.c

36
arch/arm/src/kinetis/hardware/kinetis_usbhs.h
View File

@ -48,6 +48,11 @@
* Pre-processor Definitions * Pre-processor Definitions
********************************************************************************************************************/ ********************************************************************************************************************/
#define KINETIS_EHCI_NRHPORT 1 /* There is only a single root hub port */
#define KINETIS_USBHS_HCCR_OFFSET 0x100 /* Offset to EHCI Host Controller Capabiliy registers */
#define KINETIS_USBHS_HCOR_OFFSET 0x140 /* Offset to EHCI Host Controller Operational Registers */
/* Register Offsets *************************************************************************************************/ /* Register Offsets *************************************************************************************************/
#define KINETIS_USBHS_ID_OFFSET 0x0000 /* Identification Register */ #define KINETIS_USBHS_ID_OFFSET 0x0000 /* Identification Register */
@ -160,6 +165,9 @@
/* Register Addresses ***********************************************************************************************/ /* Register Addresses ***********************************************************************************************/
#define KINETIS_USBHS_HCCR_BASE (KINETIS_USBHS_BASE + KINETIS_USBHS_HCCR_OFFSET)
#define KINETIS_USBHS_HCOR_BASE (KINETIS_USBHS_BASE + KINETIS_USBHS_HCOR_OFFSET)
#define KINETIS_USBHS_ID (KINETIS_USBHS_BASE + KINETIS_USBHS_ID_OFFSET) #define KINETIS_USBHS_ID (KINETIS_USBHS_BASE + KINETIS_USBHS_ID_OFFSET)
#define KINETIS_USBHS_HWGENERAL (KINETIS_USBHS_BASE + KINETIS_USBHS_HWGENERAL_OFFSET) #define KINETIS_USBHS_HWGENERAL (KINETIS_USBHS_BASE + KINETIS_USBHS_HWGENERAL_OFFSET)
#define KINETIS_USBHS_HWHOST (KINETIS_USBHS_BASE + KINETIS_USBHS_HWHOST_OFFSET) #define KINETIS_USBHS_HWHOST (KINETIS_USBHS_BASE + KINETIS_USBHS_HWHOST_OFFSET)
@ -369,7 +377,7 @@
/* Bits 28-31: Reserved */ /* Bits 28-31: Reserved */
#define USBHS_HCSPARAMS_N_TT_SHIFT (24) /* Bits 24-27: Number of Transaction Translators */ #define USBHS_HCSPARAMS_N_TT_SHIFT (24) /* Bits 24-27: Number of Transaction Translators */
#define USBHS_HCSPARAMS_N_TT_MASK (0xf << USBHS_HCSPARAMS_N_TT_SHIFT) #define USBHS_HCSPARAMS_N_TT_MASK (0xf << USBHS_HCSPARAMS_N_TT_SHIFT)
#define USBHS_HCSPARAMS_N_PTT_SHIFT (20) /* Bits 22-30: Ports per Transaction Translator */ #define USBHS_HCSPARAMS_N_PTT_SHIFT (20) /* Bits 20-23: Ports per Transaction Translator */
#define USBHS_HCSPARAMS_N_PTT_MASK (0xf << USBHS_HCSPARAMS_N_PTT_SHIFT) #define USBHS_HCSPARAMS_N_PTT_MASK (0xf << USBHS_HCSPARAMS_N_PTT_SHIFT)
/* Bits 17-19: Reserved */ /* Bits 17-19: Reserved */
#define USBHS_HCSPARAMS_PI (1 << 16) /* Bit 16: Port Indicators */ #define USBHS_HCSPARAMS_PI (1 << 16) /* Bit 16: Port Indicators */
@ -556,6 +564,10 @@
/* Bit 28-29: Reserved */ /* Bit 28-29: Reserved */
#define USBHS_PORTSC1_PSPD_SHIFT (26) /* Bits 26-27: Port Speed */ #define USBHS_PORTSC1_PSPD_SHIFT (26) /* Bits 26-27: Port Speed */
#define USBHS_PORTSC1_PSPD_MASK (0x3 << USBHS_PORTSC1_PSPD_SHIFT) #define USBHS_PORTSC1_PSPD_MASK (0x3 << USBHS_PORTSC1_PSPD_SHIFT)
# define USBHS_PORTSC1_PSPD_FS (0 << USBHS_PORTSC1_PSPD_SHIFT) /* Full-speed */
# define USBHS_PORTSC1_PSPD_LS (1 << USBHS_PORTSC1_PSPD_SHIFT) /* Low-speed */
# define USBHS_PORTSC1_PSPD_HS (2 << USBHS_PORTSC1_PSPD_SHIFT) /* High-speed */
#define USBHS_PORTSC1_PTS2 (1 << 25) /* Bit 25: Port Transceiver Select [2] */ #define USBHS_PORTSC1_PTS2 (1 << 25) /* Bit 25: Port Transceiver Select [2] */
#define USBHS_PORTSC1_PFSC (1 << 24) /* Bit 24: Port force Full-Speed Connect */ #define USBHS_PORTSC1_PFSC (1 << 24) /* Bit 24: Port force Full-Speed Connect */
#define USBHS_PORTSC1_PHCD (1 << 23) /* Bit 23: PHY low power suspend */ #define USBHS_PORTSC1_PHCD (1 << 23) /* Bit 23: PHY low power suspend */
@ -627,6 +639,9 @@
#define USBHS_USBMODE_ES (1 << 2) /* Bit 2: Endian Select */ #define USBHS_USBMODE_ES (1 << 2) /* Bit 2: Endian Select */
#define USBHS_USBMODE_CM_SHIFT (0) /* Bits 0-1: Controller Mode */ #define USBHS_USBMODE_CM_SHIFT (0) /* Bits 0-1: Controller Mode */
#define USBHS_USBMODE_CM_MASK (0x3 << USBHS_USBMODE_CM_SHIFT) #define USBHS_USBMODE_CM_MASK (0x3 << USBHS_USBMODE_CM_SHIFT)
# define USBHS_USBMODE_CM_IDLE (0 << USBHS_USBMODE_CM_SHIFT) /* Idle */
# define USBHS_USBMODE_CM_DEVICE (2 << USBHS_USBMODE_CM_SHIFT) /* Device controller */
# define USBHS_USBMODE_CM_HOST (3 << USBHS_USBMODE_CM_SHIFT) /* Host controller */
/* Endpoint Setup Status Register */ /* Endpoint Setup Status Register */
@ -730,24 +745,24 @@
/* USB PHY Transmitter Control Register */ /* USB PHY Transmitter Control Register */
#define USBPHY_TXn_USBPHY_TX_EDGECTRL_SHIFT (29) /* Bits 28-26: Edge-rate of the current sensing in HS transmit */ #define USBPHY_TXn_USBPHY_TX_EDGECTRL_SHIFT (26) /* Bits 26-28: Edge-rate of the current sensing in HS transmit */
#define USBPHY_TXn_USBPHY_TX_EDGECTRL_MASK (0x7 << USBPHY_TXn_USBPHY_TX_EDGECTRL_SHIFT) #define USBPHY_TXn_USBPHY_TX_EDGECTRL_MASK (0x7 << USBPHY_TXn_USBPHY_TX_EDGECTRL_SHIFT)
/* Bit 20-25: Reserved */ /* Bit 20-25: Reserved */
#define USBPHY_TXn_TXCAL45DP_SHIFT (19) /* Bits 16-19: Trim termination resistance to the USB_DP output */ #define USBPHY_TXn_TXCAL45DP_SHIFT (16) /* Bits 16-19: Trim termination resistance to the USB_DP output */
#define USBPHY_TXn_TXCAL45DP_MASK (0xf << USBPHY_TXn_TXCAL45DP_SHIFT) #define USBPHY_TXn_TXCAL45DP_MASK (0xf << USBPHY_TXn_TXCAL45DP_SHIFT)
/* Bits 12-15: Reserved */ /* Bits 12-15: Reserved */
#define USBPHY_TXn_TXCAL45DM_SHIFT (11) /* Bits 8-11: Trim termination resistance to the USB_DM output */ #define USBPHY_TXn_TXCAL45DM_SHIFT (8) /* Bits 8-11: Trim termination resistance to the USB_DM output */
#define USBPHY_TXn_TXCAL45DM_MASK (0xf << USBPHY_TXn_TXCAL45DM_SHIFT) #define USBPHY_TXn_TXCAL45DM_MASK (0xf << USBPHY_TXn_TXCAL45DM_SHIFT)
/* Bits 4-7: Reserved */ /* Bits 4-7: Reserved */
#define USBPHY_TXn_D_CAL_SHIFT (0) /* Bits 7-0: Trim current source for the High Speed TX drivers */ #define USBPHY_TXn_D_CAL_SHIFT (0) /* Bits 7-0: Trim current source for the High Speed TX drivers */
#define USBPHY_TXn_D_CAL_MASK (0x7f << USBPHY_TXn_D_CAL_SHIFT) #define USBPHY_TXn_D_CAL_MASK (0xf << USBPHY_TXn_D_CAL_SHIFT)
/* USB PHY Receiver Control Register */ /* USB PHY Receiver Control Register */
/* Bits 23-31: Reserved */ /* Bits 23-31: Reserved */
#define USBPHY_RXn_RXDBYPASS (1 << 22) /* Bit 22: Test mode, replace FS differential receiver with DP single ended receiver */ #define USBPHY_RXn_RXDBYPASS (1 << 22) /* Bit 22: Test mode, replace FS differential receiver with DP single ended receiver */
/* Bits 7-21: Reserved */ /* Bits 7-21: Reserved */
#define USBPHY_RXn_DISCONADJ_SHIFT (4) /* Bits 6-4: Adjusts the trip point for the disconnect detector */ #define USBPHY_RXn_DISCONADJ_SHIFT (4) /* Bits 4-6: Adjusts the trip point for the disconnect detector */
#define USBPHY_RXn_DISCONADJ_MASK (0x7 << USBPHY_RXn_DISCONADJ_SHIFT) #define USBPHY_RXn_DISCONADJ_MASK (0x7 << USBPHY_RXn_DISCONADJ_SHIFT)
/* Bit 3: Reserved */ /* Bit 3: Reserved */
#define USBPHY_RXn_ENVADJ_SHIFT (0) /* Bits 0-3: Adjusts the trip point for the envelope detector */ #define USBPHY_RXn_ENVADJ_SHIFT (0) /* Bits 0-3: Adjusts the trip point for the envelope detector */
@ -847,11 +862,16 @@
#define USBPHY_PLL_SICn_PLL_ENABLE (1 << 13) /* Bit 13: Enable the clock output from the USB PLL */ #define USBPHY_PLL_SICn_PLL_ENABLE (1 << 13) /* Bit 13: Enable the clock output from the USB PLL */
#define USBPHY_PLL_SICn_PLL_POWER (1 << 12) /* Bit 12: Power up the USB PLL */ #define USBPHY_PLL_SICn_PLL_POWER (1 << 12) /* Bit 12: Power up the USB PLL */
#define USBPHY_PLL_SICn_PLL_HOLD_RING_OFF (1 << 11) /* Bit 11: Analog debug bit */ #define USBPHY_PLL_SICn_PLL_HOLD_RING_OFF (1 << 11) /* Bit 11: Analog debug bit */
/* Bit 10: Reserved */ /* Bits 7-10: Reserved */
#define USBPHY_PLL_SICn_PLL_EN_USB_CLKS (1 << 9) /* Bit 6: Enable the USB clock output from the USB PHY PLL */ #define USBPHY_PLL_SICn_PLL_EN_USB_CLKS (1 << 6) /* Bit 6: Enable the USB clock output from the USB PHY PLL */
/* Bits 2-5: Reserved */ /* Bits 2-5: Reserved */
#define USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT (0) /* Bits 0-4: Controls the USB PLL feedback loop divider */ #define USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT (0) /* Bits 0-4: Controls the USB PLL feedback loop divider */
#define USBPHY_PLL_SICn_PLL_DIV_SEL_MASK (0x1f << USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT) #define USBPHY_PLL_SICn_PLL_DIV_SEL_MASK (0x1f << USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT)
# define USBPHY_PLL_SICn_PLL_DIV_SEL_24MHZ (0 << USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT) /* 24Mhz XTAL */
# define USBPHY_PLL_SICn_PLL_DIV_SEL_16MHZ (1 << USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT) /* 16Mhz XTAL */
# define USBPHY_PLL_SICn_PLL_DIV_SEL_12MHZ (2 << USBPHY_PLL_SICn_PLL_DIV_SEL_SHIFT) /* 12Mhz XTAL */
/* USB PHY VBUS Detect Control Register */ /* USB PHY VBUS Detect Control Register */

5469
arch/arm/src/kinetis/kinetis_usbhshost.c Normal file
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File diff suppressed because it is too large Load Diff

149
arch/arm/src/kinetis/kinetis_usbhshost.h Normal file
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@ -0,0 +1,149 @@
/*****************************************************************************
* arch/arm/src/kinetis/kinetis_usbhshost.h
*
* Copyright (C) 2012, 2015, 2019 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* Dave Marples <dave@marples.net>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_USBHSHOST_H
#define __ARCH_ARM_SRC_KINETIS_KINETIS_USBHSHOST_H
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
/*****************************************************************************
* Public Types
*****************************************************************************/
#ifndef __ASSEMBLY__
/*****************************************************************************
* Public Data
*****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/*****************************************************************************
* Public Function Prototypes
*****************************************************************************/
/*****************************************************************************
* Name: kinetis_usbhost_vbusdrive
*
* Description:
* Enable/disable driving of VBUS 5V output. This function must be provided
* by each platform that implements the OHCI or EHCI host interface
*
* Input Parameters:
* rhport - Selects root hub port to be powered host interface. Since the
* KINETIS has only a downstream port, zero is the only possible value for
* this parameter.
* enable - true: enable VBUS power; false: disable VBUS power
*
* Returned Value:
* None
*
*****************************************************************************/
extern void kinetis_usbhost_vbusdrive(int rhport, bool enable);
/*****************************************************************************
* Name: kinetis_setup_overcurrent
*
* Description:
* Setup to receive an interrupt-level callback if an over-current condition
* is detected.
*
* Input Parameters:
* handler - New over-current interrupt handler
* arg - The argument that will accompany the interrupt
*
* Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
*****************************************************************************/
extern int kinetis_setup_overcurrent(xcpt_t handler, void *arg);
/*****************************************************************************
* Name: kinetis_ehci_initialize
*
* Description:
* Initialize USB EHCI host controller hardware.
*
* Input Parameters:
* controller -- If the device supports more than one EHCI interface, then
* this identifies which controller is being initialized. Normally, this
* is just zero.
*
* Returned Value:
* And instance of the USB host interface. The controlling task should
* use this interface to (1) call the wait() method to wait for a device
* to be connected, and (2) call the enumerate() method to bind the device
* to a class driver.
*
* Assumptions:
* - This function should called in the initialization sequence in order
* to initialize the USB device functionality.
* - Class drivers should be initialized prior to calling this function.
* Otherwise, there is a race condition if the device is already connected.
*
****************************************************************************/
#if defined(CONFIG_KINETIS_USBHS) && defined(CONFIG_USBHOST)
struct usbhost_connection_s;
FAR struct usbhost_connection_s *kinetis_ehci_initialize(int controller);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_USBHSHOST_H */

6
boards/arm/kinetis/freedom-k28f/src/Makefile
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@ -66,4 +66,10 @@ ifeq ($(CONFIG_KINETIS_USBOTG),y)
CSRCS += k28_usbdev.c CSRCS += k28_usbdev.c
endif endif
ifeq ($(CONFIG_KINETIS_USBHS),y)
ifeq ($(CONFIG_USBHOST),y)
CSRCS += k28_usbhshost.c
endif
endif
include $(TOPDIR)/boards/Board.mk include $(TOPDIR)/boards/Board.mk

23
boards/arm/kinetis/freedom-k28f/src/freedom-k28f.h
View File

@ -164,6 +164,15 @@
#define GPIO_SW2 (GPIO_PULLUP | PIN_INT_BOTH | PIN_PORTA | PIN4) #define GPIO_SW2 (GPIO_PULLUP | PIN_INT_BOTH | PIN_PORTA | PIN4)
#define GPIO_SW3 (GPIO_PULLUP | PIN_INT_BOTH | PIN_PORTD | PIN0) #define GPIO_SW3 (GPIO_PULLUP | PIN_INT_BOTH | PIN_PORTD | PIN0)
/* A micro Secure Digital (SD) card slot is available on the FRDM-K28F
* connected to the SD Host Controller (SDHC) signals of the MCU.
* This slot will accept micro format SD memory cards.
* The SD card detect pin (PTB5) is an open switch that shorts with VDD when
* card is inserted.
*/
#define GPIO_SD_CARDDETECT (GPIO_INPUT | PIN_INT_BOTH | PIN_PORTB | PIN5)
/**************************************************************************** /****************************************************************************
* Public Types * Public Types
****************************************************************************/ ****************************************************************************/
@ -234,6 +243,20 @@ void k28_i2cdev_initialize(void);
extern void weak_function k28_usbdev_initialize(void); extern void weak_function k28_usbdev_initialize(void);
/****************************************************************************
* Name: k28_usbhost_initialize
*
* Description:
* Inititialize USB High Speed Host
*
****************************************************************************/
#if defined(CONFIG_KINETIS_USBHS) && defined(CONFIG_USBHOST)
int k28_usbhost_initialize(void);
#else
# define k28_usbhost_initialize() (OK)
#endif
/**************************************************************************** /****************************************************************************
* Name: k28_sdhc_initialize * Name: k28_sdhc_initialize
* *

5
boards/arm/kinetis/freedom-k28f/src/k28_bringup.c
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@ -153,6 +153,11 @@ int k28_bringup(void)
} }
#endif #endif
#if defined(CONFIG_USBHOST) && defined(CONFIG_KINETIS_USBHS)
k28_usbhost_initialize();
#endif
UNUSED(ret); UNUSED(ret);
return OK; return OK;
} }

409
boards/arm/kinetis/freedom-k28f/src/k28_usbhshost.c Normal file
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@ -0,0 +1,409 @@
/*****************************************************************************
* boards/arm/kinetis/freedom-k28f/src/k28_usbhshost.c
*
* Copyright (C) 2013, 2015-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*****************************************************************************/
/*****************************************************************************
* Included Files
*****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <sched.h>
#include <errno.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/irq.h>
#include <nuttx/kthread.h>
#include <nuttx/usb/usbdev.h>
#include <nuttx/usb/usbhost.h>
#include <nuttx/usb/usbdev_trace.h>
#include <nuttx/usb/ehci.h>
#include <kinetis_usbhshost.h>
#include "arm_arch.h"
#include "hardware/kinetis_k28pinmux.h"
#include "hardware/kinetis_mcg.h"
#include "hardware/kinetis_sim.h"
#include "hardware/kinetis_osc.h"
#include "hardware/kinetis_usbhs.h"
#include "freedom-k28f.h"
#include <arch/board/board.h> /* Must always be included last */
#if defined(CONFIG_KINETIS_USBHS) && defined(CONFIG_USBHOST)
/*****************************************************************************
* Pre-processor Definitions
*****************************************************************************/
#define BOARD_USB_PHY_D_CAL (0x0CU)
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
#ifndef CONFIG_USBHOST_DEFPRIO
# define CONFIG_USBHOST_DEFPRIO 50
#endif
#ifndef CONFIG_USBHOST_STACKSIZE
# ifdef CONFIG_USBHOST_HUB
# define CONFIG_USBHOST_STACKSIZE 1536
# else
# define CONFIG_USBHOST_STACKSIZE 1024
# endif
#endif
/*****************************************************************************
* Private Data
*****************************************************************************/
/* Retained device driver handle */
static struct usbhost_connection_s *g_ehciconn;
/*****************************************************************************
* Private Functions
*****************************************************************************/
/*****************************************************************************
* Name: ehci_waiter
*
* Description:
* Wait for USB devices to be connected to the EHCI root hub.
*
*****************************************************************************/
static int ehci_waiter(int argc, char *argv[])
{
FAR struct usbhost_hubport_s *hport;
uinfo("ehci_waiter: Running\n");
for (; ; )
{
/* Wait for the device to change state */
DEBUGVERIFY(CONN_WAIT(g_ehciconn, &hport));
syslog(LOG_INFO, "ehci_waiter: %s\n",
hport->connected ? "connected" : "disconnected");
/* Did we just become connected? */
if (hport->connected)
{
/* Yes.. enumerate the newly connected device */
CONN_ENUMERATE(g_ehciconn, hport);
}
}
/* Keep the compiler from complaining */
return 0;
}
/*****************************************************************************
* Name: ehci_hw_init
*
* Description:
* Initialize PHY and clocks for EHCI
*
*****************************************************************************/
static void ehci_hwinit(void)
{
uint32_t regval;
uint8_t regval8;
/* Enable Internal Reference Clock */
regval8 = getreg8(KINETIS_MCG_C1);
regval8 |= (MCG_C1_IRCLKEN);
putreg8(regval8, KINETIS_MCG_C1);
/* Enable External Reference Clock */
regval8 = getreg8(KINETIS_OSC_CR);
regval8 |= (OSC_CR_ERCLKEN);
putreg8(regval8, KINETIS_OSC_CR);
/* Enable PLL Regulator */
regval = getreg32(KINETIS_SIM_SOPT2);
regval |= (SIM_SOPT2_USBREGEN);
putreg32(regval, KINETIS_SIM_SOPT2);
/* Gate USB clock */
regval = getreg32(KINETIS_SIM_SCGC3);
regval |= (SIM_SCGC3_USBHSPHY);
putreg32(regval, KINETIS_SIM_SCGC3);
/* Release Softreset and ungate PHY Clock */
regval = getreg32(KINETIS_USBHSPHY_CTRL);
regval &= ~(USBPHY_CTRLn_SFTRST);
regval &= ~(USBPHY_CTRLn_CLKGATE);
putreg32(regval, KINETIS_USBHSPHY_CTRL);
/* Set PHY PLL Clock */
regval = getreg32(KINETIS_USBHSPHY_PLL_SIC);
regval &= ~(USBPHY_PLL_SICn_PLL_BYPASS);
regval &= ~(USBPHY_PLL_SICn_PLL_DIV_SEL_MASK);
regval |= (USBPHY_PLL_SICn_PLL_POWER);
regval |= (USBPHY_PLL_SICn_PLL_EN_USB_CLKS);
# if (BOARD_EXTAL_FREQ == 24000000)
regval |= USBPHY_PLL_SICn_PLL_DIV_SEL_24MHZ;
# elif (BOARD_EXTAL_FREQ == 16000000)
regval |= USBPHY_PLL_SICn_PLL_DIV_SEL_16MHZ;
# elif (BOARD_EXTAL_FREQ == 12000000)
regval |= USBPHY_PLL_SICn_PLL_DIV_SEL_12MHZ;
# else
# warning Not supported.
# endif
putreg32(regval, KINETIS_USBHSPHY_PLL_SIC);
regval = getreg32(KINETIS_USBHSPHY_TRIM_OVERRIDE_EN);
regval |= (USBPHY_TRIM_OVERRIDE_ENn_TRIM_DIV_SEL_OVERRIDE);
putreg32(regval, KINETIS_USBHSPHY_TRIM_OVERRIDE_EN);
do
{
regval = getreg32(KINETIS_USBHSPHY_PLL_SIC);
}
while (!(regval & USBPHY_PLL_SICn_PLL_LOCK));
/* Enable USBHS Clock and Regulator */
regval = getreg32(KINETIS_SIM_SCGC3);
regval |= (SIM_SCGC3_USBHS);
putreg32(regval, KINETIS_SIM_SCGC3);
regval = getreg32(KINETIS_SIM_USBPHYCTL);
regval &= ~(SIM_USBPHYCTL_USB3VOUTTRG_MASK);
regval |= SIM_USBPHYCTL_USB3VOUTTRG_3V310;
regval |= SIM_USBPHYCTL_USBVREGSEL;
putreg32(regval, KINETIS_SIM_USBPHYCTL);
/* Disable Powerdown */
putreg32(0, KINETIS_USBHSPHY_PWD);
/* Misc */
regval = getreg32(KINETIS_USBHSPHY_CTRL);
regval |= USBPHY_CTRLn_ENUTMILEVEL2;
regval |= USBPHY_CTRLn_ENUTMILEVEL3;
putreg32(regval, KINETIS_USBHSPHY_CTRL);
}
/*****************************************************************************
* Public Functions
*****************************************************************************/
/*****************************************************************************
* Name: k28_usbhost_initialize
*
* Description:
* Called at application startup time to initialize the USB host
* functionality.
* This function will start a thread that will monitor for device
* connection/disconnection events.
*
*****************************************************************************/
int k28_usbhost_initialize(void)
{
pid_t pid;
int ret;
/* First, register all of the class drivers needed to support the drivers
* that we care about
*/
#ifdef CONFIG_USBHOST_HUB
/* Initialize USB hub support */
ret = usbhost_hub_initialize();
if (ret < 0)
{
syslog(LOG_ERR, "ERROR: usbhost_hub_initialize failed: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_MSC
/* Register the USB host Mass Storage Class */
ret = usbhost_msc_initialize();
if (ret != OK)
{
syslog(LOG_ERR,
"ERROR: Failed to register the mass storage class: %d\n", ret);
}
#endif
#ifdef CONFIG_USBHOST_CDCACM
/* Register the CDC/ACM serial class */
ret = usbhost_cdcacm_initialize();
if (ret != OK)
{
uerr("ERROR: Failed to register the CDC/ACM serial class\n");
}
#endif
#ifdef CONFIG_USBHOST_HIDKBD
/* Register the USB host HID keyboard class driver */
ret = usbhost_kbdinit();
if (ret != OK)
{
uerr("ERROR: Failed to register the KBD class\n");
}
#endif
/* Enable PHY and clocks */
ehci_hwinit();
/* Then get an instance of the USB EHCI interface. */
g_ehciconn = kinetis_ehci_initialize(0);
if (!g_ehciconn)
{
uerr("ERROR: kinetis_ehci_initialize failed\n");
return -ENODEV;
}
/* Start a thread to handle device connection. */
pid = kthread_create("EHCI Monitor", CONFIG_USBHOST_DEFPRIO,
CONFIG_USBHOST_STACKSIZE,
(main_t)ehci_waiter, (FAR char * const *)NULL);
if (pid < 0)
{
uerr("ERROR: Failed to create ehci_waiter task: %d\n", ret);
return -ENODEV;
}
return OK;
}
/*****************************************************************************
* Name: kinetis_usbhost_vbusdrive
*
* Description:
* Enable/disable driving of VBUS 5V output. This function must be
* provided by each platform that implements the OHCI or EHCI host
* interface
*
* Input Parameters:
* rhport - Selects root hub port to be powered host interface.
* Since the KINETIS has only a downstream port, zero is
* the only possible value for this parameter.
* enable - true: enable VBUS power; false: disable VBUS power
*
* Returned Value:
* None
*
*****************************************************************************/
#define HCOR ((volatile struct ehci_hcor_s *)KINETIS_USBHS_HCOR_BASE)
void kinetis_usbhost_vbusdrive(int rhport, bool enable)
{
uint32_t regval;
uinfo("RHPort%d: enable=%d\n", rhport + 1, enable);
/* The KINETIS has only a single root hub port */
if (rhport == 0)
{
/* Then enable or disable VBUS power */
regval = HCOR->portsc[rhport];
regval &= ~EHCI_PORTSC_PP;
if (enable)
{
regval |= EHCI_PORTSC_PP;
}
HCOR->portsc[rhport] = regval;
}
}
/****************************************************************************
* Name: kinetis_setup_overcurrent
*
* Description:
* Setup to receive an interrupt-level callback if an overcurrent condition
* is detected.
*
* Input Parameters:
* handler - New overcurrent interrupt handler
* arg - The argument that will accompany the interrupt
*
* Returned Value:
* Zero (OK) returned on success; a negated errno value is returned on
* failure.
*
****************************************************************************/
#if 0 /* Not ready yet */
int kinetis_setup_overcurrent(xcpt_t handler, void *arg)
{
irqstate_t flags;
/* Disable interrupts until we are done. This guarantees that the
* following operations are atomic.
*/
flags = enter_critical_section();
/* Configure the interrupt */
#warning Missing logic
leave_critical_section(flags);
return OK;
}
#endif /* 0 */
#endif /* CONFIG_KINETIS_USBOTG || CONFIG_USBHOST */