qemu/armv7a: add Symmetric Multi-Processing (SMP) support
Bringup Co-Processor by PSCI(Power State Coordination Interface) Signed-off-by: chao an <anchao@lixiang.com>
This commit is contained in:
chao an
Xiang Xiao
parent
6b608ab6a2
commit
c7770fddfe
@ -22,3 +22,7 @@ include armv7-a/Make.defs
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# qemu-specific C source files
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# qemu-specific C source files
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CHIP_CSRCS = qemu_boot.c qemu_serial.c qemu_irq.c qemu_timer.c qemu_memorymap.c
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CHIP_CSRCS = qemu_boot.c qemu_serial.c qemu_irq.c qemu_timer.c qemu_memorymap.c
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ifeq ($(CONFIG_SMP),y)
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CHIP_CSRCS += qemu_cpuboot.c
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endif
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@ -26,6 +26,7 @@
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#include "arm_internal.h"
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#include "arm_internal.h"
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#include "qemu_boot.h"
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#include "qemu_irq.h"
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#include "qemu_irq.h"
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#include "qemu_memorymap.h"
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#include "qemu_memorymap.h"
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@ -72,4 +73,12 @@ void arm_boot(void)
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arm_earlyserialinit();
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arm_earlyserialinit();
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#endif
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#endif
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/* Now we can enable all other CPUs. The enabled CPUs will start execution
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* at __cpuN_start and, after very low-level CPU initialization has been
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* performed, will branch to arm_cpu_boot()
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* (see arch/arm/src/armv7-a/smp.h)
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*/
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qemu_cpu_enable();
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}
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}
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83
arch/arm/src/qemu/qemu_boot.h
Normal file
83
arch/arm/src/qemu/qemu_boot.h
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@ -0,0 +1,83 @@
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/****************************************************************************
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* arch/arm/src/qemu/qemu_boot.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_QEMU_QEMU_BOOT_H
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#define __ARCH_ARM_SRC_QEMU_QEMU_BOOT_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/compiler.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <arch/chip/chip.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Name: qemu_cpu_enable
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*
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* Description:
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* Called from CPU0 to enable all other CPUs. The enabled CPUs will start
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* execution at __cpuN_start and, after very low-level CPU initialization
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* has been performed, will branch to arm_cpu_boot()
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* (see arch/arm/src/armv7-a/smp.h)
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_SMP
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void qemu_cpu_enable(void);
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#else
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# define qemu_cpu_enable()
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_QEMU_QEMU_BOOT_H */
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172
arch/arm/src/qemu/qemu_cpuboot.c
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172
arch/arm/src/qemu/qemu_cpuboot.c
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@ -0,0 +1,172 @@
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/****************************************************************************
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* arch/arm/src/qemu/qemu_cpuboot.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <nuttx/arch.h>
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#include <nuttx/sched.h>
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#include <arch/irq.h>
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#include "arm_internal.h"
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#include "sctlr.h"
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#include "smp.h"
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#include "scu.h"
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#include "gic.h"
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#include "mmu.h"
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#include "barriers.h"
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#include "arm_cpu_psci.h"
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#ifdef CONFIG_SMP
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/****************************************************************************
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* Private Data
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****************************************************************************/
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static const start_t g_cpu_boot[CONFIG_SMP_NCPUS] =
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{
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0,
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#if CONFIG_SMP_NCPUS > 1
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__cpu1_start,
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#endif
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#if CONFIG_SMP_NCPUS > 2
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__cpu2_start,
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#endif
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#if CONFIG_SMP_NCPUS > 3
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__cpu3_start
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#endif
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};
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/* Symbols defined via the linker script */
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extern uint8_t _vector_start[]; /* Beginning of vector block */
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: qemu_cpu_enable
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*
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* Description:
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* Called from CPU0 to enable all other CPUs. The enabled CPUs will start
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* execution at __cpuN_start and, after very low-level CPU initialization
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* has been performed, will branch to arm_cpu_boot()
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* (see arch/arm/src/armv7-a/smp.h)
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void qemu_cpu_enable(void)
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{
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int cpu;
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for (cpu = 1; cpu < CONFIG_SMP_NCPUS; cpu++)
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{
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/* Then enable the CPU */
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psci_cpu_on(CORE_TO_MPID(cpu, 0), (uintptr_t)g_cpu_boot[cpu]);
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}
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}
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/****************************************************************************
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* Name: arm_cpu_boot
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*
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* Description:
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* Continues the C-level initialization started by the assembly language
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* __cpu[n]_start function. At a minimum, this function needs to
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* initialize interrupt handling and, perhaps, wait on WFI for
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* arm_cpu_start() to issue an SGI.
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*
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* This function must be provided by the each ARMv7-A MCU and implement
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* MCU-specific initialization logic.
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*
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* Input Parameters:
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* cpu - The CPU index. This is the same value that would be obtained by
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* calling up_cpu_index();
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*
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* Returned Value:
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* Does not return.
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*
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****************************************************************************/
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void arm_cpu_boot(int cpu)
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{
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/* Enable SMP cache coherency for the CPU */
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arm_enable_smp(cpu);
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/* Initialize the FPU */
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arm_fpuconfig();
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/* Initialize the Generic Interrupt Controller (GIC) for CPUn (n != 0) */
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arm_gic_initialize();
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#ifdef CONFIG_ARCH_LOWVECTORS
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/* If CONFIG_ARCH_LOWVECTORS is defined, then the vectors located at the
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* beginning of the .text region must appear at address at the address
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* specified in the VBAR. There are two ways to accomplish this:
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*
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* 1. By explicitly mapping the beginning of .text region with a page
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* table entry so that the virtual address zero maps to the beginning
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* of the .text region. VBAR == 0x0000:0000.
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*
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* 2. Set the Cortex-A5 VBAR register so that the vector table address
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* is moved to a location other than 0x0000:0000.
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*
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* The second method is used by this logic.
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*/
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/* Set the VBAR register to the address of the vector table */
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DEBUGASSERT((((uintptr_t)_vector_start) & ~VBAR_MASK) == 0);
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cp15_wrvbar((uint32_t)_vector_start);
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#endif /* CONFIG_ARCH_LOWVECTORS */
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#ifndef CONFIG_SUPPRESS_INTERRUPTS
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/* And finally, enable interrupts */
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up_irq_enable();
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#endif
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/* The next thing that we expect to happen is for logic running on CPU0
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* to call up_cpu_start() which generate an SGI and a context switch to
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* the configured NuttX IDLE task.
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*/
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for (; ; )
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{
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asm("WFI");
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}
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}
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#endif /* CONFIG_SMP */
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