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arch/xtensa/xtensa_sigdeliver.c: Remove old code that was preventing

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jumping back to the assembly signal trampoline and getting into its
infinite loop.

Signed-off-by: Abdelatif Guettouche <abdelatif.guettouche@espressif.com>
This commit is contained in:
Abdelatif Guettouche 2022-05-31 10:08:29 +02:00 committed by Xiang Xiao
parent c99776659f
commit c7823f7914
1 changed files with 0 additions and 34 deletions
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34
arch/xtensa/src/common/xtensa_sigdeliver.c
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@ -139,40 +139,6 @@ void xtensa_sig_deliver(void)
rtcb->xcp.sigdeliver = NULL; /* Allows next handler to be scheduled */ rtcb->xcp.sigdeliver = NULL; /* Allows next handler to be scheduled */
/* Issue:
*
* Task1 --> process
* --> xtensa_context_save(S1)
* --> s32i a0, a2, (4 * REG_A0)
* --> rtcb->xcp.regs[REG_A0] = A0
*
* Task preemption
*
* Task2 --> Post signal to Task1
* --> Wake up Task1
*
* Task1 --> xtensa_sig_deliver
* --> up_irq_enable()
* --> Task preemption
*
* Task preemption --> xtensa_context_save
* --> rtcb->xcp.regs[REG_A0] = A0 of "xtensa_sig_deliver"
* = _xtensa_sig_trampoline + 6
* = "j 1b"
*
* Process ...
*
* Task1 --> xtensa_sig_deliver
* --> xtensa_context_restore
* --> xtensa_context_save(S1)
* --> l32i a0, a2, (4 * REG_A0)
* --> a0 = "j 1b"
* --> ret
* --> run "j 1b"
*/
rtcb->xcp.regs[REG_A0] = regs[REG_A0];
/* Then restore the correct state for this thread of execution. /* Then restore the correct state for this thread of execution.
* NOTE: The co-processor state should already be correct. * NOTE: The co-processor state should already be correct.
*/ */