Documentation: various improvements for stm32xx documentation
This commit is contained in:
raiden00pl
Xiang Xiao
parent
612b8320bb
commit
c795e06e01
@ -25,36 +25,31 @@ The following list indicates peripherals supported in NuttX:
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========== ======= =====
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Peripheral Support Notes
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========== ======= =====
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IRQs Yes
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GPIO Yes
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EXTI Yes
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HSE Yes
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PLL Yes
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HSI Yes
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MSI Yes
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LSE Yes
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RCC Yes
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SYSCFG Yes
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USART Yes
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FLASH No
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DMA Yes
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SPI Yes
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I2S No
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I2C Yes
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RTC No
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Timers Yes
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IRTIM No
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PM No
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RNG Yes
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CRC No
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PM No
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RCC Yes
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CSR No
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GPIO Yes
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SYSCFG Yes
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DMA Yes
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EXTI Yes
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ADC Yes
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DAC No
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COMP No
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WWDG No
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TSC No
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TIM Yes
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IRTIM No
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IWDG No
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WWDG No
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RTC No
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I2C Yes
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USART Yes
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SPI Yes
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I2S No
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CAN No
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HDMI-CEC No
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USB Yes
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HDMI-CEC No
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========== ======= =====
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Supported Boards
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@ -2,7 +2,7 @@
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CloudController
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===============
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This README discusses issues unique to NuttX configurations for the CloudController
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This page discusses issues unique to NuttX configurations for the CloudController
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development board featuring the STMicro STM32F107VCT MCU.
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Features of the CloudController board include:
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@ -2,16 +2,16 @@
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ET-STM32 Stamp
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==============
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This README discusses issues/thoughts unique to NuttX configuration(s) for the
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This page discusses issues/thoughts unique to NuttX configuration(s) for the
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ET-STM32 Stamp board from Futurlec (https://www.futurlec.com/ET-STM32_Stamp.shtml).
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Microprocessor: 32-bit ARM Cortex M3 at 72MHz STM32F103RET6
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Memory: 512 KB Flash and 64 KB SRAM
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I/O Pins Out: 48
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ADCs: 16 (at 12-bit resolution)
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DACs: 2 (at 12-bit resolution)
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Peripherals: RTC, 4 timers, 2 I2Cs, 3 SPI ports, 1 on-board UART (upto 5 channels)
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Other: Sleep, stop, and standby modes; serial wire debug and JTAG interfaces
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- Microprocessor: 32-bit ARM Cortex M3 at 72MHz STM32F103RET6
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- Memory: 512 KB Flash and 64 KB SRAM
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- I/O Pins Out: 48
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- ADCs: 16 (at 12-bit resolution)
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- DACs: 2 (at 12-bit resolution)
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- Peripherals: RTC, 4 timers, 2 I2Cs, 3 SPI ports, 1 on-board UART (upto 5 channels)
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- Other: Sleep, stop, and standby modes; serial wire debug and JTAG interfaces
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Please see link below for board specific details:
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@ -2,7 +2,7 @@
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fire-stm2v2
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===========
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This README discusses issues unique to NuttX configurations for the M3
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This page discusses issues unique to NuttX configurations for the M3
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Wildfire development board (STM32F103VET6). See http://firestm32.taobao.com
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This configuration should support both the version 2 and version 3 of the
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@ -2,7 +2,7 @@
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HY-MiniSTM32V
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=============
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This README discusses issues unique to NuttX configurations for the
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This page discusses issues unique to NuttX configurations for the
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HY-MiniSTM32V development board.
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ST Bootloader
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@ -2,15 +2,15 @@
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maple
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=====
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This README discusses issues unique to NuttX configurations for the
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This page discusses issues unique to NuttX configurations for the
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maple board from LeafLabs (http://leaflabs.com).
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Microprocessor: 32-bit ARM Cortex M3 at 72MHz STM32F103RBT6 (STM32F103CBT6 for mini version)
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Memory: 120 KB Flash and 20 KB SRAM
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I/O Pins Out: 43 (34 for mini version)
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ADCs: 9 (at 12-bit resolution)
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Peripherals: 4 timers, 2 I2Cs, 2 SPI ports, 3 USARTs
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Other: Sleep, stop, and standby modes; serial wire debug and JTAG interfaces
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- Microprocessor: 32-bit ARM Cortex M3 at 72MHz STM32F103RBT6 (STM32F103CBT6 for mini version)
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- Memory: 120 KB Flash and 20 KB SRAM
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- I/O Pins Out: 43 (34 for mini version)
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- ADCs: 9 (at 12-bit resolution)
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- Peripherals: 4 timers, 2 I2Cs, 2 SPI ports, 3 USARTs
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- Other: Sleep, stop, and standby modes; serial wire debug and JTAG interfaces
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Please see below link for a list of maple devices and documentations.
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@ -2,7 +2,7 @@
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ST Nucleo F103RB
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================
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The Nucleo-F103RB is a member of the Nucleo-64 board family.
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The Nucleo F103RB is a member of the Nucleo-64 board family.
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Configurations
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==============
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@ -2,7 +2,7 @@
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Shenzhou IV
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===========
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This README discusses issues unique to NuttX configurations for the Shenzhou
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This page discusses issues unique to NuttX configurations for the Shenzhou
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IV development board from www.armjishu.com featuring the STMicro STM32F107VCT
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MCU. As of this writing, there are five models of the Shenzhou board:
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@ -2,7 +2,7 @@
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ST STM3210E-EVAL
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================
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This README discusses issues unique to NuttX configurations for the
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This page discusses issues unique to NuttX configurations for the
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STMicro STM3210E-EVAL development board.
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DFU and JTAG
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@ -2,23 +2,13 @@
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STM32 Tiny
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==========
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This README discusses issues unique to NuttX configurations for the
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This page discusses issues unique to NuttX configurations for the
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STM32 Tiny development board.
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This board is available from several vendors on the net, and may
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be sold under different names. It is based on a STM32 F103C8T6 MCU, and
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is (always ?) bundled with a nRF24L01 wireless communication module.
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Contents
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========
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- LEDs
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- PWM
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- UARTs
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- Timer Inputs/Outputs
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- STM32 Tiny -specific Configuration Options
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- Configurations
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LEDs
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====
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@ -2,7 +2,7 @@
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stm32f103-minimum
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=================
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This README discusses issues unique to NuttX configurations for the
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This page discusses issues unique to NuttX configurations for the
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STM32F103C8T6 Minimum System Development Board for ARM Microcontroller.
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STM32F103C8T6 Minimum System Development Boards:
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@ -2,10 +2,9 @@
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ST STM32VLDiscovery
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===================
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This README discusses issues unique to NuttX configurations for the STMicro
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This page discusses issues unique to NuttX configurations for the STMicro
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STM32VLDiscovery (Value Line Discovery) board.
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LEDs
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====
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@ -2,7 +2,7 @@
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ViewTool STM32F103/F107
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=======================
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This README discusses issues unique to NuttX configurations for the
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This page discusses issues unique to NuttX configurations for the
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ViewTool STM32F103/F107 V1.2 board. This board may be fitted with either
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- STM32F107VCT6, or
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@ -10,7 +10,33 @@ TODO
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Peripheral Support
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==================
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TODO
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The following list indicates peripherals supported in NuttX:
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========== ======= =====
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Peripheral Support Notes
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========== ======= =====
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FLASH Yes
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PM ?
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RCC Yes
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GPIO Yes
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EXTI Yes
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ADC Yes
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DAC Yes
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DMA Yes
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TIM Yes
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RTC Yes
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IWDG Yes
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WWDG Yes
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FSMC Yes
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SDIO Yes
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USB Yes
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CAN Yes
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SPI Yes
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I2C Yes
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USART Yes
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OTG_FS Yes
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ETH Yes
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========== ======= =====
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Supported Boards
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================
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@ -1,3 +1,5 @@
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================
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ST Nucleo F207ZG
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================
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The Nucleo F207ZG is a member of the Nucleo-144 board family.
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@ -1,6 +1,6 @@
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=============
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STM3220G-EVAL
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=============
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================
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ST STM3220G-EVAL
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================
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This page discusses issues unique to NuttX configurations for the
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STMicro STM3220G-EVAL development board.
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@ -15,140 +15,129 @@ The following list indicates peripherals supported in NuttX:
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========== ======= =====
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Peripheral Support Notes
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========== ======= =====
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IRQs Yes
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GPIO Yes
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EXTI Yes
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HSE Yes
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PLL Yes
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HSI Yes
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MSI Yes
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LSE Yes
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RCC Yes
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SYSCFG Yes
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USART Yes
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FLASH Yes
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CRC Yes
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PM ?
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RCC Yes
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GPIO Yes
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SYSCFG Yes
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EXTI Yes
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DMA Yes
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SPI Yes
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I2S Yes
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I2C Yes
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RTC Yes
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Timers Yes
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PM Yes
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RNG Yes
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CRC No
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CRYPTO Yes
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HASH No
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ADC Yes
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DAC Yes
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WWDG Yes
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DCMI No
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TIM Yes
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IWDG Yes
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WWDG Yes
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CRYP Yes
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RNG Yes
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HASH ?
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RTC Yes
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I2C Yes
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USART Yes
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SPI Yes
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SDIO Yes
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CAN Yes
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USB FS Yes
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USB HS Yes
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ETH Yes
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OTG_FS Yes
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OTG_HS Yes
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FSMC Yes
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========== ======= =====
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Memory
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======
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------
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CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case)::
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- CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case)
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CONFIG_RAM_SIZE=0x00010000 (64Kb)
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CONFIG_RAM_START - The start address of installed DRAM::
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CONFIG_RAM_START=0x20000000
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- CONFIG_RAM_START - The start address of installed DRAM
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In addition to internal SRAM, SRAM may also be available through the FSMC.
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In order to use FSMC SRAM, the following additional things need to be
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present in the NuttX configuration file:
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CONFIG_STM32_EXTERNAL_RAM - Indicates that SRAM is available via the
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FSMC (as opposed to an LCD or FLASH).
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- CONFIG_STM32_EXTERNAL_RAM - Indicates that SRAM is available via the
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FSMC (as opposed to an LCD or FLASH).
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CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space (hex)
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- CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC address space (hex)
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CONFIG_HEAP2_SIZE - The size of the SRAM in the FSMC address space (decimal)
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- CONFIG_HEAP2_SIZE - The size of the SRAM in the FSMC address space (decimal)
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CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that have LEDs
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- CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that have LEDs
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CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
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stack. If defined, this symbol is the size of the interrupt
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stack in bytes. If not defined, the user task stacks will be
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used during interrupt handling.
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- CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
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stack. If defined, this symbol is the size of the interrupt
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stack in bytes. If not defined, the user task stacks will be
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used during interrupt handling.
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CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
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- CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
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CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
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- CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
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Clock
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=====
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-----
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CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
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configuration features.::
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- CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
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configuration features.::
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CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
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CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
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of delay loops
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CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
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- CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
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of delay loops
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CAN
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===
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---
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CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
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CONFIG_STM32_CAN2 must also be defined)
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- CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
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CONFIG_STM32_CAN2 must also be defined)
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CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID.
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Default Standard 11-bit IDs.
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- CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID.
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Default Standard 11-bit IDs.
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CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
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Default: 8
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- CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
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Default: 8
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CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
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Default: 4
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- CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
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Default: 4
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CONFIG_STM32_CAN1 - Enable support for CAN1
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- CONFIG_STM32_CAN1 - Enable support for CAN1
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CONFIG_STM32_CAN2 - Enable support for CAN2
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- CONFIG_STM32_CAN2 - Enable support for CAN2
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CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate.
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Required if CONFIG_STM32_CAN1 is defined.
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- CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate.
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Required if CONFIG_STM32_CAN1 is defined.
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CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate.
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Required if CONFIG_STM32_CAN2 is defined.
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- CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate.
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Required if CONFIG_STM32_CAN2 is defined.
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CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
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Default: 6
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- CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
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Default: 6
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CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
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Default: 7
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- CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
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Default: 7
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CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
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dump of all CAN registers.
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- CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
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dump of all CAN registers.
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FSMC SRAM
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=========
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---------
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Internal SRAM is available in all members of the STM32 family. In addition
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to internal SRAM, SRAM may also be available through the FSMC. In order to
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use FSMC SRAM, the following additional things need to be present in the
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NuttX configuration file::
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NuttX configuration file:
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CONFIG_STM32_FSMC=y : Enables the FSMC
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CONFIG_STM32_EXTERNAL_RAM=y : Indicates that SRAM is available via the
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FSMC (as opposed to an LCD or FLASH).
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CONFIG_HEAP2_BASE : The base address of the SRAM in the FSMC
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address space
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CONFIG_HEAP2_SIZE : The size of the SRAM in the FSMC
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address space
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CONFIG_MM_REGIONS : Must be set to a large enough value to
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include the FSMC SRAM
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- CONFIG_STM32_FSMC=y - Enables the FSMC
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- CONFIG_STM32_EXTERNAL_RAM=y - Indicates that SRAM is available via the
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FSMC (as opposed to an LCD or FLASH).
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- CONFIG_HEAP2_BASE - The base address of the SRAM in the FSMC
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address space
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- CONFIG_HEAP2_SIZE - The size of the SRAM in the FSMC
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address space
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- CONFIG_MM_REGIONS - Must be set to a large enough value to
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include the FSMC SRAM
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TIMER
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=====
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Timers
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------
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Timer devices may be used for different purposes. One special purpose is
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to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
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@ -156,147 +145,155 @@ is defined (as above) then the following may also be defined to indicate that
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the timer is intended to be used for pulsed output modulation, ADC conversion,
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or DAC conversion. Note that ADC/DAC require two definition: Not only do you have
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to assign the timer (n) for used by the ADC or DAC, but then you also have to
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configure which ADC or DAC (m) it is assigned to.::
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configure which ADC or DAC (m) it is assigned to.:
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CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
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CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
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CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
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CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
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CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
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- CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
|
||||
- CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
|
||||
- CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
|
||||
- CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
|
||||
- CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
|
||||
|
||||
For each timer that is enabled for PWM usage, we need the following additional
|
||||
configuration settings::
|
||||
configuration settings:
|
||||
|
||||
CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
|
||||
- CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
|
||||
|
||||
NOTE: The STM32 timers are each capable of generating different signals on
|
||||
each of the four channels with different duty cycles. That capability is
|
||||
not supported by this driver: Only one output channel per timer.
|
||||
|
||||
JTAG
|
||||
====
|
||||
----
|
||||
|
||||
JTAG Enable settings (by default JTAG-DP and SW-DP are disabled)::
|
||||
JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):
|
||||
|
||||
CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
but without JNTRST.
|
||||
CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
|
||||
- CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
|
||||
- CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
but without JNTRST.
|
||||
|
||||
- CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
|
||||
|
||||
USART
|
||||
=====
|
||||
-----
|
||||
|
||||
CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
|
||||
m (m=4,5) for the console and ttys0 (default is the USART1).
|
||||
Options:
|
||||
|
||||
CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
This specific the size of the receive buffer
|
||||
- CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UARTm (m=4,5)
|
||||
for the console and ttys0 (default is the USART1).
|
||||
|
||||
CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
|
||||
being sent. This specific the size of the transmit buffer
|
||||
- CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
This specific the size of the receive buffer
|
||||
|
||||
CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
|
||||
- CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
|
||||
being sent. This specific the size of the transmit buffer
|
||||
|
||||
CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
|
||||
- CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
|
||||
|
||||
CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
- CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
|
||||
|
||||
CONFIG_U[S]ARTn_2STOP - Two stop bits
|
||||
- CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
|
||||
- CONFIG_U[S]ARTn_2STOP - Two stop bits
|
||||
|
||||
SPI
|
||||
===
|
||||
---
|
||||
|
||||
CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
|
||||
support. Non-interrupt-driven, poll-waiting is recommended if the
|
||||
interrupt rate would be to high in the interrupt driven case.
|
||||
- CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
|
||||
support. Non-interrupt-driven, poll-waiting is recommended if the
|
||||
interrupt rate would be to high in the interrupt driven case.
|
||||
|
||||
CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
|
||||
Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
|
||||
- CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
|
||||
Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
|
||||
|
||||
SDIO
|
||||
====
|
||||
----
|
||||
|
||||
CONFIG_SDIO_DMA - Support DMA data transfers. Requires CONFIG_STM32_SDIO
|
||||
and CONFIG_STM32_DMA2.
|
||||
Options:
|
||||
|
||||
CONFIG_STM32_SDIO_PRI - Select SDIO interrupt priority. Default: 128
|
||||
- CONFIG_SDIO_DMA - Support DMA data transfers. Requires CONFIG_STM32_SDIO
|
||||
and CONFIG_STM32_DMA2.
|
||||
|
||||
CONFIG_STM32_SDIO_DMAPRIO - Select SDIO DMA interrupt priority.
|
||||
Default: Medium
|
||||
- CONFIG_STM32_SDIO_PRI - Select SDIO interrupt priority. Default: 128
|
||||
|
||||
CONFIG_STM32_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
|
||||
4-bit transfer mode.
|
||||
- CONFIG_STM32_SDIO_DMAPRIO - Select SDIO DMA interrupt priority.
|
||||
Default: Medium
|
||||
|
||||
- CONFIG_STM32_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
|
||||
4-bit transfer mode.
|
||||
|
||||
ETH
|
||||
===
|
||||
---
|
||||
|
||||
CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
|
||||
Options:
|
||||
|
||||
CONFIG_STM32_MII - Support Ethernet MII interface
|
||||
- CONFIG_STM32_PHYADDR - The 5-bit address of the PHY on the board
|
||||
|
||||
CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
|
||||
- CONFIG_STM32_MII - Support Ethernet MII interface
|
||||
|
||||
CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
|
||||
- CONFIG_STM32_MII_MCO1 - Use MCO1 to clock the MII interface
|
||||
|
||||
CONFIG_STM32_RMII - Support Ethernet RMII interface
|
||||
- CONFIG_STM32_MII_MCO2 - Use MCO2 to clock the MII interface
|
||||
|
||||
CONFIG_STM32_AUTONEG - Use PHY autonegotiation to determine speed and mode
|
||||
- CONFIG_STM32_RMII - Support Ethernet RMII interface
|
||||
|
||||
CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
|
||||
may be defined to select full duplex mode. Default: half-duplex
|
||||
- CONFIG_STM32_AUTONEG - Use PHY autonegotiation to determine speed and mode
|
||||
|
||||
CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
|
||||
may be defined to select 100 MBps speed. Default: 10 Mbps
|
||||
- CONFIG_STM32_ETHFD - If CONFIG_STM32_AUTONEG is not defined, then this
|
||||
may be defined to select full duplex mode. Default: half-duplex
|
||||
|
||||
CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. The PHY status register address may diff from PHY to PHY. This
|
||||
configuration sets the address of the PHY status register.
|
||||
- CONFIG_STM32_ETH100MBPS - If CONFIG_STM32_AUTONEG is not defined, then this
|
||||
may be defined to select 100 MBps speed. Default: 10 Mbps
|
||||
|
||||
CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. This provides bit mask indicating 10 or 100MBps speed.
|
||||
- CONFIG_STM32_PHYSR - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. The PHY status register address may diff from PHY to PHY. This
|
||||
configuration sets the address of the PHY status register.
|
||||
|
||||
CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. This provides the value of the speed bit(s) indicating 100MBps speed.
|
||||
- CONFIG_STM32_PHYSR_SPEED - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. This provides bit mask indicating 10 or 100MBps speed.
|
||||
|
||||
CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. This provide bit mask indicating full or half duplex modes.
|
||||
- CONFIG_STM32_PHYSR_100MBPS - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. This provides the value of the speed bit(s) indicating 100MBps speed.
|
||||
|
||||
CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. This provides the value of the mode bits indicating full duplex mode.
|
||||
- CONFIG_STM32_PHYSR_MODE - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. This provide bit mask indicating full or half duplex modes.
|
||||
|
||||
CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
|
||||
but some hooks are indicated with this condition.
|
||||
- CONFIG_STM32_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32_AUTONEG is
|
||||
defined. This provides the value of the mode bits indicating full duplex mode.
|
||||
|
||||
- CONFIG_STM32_ETH_PTP - Precision Time Protocol (PTP). Not supported
|
||||
but some hooks are indicated with this condition.
|
||||
|
||||
USB OTG FS
|
||||
==========
|
||||
----------
|
||||
|
||||
STM32 USB OTG FS Host Driver Support
|
||||
|
||||
Pre-requisites::
|
||||
Pre-requisites:
|
||||
|
||||
CONFIG_USBHOST - Enable general USB host support
|
||||
CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block
|
||||
CONFIG_STM32_SYSCFG - Needed
|
||||
- CONFIG_USBHOST - Enable general USB host support
|
||||
- CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block
|
||||
- CONFIG_STM32_SYSCFG - Needed
|
||||
|
||||
CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
|
||||
Default 128 (512 bytes)
|
||||
- CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
|
||||
Default 128 (512 bytes)
|
||||
|
||||
CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
|
||||
in 32-bit words. Default 96 (384 bytes)
|
||||
- CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
|
||||
in 32-bit words. Default 96 (384 bytes)
|
||||
|
||||
CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
|
||||
words. Default 96 (384 bytes)
|
||||
- CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
|
||||
words. Default 96 (384 bytes)
|
||||
|
||||
CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128
|
||||
- CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128
|
||||
|
||||
CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
|
||||
want to do that?
|
||||
- CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
|
||||
want to do that?
|
||||
|
||||
CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access
|
||||
debug. Depends on CONFIG_DEBUG_FEATURES.
|
||||
- CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access
|
||||
debug. Depends on CONFIG_DEBUG_FEATURES.
|
||||
|
||||
CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
|
||||
packets. Depends on CONFIG_DEBUG_FEATURES.
|
||||
- CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
|
||||
packets. Depends on CONFIG_DEBUG_FEATURES.
|
||||
|
||||
Supported Boards
|
||||
================
|
||||
|
||||
@ -10,41 +10,69 @@ TODO
|
||||
Peripheral Support
|
||||
==================
|
||||
|
||||
TODO
|
||||
The following list indicates peripherals supported in NuttX:
|
||||
|
||||
========== ======= =====
|
||||
Peripheral Support Notes
|
||||
========== ======= =====
|
||||
FLASH Yes
|
||||
CRC Yes
|
||||
PM ?
|
||||
RCC Yes
|
||||
GPIO Yes
|
||||
SYSCFG Yes
|
||||
DMA Yes
|
||||
EXTI Yes
|
||||
ADC Yes
|
||||
SDADC Yes
|
||||
DAC Yes
|
||||
COMP Yes
|
||||
OPAMP Yes
|
||||
TSC No
|
||||
TIM Yes
|
||||
HRTIM Yes
|
||||
IRTIM No
|
||||
IWDG ?
|
||||
WWDG ?
|
||||
RTC Yes
|
||||
I2C Yes
|
||||
USART Yes
|
||||
SPI Yes
|
||||
I2S ?
|
||||
CAN Yes
|
||||
USB Yes
|
||||
HDMI-CEC No
|
||||
========== ======= =====
|
||||
|
||||
Memory
|
||||
------
|
||||
|
||||
CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case)::
|
||||
- CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case)
|
||||
|
||||
CONFIG_RAM_SIZE=0x00010000 (64Kb)
|
||||
- CONFIG_RAM_START - The start address of installed DRAM
|
||||
|
||||
CONFIG_RAM_START - The start address of installed DRAM::
|
||||
- CONFIG_STM32_CCMEXCLUDE - Exclude CCM SRAM from the HEAP
|
||||
|
||||
CONFIG_RAM_START=0x20000000
|
||||
- CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
|
||||
stack. If defined, this symbol is the size of the interrupt
|
||||
stack in bytes. If not defined, the user task stacks will be
|
||||
used during interrupt handling.
|
||||
|
||||
CONFIG_STM32_CCMEXCLUDE - Exclude CCM SRAM from the HEAP
|
||||
|
||||
CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
|
||||
stack. If defined, this symbol is the size of the interrupt
|
||||
stack in bytes. If not defined, the user task stacks will be
|
||||
used during interrupt handling.
|
||||
|
||||
CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
|
||||
- CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
|
||||
|
||||
Clock
|
||||
-----
|
||||
|
||||
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
|
||||
configuration features.::
|
||||
- CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
|
||||
configuration features.::
|
||||
|
||||
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
|
||||
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
|
||||
|
||||
CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
|
||||
of delay loops
|
||||
- CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
|
||||
of delay loops
|
||||
|
||||
TIMER
|
||||
-----
|
||||
Timers
|
||||
------
|
||||
|
||||
Timer devices may be used for different purposes. One special purpose is
|
||||
to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
|
||||
@ -54,16 +82,16 @@ or DAC conversion. Note that ADC/DAC require two definition: Not only do you ha
|
||||
to assign the timer (n) for used by the ADC or DAC, but then you also have to
|
||||
configure which ADC or DAC (m) it is assigned to.
|
||||
|
||||
CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
|
||||
CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
|
||||
CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
|
||||
CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
|
||||
CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
|
||||
- CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
|
||||
- CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
|
||||
- CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
|
||||
- CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
|
||||
- CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
|
||||
|
||||
For each timer that is enabled for PWM usage, we need the following additional
|
||||
configuration settings:
|
||||
|
||||
CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
|
||||
- CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
|
||||
|
||||
NOTE: The STM32 timers are each capable of generating different signals on
|
||||
each of the four channels with different duty cycles. That capability is
|
||||
@ -72,75 +100,120 @@ not supported by this driver: Only one output channel per timer.
|
||||
JTAG
|
||||
----
|
||||
|
||||
CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):
|
||||
|
||||
CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
but without JNTRST.
|
||||
- CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
|
||||
CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
|
||||
- CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
but without JNTRST.
|
||||
|
||||
- CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
|
||||
|
||||
USART
|
||||
-----
|
||||
|
||||
CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
|
||||
m (m=4,5) for the console and ttys0 (default is the USART1).
|
||||
Options:
|
||||
|
||||
CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
This specific the size of the receive buffer
|
||||
- CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UARTm (m=4,5)
|
||||
for the console and ttys0 (default is the USART1).
|
||||
|
||||
CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
|
||||
being sent. This specific the size of the transmit buffer
|
||||
- CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
This specific the size of the receive buffer
|
||||
|
||||
CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
|
||||
- CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
|
||||
being sent. This specific the size of the transmit buffer
|
||||
|
||||
CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
|
||||
- CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
|
||||
|
||||
CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
- CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
|
||||
|
||||
CONFIG_U[S]ARTn_2STOP - Two stop bits
|
||||
- CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
|
||||
CAN
|
||||
---
|
||||
- CONFIG_U[S]ARTn_2STOP - Two stop bits
|
||||
|
||||
CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
|
||||
CONFIG_STM32_CAN2 must also be defined)
|
||||
CAN character device
|
||||
--------------------
|
||||
|
||||
CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default
|
||||
Standard 11-bit IDs.
|
||||
- CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
|
||||
CONFIG_STM32_CAN2 must also be defined)
|
||||
|
||||
CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
|
||||
Default: 8
|
||||
- CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default
|
||||
Standard 11-bit IDs.
|
||||
|
||||
CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
|
||||
Default: 4
|
||||
- CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
|
||||
Default: 8
|
||||
|
||||
CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
|
||||
mode for testing. The STM32 CAN driver does support loopback mode.
|
||||
- CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
|
||||
Default: 4
|
||||
|
||||
CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1
|
||||
is defined.
|
||||
- CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
|
||||
mode for testing. The STM32 CAN driver does support loopback mode.
|
||||
|
||||
CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2
|
||||
is defined.
|
||||
- CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1
|
||||
is defined.
|
||||
|
||||
CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
|
||||
Default: 6
|
||||
- CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2
|
||||
is defined.
|
||||
|
||||
CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
|
||||
Default: 7
|
||||
- CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
|
||||
Default: 6
|
||||
|
||||
CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
|
||||
dump of all CAN registers.
|
||||
- CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
|
||||
Default: 7
|
||||
|
||||
- CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
|
||||
dump of all CAN registers.
|
||||
|
||||
CAN SocketCAN
|
||||
-------------
|
||||
|
||||
TODO
|
||||
|
||||
SPI
|
||||
---
|
||||
|
||||
CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
|
||||
support. Non-interrupt-driven, poll-waiting is recommended if the
|
||||
interrupt rate would be to high in the interrupt driven case.
|
||||
- CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
|
||||
support. Non-interrupt-driven, poll-waiting is recommended if the
|
||||
interrupt rate would be to high in the interrupt driven case.
|
||||
|
||||
CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
|
||||
Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
|
||||
- CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
|
||||
Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
|
||||
|
||||
USB FS
|
||||
------
|
||||
|
||||
TODO
|
||||
|
||||
FPU
|
||||
===
|
||||
|
||||
FPU Configuration Options
|
||||
-------------------------
|
||||
|
||||
There are two version of the FPU support built into the STM32 port.
|
||||
|
||||
1. Non-Lazy Floating Point Register Save
|
||||
|
||||
In this configuration floating point register save and restore is
|
||||
implemented on interrupt entry and return, respectively. In this
|
||||
case, you may use floating point operations for interrupt handling
|
||||
logic if necessary. This FPU behavior logic is enabled by default
|
||||
with::
|
||||
|
||||
CONFIG_ARCH_FPU=y
|
||||
|
||||
2. Lazy Floating Point Register Save.
|
||||
|
||||
An alternative mplementation only saves and restores FPU registers only
|
||||
on context switches. This means: (1) floating point registers are not
|
||||
stored on each context switch and, hence, possibly better interrupt
|
||||
performance. But, (2) since floating point registers are not saved,
|
||||
you cannot use floating point operations within interrupt handlers.
|
||||
|
||||
This logic can be enabled by simply adding the following to your .config
|
||||
file::
|
||||
|
||||
CONFIG_ARCH_FPU=y
|
||||
|
||||
Supported Boards
|
||||
================
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
Axoloti
|
||||
=======
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the
|
||||
This page discusses issues unique to NuttX configurations for the
|
||||
Axoloti open source synthesizer board featuring the STM32F427IGH6
|
||||
MCU. The STM32F427IGH6 has a 180MHz Cortex-M4 core with 1MiB Flash
|
||||
memory and 256KiB of SRAM. The board features:
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
Mikroe Clicker2 STM32
|
||||
=====================
|
||||
|
||||
This is the README file for the port of NuttX to the Mikroe Clicker2 STM32
|
||||
This is the page file for the port of NuttX to the Mikroe Clicker2 STM32
|
||||
board based on the STMicro STM32F407VGT6 MCU.
|
||||
|
||||
Reference: https://shop.mikroe.com/development-boards/starter/clicker-2/stm32f4
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
mikroe-stm32f4
|
||||
==============
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the
|
||||
This page discusses issues unique to NuttX configurations for the
|
||||
MikroElektronika Mikromedia for STM32F4 development board. This is
|
||||
another board support by NuttX that uses the same STM32F407VGT6 MCU
|
||||
as does the STM32F4-Discovery board. This board, however, has very
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
ST Nucleo F401RE
|
||||
================
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the ST
|
||||
This page discusses issues unique to NuttX configurations for the ST
|
||||
NucleoF401RE and NucleoF411RE boards from ST Micro. See
|
||||
|
||||
http://www.st.com/web/catalog/mmc/FM141/SC1169/SS1577/LN1810/PF258797
|
||||
|
||||
@ -1,3 +1,5 @@
|
||||
================
|
||||
ST Nucleo F429ZI
|
||||
================
|
||||
|
||||
The Nucleo F429ZI is a member of the Nucleo-144 board family.
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
stm32f411-minimum
|
||||
=================
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the
|
||||
This page discusses issues unique to NuttX configurations for the
|
||||
WeAct Studio MiniF4 minimum system development board.
|
||||
|
||||
Board information
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
ST STM32F411E-Discovery
|
||||
=======================
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the STMicro
|
||||
This page discusses issues unique to NuttX configurations for the STMicro
|
||||
STM32F411E-Discovery board. See
|
||||
|
||||
http://www.st.com/content/ccc/resource/technical/document/user_manual/e9/d2/00/5e/15/46/44/0e/DM00148985.pdf/files/DM00148985.pdf/jcr:content/translations/en.DM00148985.pdf
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
================
|
||||
STM32F429I-DISCO
|
||||
================
|
||||
===================
|
||||
ST STM32F429I-DISCO
|
||||
===================
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the
|
||||
This page discusses issues unique to NuttX configurations for the
|
||||
STMicro STM32F429I-DISCO development board featuring the STM32F429ZIT6
|
||||
MCU. The STM32F429ZIT6 is a 180MHz Cortex-M4 operation with 2Mbit Flash
|
||||
memory and 256kbytes. The board features:
|
||||
|
||||
@ -15,75 +15,65 @@ The following list indicates peripherals supported in NuttX:
|
||||
========== ======= =====
|
||||
Peripheral Support Notes
|
||||
========== ======= =====
|
||||
IRQs Yes
|
||||
GPIO Yes
|
||||
EXTI Yes
|
||||
HSE Yes
|
||||
PLL Yes
|
||||
HSI Yes
|
||||
MSI Yes
|
||||
LSE Yes
|
||||
RCC Yes
|
||||
SYSCFG Yes
|
||||
USART Yes
|
||||
FLASH Yes
|
||||
CRC Yes
|
||||
PM ?
|
||||
RCC Yes
|
||||
GPIO Yes
|
||||
SYSCFG Yes
|
||||
DMA Yes
|
||||
SPI Yes
|
||||
I2C Yes
|
||||
I2S Yes
|
||||
FMPI2C No
|
||||
SPDIFRX No
|
||||
SAI No
|
||||
RTC Yes
|
||||
Timers Yes
|
||||
PM Yes
|
||||
RNG Yes
|
||||
CRC No
|
||||
HASH No
|
||||
DMA2D Yes
|
||||
EXTI Yes
|
||||
FMC Yes
|
||||
QUADSPI Yes
|
||||
ADC Yes
|
||||
DAC Yes
|
||||
WWDG Yes
|
||||
IWDG Yes
|
||||
CAN Yes
|
||||
USB FS Yes
|
||||
USB HS Yes
|
||||
ETH Yes
|
||||
FMC Yes
|
||||
QSPI Yes
|
||||
DCMI No
|
||||
AES Yes
|
||||
HDMI-CED No
|
||||
SDIO Yes
|
||||
LTDC Yes
|
||||
DSI No
|
||||
RNG Yes
|
||||
CRYP Yes
|
||||
HASH ?
|
||||
TIM Yes
|
||||
IWDG Yes
|
||||
WWDG Yes
|
||||
RTC Yes
|
||||
I2C Yes
|
||||
USART Yes
|
||||
SPI Yes
|
||||
I2S ?
|
||||
SAI No
|
||||
SDIO ?
|
||||
CAN Yes
|
||||
OTG_FS Yes
|
||||
OTG_HS Yes
|
||||
ETH Yes
|
||||
========== ======= =====
|
||||
|
||||
Memory
|
||||
------
|
||||
|
||||
CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
|
||||
- CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case)
|
||||
|
||||
CONFIG_RAM_SIZE=16384 (16Kb)
|
||||
- CONFIG_RAM_START - The start address of installed DRAM
|
||||
|
||||
CONFIG_RAM_START - The start address of installed DRAM
|
||||
- CONFIG_STM32_CCMEXCLUDE - Exclude CCM SRAM from the HEAP
|
||||
|
||||
CONFIG_RAM_START=0x20000000
|
||||
|
||||
CONFIG_STM32_CCMEXCLUDE - Exclude CCM SRAM from the HEAP
|
||||
|
||||
CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
|
||||
stack. If defined, this symbol is the size of the interrupt
|
||||
stack in bytes. If not defined, the user task stacks will be
|
||||
used during interrupt handling.
|
||||
- CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
|
||||
stack. If defined, this symbol is the size of the interrupt
|
||||
stack in bytes. If not defined, the user task stacks will be
|
||||
used during interrupt handling.
|
||||
|
||||
Clock
|
||||
-----
|
||||
|
||||
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
|
||||
configuration features.::
|
||||
- CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
|
||||
configuration features.::
|
||||
|
||||
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
|
||||
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
|
||||
|
||||
CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
|
||||
of delay loops
|
||||
- CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
|
||||
of delay loops
|
||||
|
||||
TIMER
|
||||
-----
|
||||
@ -96,16 +86,20 @@ or DAC conversion. Note that ADC/DAC require two definition: Not only do you ha
|
||||
to assign the timer (n) for used by the ADC or DAC, but then you also have to
|
||||
configure which ADC or DAC (m) it is assigned to.
|
||||
|
||||
CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
|
||||
CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
|
||||
CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
|
||||
CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
|
||||
CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
|
||||
- CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
|
||||
|
||||
- CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
|
||||
|
||||
- CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
|
||||
|
||||
- CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
|
||||
|
||||
- CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
|
||||
|
||||
For each timer that is enabled for PWM usage, we need the following additional
|
||||
configuration settings:
|
||||
|
||||
CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
|
||||
- CONFIG_STM32_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
|
||||
|
||||
NOTE: The STM32 timers are each capable of generating different signals on
|
||||
each of the four channels with different duty cycles. That capability is
|
||||
@ -114,121 +108,118 @@ not supported by this driver: Only one output channel per timer.
|
||||
JTAG
|
||||
----
|
||||
|
||||
CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
- CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
|
||||
CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
but without JNTRST.
|
||||
- CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
but without JNTRST.
|
||||
|
||||
CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
|
||||
- CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
|
||||
|
||||
USART
|
||||
-----
|
||||
|
||||
CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
|
||||
m (m=4,5) for the console and ttys0 (default is the USART1).
|
||||
- CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
|
||||
m (m=4,5) for the console and ttys0 (default is the USART1).
|
||||
|
||||
CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
This specific the size of the receive buffer
|
||||
- CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
This specific the size of the receive buffer
|
||||
|
||||
CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
|
||||
being sent. This specific the size of the transmit buffer
|
||||
- CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
|
||||
being sent. This specific the size of the transmit buffer
|
||||
|
||||
CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
|
||||
- CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
|
||||
|
||||
CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
|
||||
- CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
|
||||
|
||||
CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
- CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
|
||||
CONFIG_U[S]ARTn_2STOP - Two stop bits
|
||||
- CONFIG_U[S]ARTn_2STOP - Two stop bits
|
||||
|
||||
CAN
|
||||
---
|
||||
|
||||
CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
|
||||
CONFIG_STM32_CAN2 must also be defined)
|
||||
- CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
|
||||
CONFIG_STM32_CAN2 must also be defined)
|
||||
|
||||
CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default
|
||||
Standard 11-bit IDs.
|
||||
- CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default
|
||||
Standard 11-bit IDs.
|
||||
|
||||
CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
|
||||
Default: 8
|
||||
- CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
|
||||
Default: 8
|
||||
|
||||
CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
|
||||
Default: 4
|
||||
- CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
|
||||
Default: 4
|
||||
|
||||
CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
|
||||
mode for testing. The STM32 CAN driver does support loopback mode.
|
||||
- CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
|
||||
mode for testing. The STM32 CAN driver does support loopback mode.
|
||||
|
||||
CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1
|
||||
is defined.
|
||||
- CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1
|
||||
is defined.
|
||||
|
||||
CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2
|
||||
is defined.
|
||||
- CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2
|
||||
is defined.
|
||||
|
||||
CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
|
||||
Default: 6
|
||||
- CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
|
||||
Default: 6
|
||||
|
||||
CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
|
||||
Default: 7
|
||||
- CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
|
||||
Default: 7
|
||||
|
||||
CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
|
||||
dump of all CAN registers.
|
||||
- CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
|
||||
dump of all CAN registers.
|
||||
|
||||
SPI
|
||||
---
|
||||
|
||||
CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
|
||||
support. Non-interrupt-driven, poll-waiting is recommended if the
|
||||
interrupt rate would be to high in the interrupt driven case.
|
||||
- CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
|
||||
support. Non-interrupt-driven, poll-waiting is recommended if the
|
||||
interrupt rate would be to high in the interrupt driven case.
|
||||
|
||||
CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
|
||||
Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
|
||||
- CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
|
||||
Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
|
||||
|
||||
DMA
|
||||
---
|
||||
SDIO
|
||||
----
|
||||
|
||||
CONFIG_SDIO_DMA - Support DMA data transfers. Requires CONFIG_STM32_SDIO and CONFIG_STM32_DMA2.
|
||||
CONFIG_STM32_SDIO_PRI - Select SDIO interrupt priority. Default: 128
|
||||
- CONFIG_SDIO_DMA - Support DMA data transfers. Requires CONFIG_STM32_SDIO and CONFIG_STM32_DMA2.
|
||||
|
||||
CONFIG_STM32_SDIO_DMAPRIO - Select SDIO DMA interrupt priority. Default: Medium
|
||||
- CONFIG_STM32_SDIO_PRI - Select SDIO interrupt priority. Default: 128
|
||||
|
||||
CONFIG_STM32_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
|
||||
4-bit transfer mode.
|
||||
- CONFIG_STM32_SDIO_DMAPRIO - Select SDIO DMA interrupt priority. Default: Medium
|
||||
|
||||
- CONFIG_STM32_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default:
|
||||
4-bit transfer mode.
|
||||
|
||||
USB
|
||||
---
|
||||
|
||||
STM32 USB OTG FS Host Driver Support
|
||||
|
||||
Pre-requisites::
|
||||
Pre-requisites:
|
||||
|
||||
CONFIG_USBDEV - Enable USB device support
|
||||
CONFIG_USBHOST - Enable USB host support
|
||||
CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block
|
||||
CONFIG_STM32_SYSCFG - Needed
|
||||
CONFIG_SCHED_WORKQUEUE - Worker thread support is required
|
||||
- CONFIG_USBHOST - Enable general USB host support
|
||||
- CONFIG_STM32_OTGFS - Enable the STM32 USB OTG FS block
|
||||
- CONFIG_STM32_SYSCFG - Needed
|
||||
|
||||
Options:
|
||||
- CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
|
||||
Default 128 (512 bytes)
|
||||
|
||||
CONFIG_STM32_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
|
||||
Default 128 (512 bytes)
|
||||
- CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
|
||||
in 32-bit words. Default 96 (384 bytes)
|
||||
|
||||
CONFIG_STM32_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
|
||||
in 32-bit words. Default 96 (384 bytes)
|
||||
- CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
|
||||
words. Default 96 (384 bytes)
|
||||
|
||||
CONFIG_STM32_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
|
||||
words. Default 96 (384 bytes)
|
||||
- CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128
|
||||
|
||||
CONFIG_STM32_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128
|
||||
- CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
|
||||
want to do that?
|
||||
|
||||
CONFIG_STM32_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
|
||||
want to do that?
|
||||
- CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access
|
||||
debug. Depends on CONFIG_DEBUG_FEATURES.
|
||||
|
||||
CONFIG_STM32_USBHOST_REGDEBUG - Enable very low-level register access
|
||||
debug. Depends on CONFIG_DEBUG_FEATURES.
|
||||
|
||||
CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
|
||||
packets. Depends on CONFIG_DEBUG_FEATURES.
|
||||
- CONFIG_STM32_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
|
||||
packets. Depends on CONFIG_DEBUG_FEATURES.
|
||||
|
||||
LTDC hardware acceleration
|
||||
--------------------------
|
||||
@ -236,15 +227,17 @@ LTDC hardware acceleration
|
||||
The LTDC driver provides two 2 LTDC overlays and supports the following hardware
|
||||
acceleration and features:
|
||||
|
||||
Configured at build time
|
||||
Configured at build time:
|
||||
|
||||
- background color
|
||||
|
||||
- default color (outside visible screen)
|
||||
|
||||
Configurable by nuttx framebuffer interface
|
||||
Configurable by nuttx framebuffer interface:
|
||||
|
||||
- cmap support (color table is shared by both LTDC overlays and DMA2D when enabled)
|
||||
|
||||
Configurable via the nuttx framebuffer interface (for each layer separately)
|
||||
Configurable via the nuttx framebuffer interface (for each layer separately):
|
||||
|
||||
- chromakey
|
||||
|
||||
@ -270,11 +263,11 @@ DMA2D hardware acceleration
|
||||
|
||||
The DMA2D driver implements the following hardware acceleration:
|
||||
|
||||
Configurable via the nuttx framebuffer interface
|
||||
Configurable via the nuttx framebuffer interface:
|
||||
|
||||
- cmap support (color table is shared by all DMA2D overlays and LTDC overlays)
|
||||
|
||||
Configurable via the nuttx framebuffer interface (for each layer separately)
|
||||
Configurable via the nuttx framebuffer interface (for each layer separately):
|
||||
|
||||
- color (fill memory region with a specific ARGB8888 color immediately), if
|
||||
cmap is disabled
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
ST Nucleo F722ZE
|
||||
================
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the STMicro
|
||||
This page discusses issues unique to NuttX configurations for the STMicro
|
||||
Nucleo-144 board. See ST document STM32 Nucleo-144 boards (UM1974):
|
||||
|
||||
https://www.st.com/resource/en/user_manual/dm00244518.pdf
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
ST Nucleo F746ZG
|
||||
================
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the STMicro
|
||||
This page discusses issues unique to NuttX configurations for the STMicro
|
||||
Nucleo-144 board. See ST document STM32 Nucleo-144 boards (UM1974):
|
||||
|
||||
https://www.st.com/resource/en/user_manual/dm00244518.pdf
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
ST Nucleo F767ZI
|
||||
================
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the STMicro
|
||||
This page discusses issues unique to NuttX configurations for the STMicro
|
||||
Nucleo-144 board. See ST document STM32 Nucleo-144 boards (UM1974):
|
||||
|
||||
https://www.st.com/resource/en/user_manual/dm00244518.pdf
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
ST STEVAL-ETH001V1
|
||||
==================
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the
|
||||
This page discusses issues unique to NuttX configurations for the
|
||||
STMicro STEVAL-ETH001V1 servo drive evaluation board.
|
||||
The STEVAL-ETH001V1 board is based on the STM32F767ZI MCU (2Mbytes FLASH
|
||||
and 512Kbytes of SRAM).
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
ST STM32F746G-DISCO
|
||||
===================
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the
|
||||
This page discusses issues unique to NuttX configurations for the
|
||||
STMicro STM32F746G-DISCO development board featuring the STM32F746NGH6
|
||||
MCU. The STM32F746NGH6 is a 216MHz Cortex-M7 operation with 1024Kb Flash
|
||||
memory and 300Kb SRAM. The board features:
|
||||
|
||||
@ -2,59 +2,50 @@
|
||||
ST STM32F769I-DISCO
|
||||
===================
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the
|
||||
This page discusses issues unique to NuttX configurations for the
|
||||
STMicro STM32F769I-DISCO development board featuring the STM32F769NIH6
|
||||
MCU. The STM32F769NIH6 is a 216MHz Cortex-M7 operating with 2048K Flash
|
||||
memory and 512Kb SRAM. The board features:
|
||||
|
||||
- On-board ST-LINK/V2 for programming and debugging,
|
||||
- Mbed-enabled (mbed.org)
|
||||
- 4-inch 800x472 color LCD-TFT with capacitive touch screen
|
||||
- SAI audio codec
|
||||
- Audio line in and line out jack
|
||||
- Two ST MEMS microphones
|
||||
- SPDIF RCA input connector
|
||||
- Two pushbuttons (user and reset)
|
||||
- 512-Mbit Quad-SPI Flash memory
|
||||
- 128-Mbit SDRAM
|
||||
- Connector for microSD card
|
||||
- RF-EEPROM daughterboard connector
|
||||
- USB OTG HS with Micro-AB connectors
|
||||
- Ethernet connector compliant with IEEE-802.3-2002 and PoE
|
||||
- On-board ST-LINK/V2 for programming and debugging,
|
||||
- Mbed-enabled (mbed.org)
|
||||
- 4-inch 800x472 color LCD-TFT with capacitive touch screen
|
||||
- SAI audio codec
|
||||
- Audio line in and line out jack
|
||||
- Two ST MEMS microphones
|
||||
- SPDIF RCA input connector
|
||||
- Two pushbuttons (user and reset)
|
||||
- 512-Mbit Quad-SPI Flash memory
|
||||
- 128-Mbit SDRAM
|
||||
- Connector for microSD card
|
||||
- RF-EEPROM daughterboard connector
|
||||
- USB OTG HS with Micro-AB connectors
|
||||
- Ethernet connector compliant with IEEE-802.3-2002 and PoE
|
||||
|
||||
Refer to the http://www.st.com website for further information about this
|
||||
board (search keyword: stm32f769i-disco)
|
||||
|
||||
Contents
|
||||
========
|
||||
|
||||
- STATUS
|
||||
- Development Environment
|
||||
- LEDs and Buttons
|
||||
- Serial Console
|
||||
- Configurations
|
||||
|
||||
STATUS
|
||||
======
|
||||
|
||||
2019-06: PWM support has been tested as working.
|
||||
2019-06: PWM support has been tested as working.
|
||||
|
||||
2017-07: The basic NSH configuration is functional using a serial
|
||||
console on USART1, which is connected to the "virtual com port"
|
||||
of the ST/LINK USB adapter.
|
||||
2017-07: The basic NSH configuration is functional using a serial
|
||||
console on USART1, which is connected to the "virtual com port"
|
||||
of the ST/LINK USB adapter.
|
||||
|
||||
2017-07: STM32 F7 Ethernet appears to be functional, but has had
|
||||
only light testing.
|
||||
2017-07: STM32 F7 Ethernet appears to be functional, but has had
|
||||
only light testing.
|
||||
|
||||
Work in progress: Use LCD over DSI interface, rest of board.
|
||||
Work in progress: Use LCD over DSI interface, rest of board.
|
||||
|
||||
Development Environment
|
||||
=======================
|
||||
|
||||
The Development environments for the STM32F769I-DISCO board are identical
|
||||
to the environments for other STM32F boards. For full details on the
|
||||
environment options and setup, see the README.txt file in the
|
||||
boards/arm/stm32f7/stm32f769i-disco directory.
|
||||
The Development environments for the STM32F769I-DISCO board are identical
|
||||
to the environments for other STM32F boards. For full details on the
|
||||
environment options and setup, see the README.txt file in the
|
||||
boards/arm/stm32f7/stm32f769i-disco directory.
|
||||
|
||||
LEDs and Buttons
|
||||
================
|
||||
|
||||
@ -10,102 +10,54 @@ TODO
|
||||
Peripheral Support
|
||||
==================
|
||||
|
||||
..
|
||||
Individual subsystems can be enabled:
|
||||
The following list indicates peripherals supported in NuttX:
|
||||
|
||||
========================= ==========
|
||||
APB1 Peripheral
|
||||
========================= ==========
|
||||
CONFIG_STM32F7_TIM2 TIM2
|
||||
CONFIG_STM32F7_TIM3 TIM3
|
||||
CONFIG_STM32F7_TIM4 TIM4
|
||||
CONFIG_STM32F7_TIM5 TIM5
|
||||
CONFIG_STM32F7_TIM6 TIM6
|
||||
CONFIG_STM32F7_TIM7 TIM7
|
||||
CONFIG_STM32F7_TIM12 TIM12
|
||||
CONFIG_STM32F7_TIM13 TIM13
|
||||
CONFIG_STM32F7_TIM14 TIM14
|
||||
CONFIG_STM32F7_LPTIM1 LPTIM1
|
||||
CONFIG_STM32F7_RTC RTC
|
||||
CONFIG_STM32F7_BKP BKP Registers
|
||||
CONFIG_STM32F7_WWDG WWDG
|
||||
CONFIG_STM32F7_IWDG IWDG
|
||||
CONFIG_STM32F7_SPI2 SPI2
|
||||
CONFIG_STM32F7_I2S2 I2S2
|
||||
CONFIG_STM32F7_SPI3 SPI3
|
||||
CONFIG_STM32F7_I2S3 I2S3
|
||||
CONFIG_STM32F7_SPDIFRX SPDIFRX
|
||||
CONFIG_STM32F7_USART2 USART2
|
||||
CONFIG_STM32F7_USART3 USART3
|
||||
CONFIG_STM32F7_UART4 UART4
|
||||
CONFIG_STM32F7_UART5 UART5
|
||||
CONFIG_STM32F7_I2C1 I2C1
|
||||
CONFIG_STM32F7_I2C2 I2C2
|
||||
CONFIG_STM32F7_I2C3 I2C3
|
||||
CONFIG_STM32F7_I2C4 I2C4
|
||||
CONFIG_STM32F7_CAN1 CAN1
|
||||
CONFIG_STM32F7_CAN2 CAN2
|
||||
CONFIG_STM32F7_HDMICEC HDMI-CEC
|
||||
CONFIG_STM32F7_PWR PWR
|
||||
CONFIG_STM32F7_DAC DAC
|
||||
CONFIG_STM32F7_UART7 UART7
|
||||
CONFIG_STM32F7_UART8 UART8
|
||||
========================= ==========
|
||||
|
||||
========================= ==========
|
||||
APB2 Peripheral
|
||||
========================= ==========
|
||||
CONFIG_STM32F7_TIM1 TIM1
|
||||
CONFIG_STM32F7_TIM8 TIM8
|
||||
CONFIG_STM32F7_USART1 USART1
|
||||
CONFIG_STM32F7_USART6 USART6
|
||||
CONFIG_STM32F7_ADC ADC1 - ADC2 - ADC3
|
||||
CONFIG_STM32F7_SDMMC1 SDMMC1
|
||||
CONFIG_STM32F7_SPI1 SPI1
|
||||
CONFIG_STM32F7_SPI4 SPI4
|
||||
CONFIG_STM32F7_SYSCFG SYSCFG
|
||||
CONFIG_STM32F7_EXTI EXTI
|
||||
CONFIG_STM32F7_TIM9 TIM9
|
||||
CONFIG_STM32F7_TIM10 TIM10
|
||||
CONFIG_STM32F7_TIM11 TIM11
|
||||
CONFIG_STM32F7_SPI5 SPI5
|
||||
CONFIG_STM32F7_SPI6 SPI6
|
||||
CONFIG_STM32F7_SAI1 SAI1
|
||||
CONFIG_STM32F7_SAI2 SAI2
|
||||
CONFIG_STM32F7_LTDC LCD-TFT
|
||||
========================= ==========
|
||||
|
||||
========================= ==========
|
||||
AHB1 Peripheral
|
||||
========================= ==========
|
||||
CONFIG_STM32F7_CRC CRC
|
||||
CONFIG_STM32F7_BKPSRAM BKPSRAM
|
||||
CONFIG_STM32F7_DMA1 DMA1
|
||||
CONFIG_STM32F7_DMA2 DMA2
|
||||
CONFIG_STM32F7_ETHMAC Ethernet MAC
|
||||
CONFIG_STM32F7_DMA2D Chrom-ART (DMA2D)
|
||||
CONFIG_STM32F7_OTGHS USB OTG HS
|
||||
========================= ==========
|
||||
|
||||
========================= ==========
|
||||
AHB2 Peripheral
|
||||
========================= ==========
|
||||
CONFIG_STM32F7_OTGFS USB OTG FS
|
||||
CONFIG_STM32F7_DCMI DCMI
|
||||
CONFIG_STM32F7_CRYP CRYP
|
||||
CONFIG_STM32F7_HASH HASH
|
||||
CONFIG_STM32F7_RNG RNG
|
||||
========================= ==========
|
||||
|
||||
========================= ==========
|
||||
AHB3 Peripheral
|
||||
========================= ==========
|
||||
CONFIG_STM32F7_FMC FMC control registers
|
||||
CONFIG_STM32F7_QUADSPI QuadSPI Control
|
||||
========================= ==========
|
||||
========== ======= =====
|
||||
Peripheral Support Notes
|
||||
========== ======= =====
|
||||
FLASH Yes
|
||||
PM ?
|
||||
RCC Yes
|
||||
GPIO Yes
|
||||
SYSCFG Yes
|
||||
DMA Yes
|
||||
DMA2D Yes
|
||||
EXTI Yes
|
||||
CRC Yes
|
||||
FMC Yes
|
||||
QUADSPI Yes
|
||||
ADC Yes
|
||||
DAC Yes
|
||||
DFSDM No
|
||||
DCMI No
|
||||
LTDC Yes
|
||||
DSI No
|
||||
JPEG No
|
||||
RNG Yes
|
||||
CRYP No
|
||||
HASH ?
|
||||
TIM Yes
|
||||
LPTIM No
|
||||
IWDG Yes
|
||||
WWDG Yes
|
||||
RTC Yes
|
||||
I2C Yes
|
||||
USART Yes
|
||||
SPI Yes
|
||||
I2S ?
|
||||
SAI No
|
||||
SPIDIFRX No
|
||||
MDIOS ?
|
||||
SDMMC Yes
|
||||
CAN Yes
|
||||
OTG_FS Yes
|
||||
OTG_HS Yes
|
||||
ETH Yes
|
||||
HDMI_CEC No
|
||||
========== ======= =====
|
||||
|
||||
Porting STM32 F4 Drivers
|
||||
========================
|
||||
------------------------
|
||||
|
||||
The STM32F746 is very similar to the STM32 F429 and many of the drivers
|
||||
in the stm32/ directory could be ported here: ADC, BBSRAM, CAN, DAC,
|
||||
@ -139,14 +91,9 @@ https://cwiki.apache.org/confluence/display/NUTTX/Porting+Drivers+to+the+STM32+F
|
||||
Memory
|
||||
------
|
||||
|
||||
CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case)::
|
||||
- CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case)
|
||||
|
||||
CONFIG_RAM_SIZE=0x00010000 (64Kb)
|
||||
|
||||
CONFIG_RAM_START - The start address of installed SRAM (SRAM1)::
|
||||
|
||||
CONFIG_RAM_START=0x20010000
|
||||
CONFIG_RAM_SIZE=245760
|
||||
- CONFIG_RAM_START - The start address of installed SRAM (SRAM1)
|
||||
|
||||
This configurations use only SRAM1 for data storage. The heap includes
|
||||
the remainder of SRAM1. If CONFIG_MM_REGIONS=2, then SRAM2 will be
|
||||
@ -159,32 +106,32 @@ managed with dtcm_malloc(), dtcm_free(), etc.
|
||||
In order to use FMC SRAM, the following additional things need to be
|
||||
present in the NuttX configuration file:
|
||||
|
||||
CONFIG_STM32F7_FMC_SRAM - Indicates that SRAM is available via the
|
||||
FMC (as opposed to an LCD or FLASH).
|
||||
- CONFIG_STM32F7_FMC_SRAM - Indicates that SRAM is available via the
|
||||
FMC (as opposed to an LCD or FLASH).
|
||||
|
||||
CONFIG_HEAP2_BASE - The base address of the SRAM in the FMC address space (hex)
|
||||
- CONFIG_HEAP2_BASE - The base address of the SRAM in the FMC address space (hex)
|
||||
|
||||
CONFIG_HEAP2_SIZE - The size of the SRAM in the FMC address space (decimal)
|
||||
- CONFIG_HEAP2_SIZE - The size of the SRAM in the FMC address space (decimal)
|
||||
|
||||
CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
|
||||
stack. If defined, this symbol is the size of the interrupt
|
||||
stack in bytes. If not defined, the user task stacks will be
|
||||
used during interrupt handling.
|
||||
- CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
|
||||
stack. If defined, this symbol is the size of the interrupt
|
||||
stack in bytes. If not defined, the user task stacks will be
|
||||
used during interrupt handling.
|
||||
|
||||
CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
|
||||
- CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
|
||||
|
||||
Clock
|
||||
-----
|
||||
|
||||
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
|
||||
configuration features.::
|
||||
- CONFIG_ARCH_BOARD_STM32F7_CUSTOM_CLOCKCONFIG - Enables special STM32F7 clock
|
||||
configuration features.::
|
||||
|
||||
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
|
||||
CONFIG_ARCH_BOARD_STM32F7_CUSTOM_CLOCKCONFIG=n
|
||||
|
||||
CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation of delay loops
|
||||
- CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation of delay loops
|
||||
|
||||
TIMER
|
||||
-----
|
||||
Timers
|
||||
------
|
||||
|
||||
Timer devices may be used for different purposes. One special purpose is
|
||||
to generate modulated outputs for such things as motor control. If CONFIG_STM32F7_TIMn
|
||||
@ -192,18 +139,18 @@ is defined (as above) then the following may also be defined to indicate that
|
||||
the timer is intended to be used for pulsed output modulation, ADC conversion,
|
||||
or DAC conversion. Note that ADC/DAC require two definition: Not only do you have
|
||||
to assign the timer (n) for used by the ADC or DAC, but then you also have to
|
||||
configure which ADC or DAC (m) it is assigned to.::
|
||||
configure which ADC or DAC (m) it is assigned to.:
|
||||
|
||||
CONFIG_STM32F7_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
|
||||
CONFIG_STM32F7_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
|
||||
CONFIG_STM32F7_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
|
||||
CONFIG_STM32F7_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
|
||||
CONFIG_STM32F7_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
|
||||
- CONFIG_STM32F7_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
|
||||
- CONFIG_STM32F7_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
|
||||
- CONFIG_STM32F7_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
|
||||
- CONFIG_STM32F7_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
|
||||
- CONFIG_STM32F7_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
|
||||
|
||||
For each timer that is enabled for PWM usage, we need the following additional
|
||||
configuration settings::
|
||||
configuration settings:
|
||||
|
||||
CONFIG_STM32F7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
|
||||
- CONFIG_STM32F7_TIMx_CHANNEL - Specifies the timer output channel {1,..,4}
|
||||
|
||||
NOTE: The STM32 timers are each capable of generating different signals on
|
||||
each of the four channels with different duty cycles. That capability is
|
||||
@ -215,96 +162,152 @@ JTAG
|
||||
USART
|
||||
-----
|
||||
|
||||
CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
|
||||
m (m=4,5) for the console and ttys0 (default is the USART1).
|
||||
Options:
|
||||
|
||||
CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
This specific the size of the receive buffer
|
||||
- CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UARTm (m=4,5)
|
||||
for the console and ttys0 (default is the USART1).
|
||||
|
||||
CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
|
||||
being sent. This specific the size of the transmit buffer
|
||||
- CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
This specific the size of the receive buffer
|
||||
|
||||
CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
|
||||
- CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
|
||||
being sent. This specific the size of the transmit buffer
|
||||
|
||||
CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
|
||||
- CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
|
||||
|
||||
CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
- CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
|
||||
|
||||
CONFIG_U[S]ARTn_2STOP - Two stop bits
|
||||
- CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
|
||||
- CONFIG_U[S]ARTn_2STOP - Two stop bits
|
||||
|
||||
CAN
|
||||
---
|
||||
|
||||
CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32F7_CAN1 or
|
||||
CONFIG_STM32F7_CAN2 must also be defined)
|
||||
- CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32F7F7_CAN1 or
|
||||
CONFIG_STM32F7F7_CAN2 must also be defined)
|
||||
|
||||
CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default Standard 11-bit IDs.
|
||||
- CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default Standard 11-bit IDs.
|
||||
|
||||
CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages. Default: 8
|
||||
- CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages. Default: 8
|
||||
|
||||
CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests. Default: 4
|
||||
- CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests. Default: 4
|
||||
|
||||
CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
|
||||
mode for testing. The STM32 CAN driver does support loopback mode.
|
||||
- CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
|
||||
mode for testing. The STM32F7 CAN driver does support loopback mode.
|
||||
|
||||
CONFIG_STM32F7_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7_CAN1 is defined.
|
||||
- CONFIG_STM32F7F7_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7F7_CAN1 is defined.
|
||||
|
||||
CONFIG_STM32F7_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7_CAN2 is defined.
|
||||
- CONFIG_STM32F7F7_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32F7F7_CAN2 is defined.
|
||||
|
||||
CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6
|
||||
- CONFIG_STM32F7_CAN_TSEG1 - The number of CAN time quanta in segment 1. Default: 6
|
||||
|
||||
CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7
|
||||
- CONFIG_STM32F7_CAN_TSEG2 - the number of CAN time quanta in segment 2. Default: 7
|
||||
|
||||
CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
|
||||
dump of all CAN registers.
|
||||
- CONFIG_STM32F7_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
|
||||
dump of all CAN registers.
|
||||
|
||||
CAN SocketCAN
|
||||
-------------
|
||||
|
||||
TODO
|
||||
|
||||
SPI
|
||||
---
|
||||
|
||||
CONFIG_STM32F7_SPI_INTERRUPTS - Select to enable interrupt driven SPI
|
||||
support. Non-interrupt-driven, poll-waiting is recommended if the
|
||||
interrupt rate would be to high in the interrupt driven case.
|
||||
- CONFIG_STM32F7_SPI_INTERRUPTS - Select to enable interrupt driven SPI
|
||||
support. Non-interrupt-driven, poll-waiting is recommended if the
|
||||
interrupt rate would be to high in the interrupt driven case.
|
||||
|
||||
CONFIG_STM32F7_SPIx_DMA - Use DMA to improve SPIx transfer performance.
|
||||
Cannot be used with CONFIG_STM32F7_SPI_INTERRUPT.
|
||||
- CONFIG_STM32F7_SPIx_DMA - Use DMA to improve SPIx transfer performance.
|
||||
Cannot be used with CONFIG_STM32F7_SPI_INTERRUPT.
|
||||
|
||||
DMA
|
||||
SDIO
|
||||
----
|
||||
|
||||
TODO
|
||||
|
||||
ETH
|
||||
---
|
||||
|
||||
CONFIG_SDIO_DMA - Support DMA data transfers. Requires CONFIG_STM32F7_SDIO and CONFIG_STM32F7_DMA2.
|
||||
Options:
|
||||
|
||||
CONFIG_STM32_SDIO_DMAPRIO - Select SDIO DMA interrupt priority. Default: Medium
|
||||
- CONFIG_STM32F7_PHYADDR - The 5-bit address of the PHY on the board
|
||||
|
||||
CONFIG_STM32_SDIO_WIDTH_D1_ONLY - Select 1-bit transfer mode. Default: 4-bit transfer mode.
|
||||
- CONFIG_STM32F7_MII - Support Ethernet MII interface
|
||||
|
||||
USB
|
||||
---
|
||||
- CONFIG_STM32F7_MII_MCO1 - Use MCO1 to clock the MII interface
|
||||
|
||||
- CONFIG_STM32F7_MII_MCO2 - Use MCO2 to clock the MII interface
|
||||
|
||||
- CONFIG_STM32F7_RMII - Support Ethernet RMII interface
|
||||
|
||||
- CONFIG_STM32F7_AUTONEG - Use PHY autonegotiation to determine speed and mode
|
||||
|
||||
- CONFIG_STM32F7_ETHFD - If CONFIG_STM32F7_AUTONEG is not defined, then this
|
||||
may be defined to select full duplex mode. Default: half-duplex
|
||||
|
||||
- CONFIG_STM32F7_ETH100MBPS - If CONFIG_STM32F7_AUTONEG is not defined, then this
|
||||
may be defined to select 100 MBps speed. Default: 10 Mbps
|
||||
|
||||
- CONFIG_STM32F7_PHYSR - This must be provided if CONFIG_STM32F7_AUTONEG is
|
||||
defined. The PHY status register address may diff from PHY to PHY. This
|
||||
configuration sets the address of the PHY status register.
|
||||
|
||||
- CONFIG_STM32F7_PHYSR_SPEED - This must be provided if CONFIG_STM32F7_AUTONEG is
|
||||
defined. This provides bit mask indicating 10 or 100MBps speed.
|
||||
|
||||
- CONFIG_STM32F7_PHYSR_100MBPS - This must be provided if CONFIG_STM32F7_AUTONEG is
|
||||
defined. This provides the value of the speed bit(s) indicating 100MBps speed.
|
||||
|
||||
- CONFIG_STM32F7_PHYSR_MODE - This must be provided if CONFIG_STM32F7_AUTONEG is
|
||||
defined. This provide bit mask indicating full or half duplex modes.
|
||||
|
||||
- CONFIG_STM32F7_PHYSR_FULLDUPLEX - This must be provided if CONFIG_STM32F7_AUTONEG is
|
||||
defined. This provides the value of the mode bits indicating full duplex mode.
|
||||
|
||||
- CONFIG_STM32F7_ETH_PTP - Precision Time Protocol (PTP). Not supported
|
||||
but some hooks are indicated with this condition.
|
||||
|
||||
USB OTG FS
|
||||
----------
|
||||
|
||||
STM32 USB OTG FS Host Driver Support
|
||||
|
||||
Pre-requisites::
|
||||
Pre-requisites:
|
||||
|
||||
CONFIG_USBDEV - Enable USB device support
|
||||
CONFIG_USBHOST - Enable USB host support
|
||||
CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block
|
||||
CONFIG_STM32F7_SYSCFG - Needed
|
||||
CONFIG_SCHED_WORKQUEUE - Worker thread support is required
|
||||
- CONFIG_USBDEV - Enable USB device support
|
||||
- CONFIG_USBHOST - Enable USB host support
|
||||
- CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block
|
||||
- CONFIG_STM32F7_SYSCFG - Needed
|
||||
- CONFIG_SCHED_WORKQUEUE - Worker thread support is required
|
||||
|
||||
Options::
|
||||
Options:
|
||||
|
||||
CONFIG_STM32F7_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
|
||||
Default 128 (512 bytes)
|
||||
CONFIG_STM32F7_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
|
||||
in 32-bit words. Default 96 (384 bytes)
|
||||
CONFIG_STM32F7_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
|
||||
words. Default 96 (384 bytes)
|
||||
CONFIG_STM32F7_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128
|
||||
CONFIG_STM32F7_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
|
||||
want to do that?
|
||||
CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access
|
||||
debug. Depends on CONFIG_DEBUG_FEATURES.
|
||||
CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
|
||||
packets. Depends on CONFIG_DEBUG_FEATURES.
|
||||
- CONFIG_STM32F7_OTGFS_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words.
|
||||
Default 128 (512 bytes)
|
||||
|
||||
- CONFIG_STM32F7_OTGFS_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO
|
||||
in 32-bit words. Default 96 (384 bytes)
|
||||
|
||||
- CONFIG_STM32F7_OTGFS_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit
|
||||
words. Default 96 (384 bytes)
|
||||
|
||||
- CONFIG_STM32F7_OTGFS_DESCSIZE - Maximum size of a descriptor. Default: 128
|
||||
|
||||
- CONFIG_STM32F7_OTGFS_SOFINTR - Enable SOF interrupts. Why would you ever
|
||||
want to do that?
|
||||
|
||||
- CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access
|
||||
debug. Depends on CONFIG_DEBUG_FEATURES.
|
||||
|
||||
- CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB
|
||||
packets. Depends on CONFIG_DEBUG_FEATURES.
|
||||
|
||||
USB OTG HS
|
||||
----------
|
||||
|
||||
TODO
|
||||
|
||||
FPU
|
||||
===
|
||||
@ -340,6 +343,8 @@ There are two version of the FPU support built into the STM32 port.
|
||||
SPI Test
|
||||
========
|
||||
|
||||
Available for some Nucleo boards.
|
||||
|
||||
The builtin SPI test facility can be enabled with the following settings::
|
||||
|
||||
+CONFIG_STM32F7_SPI=y
|
||||
|
||||
@ -2,4 +2,4 @@
|
||||
ST Nucleo G070RB
|
||||
================
|
||||
|
||||
The Nucleo-G070RB is a member of the Nucleo-64 board family.
|
||||
The Nucleo G070RB is a member of the Nucleo-64 board family.
|
||||
|
||||
@ -2,4 +2,4 @@
|
||||
ST Nucleo G071RB
|
||||
================
|
||||
|
||||
The Nucleo-G071RB is a member of the Nucleo-64 board family.
|
||||
The Nucleo G071RB is a member of the Nucleo-64 board family.
|
||||
|
||||
@ -15,7 +15,42 @@ STM32G0x1 Yes Access line
|
||||
Peripheral Support
|
||||
==================
|
||||
|
||||
TODO
|
||||
The following list indicates peripherals supported in NuttX:
|
||||
|
||||
========== ======= =====
|
||||
Peripheral Support Notes
|
||||
========== ======= =====
|
||||
FLASH No
|
||||
PM No
|
||||
RCC Yes
|
||||
CSR No
|
||||
GPIO Yes
|
||||
SYSCFG Yes
|
||||
DMA Yes
|
||||
DMAMUX Yes
|
||||
EXTI Yes
|
||||
CRC Yes
|
||||
ADC Yes
|
||||
DAC No
|
||||
VREFBUF ?
|
||||
COMP No
|
||||
RNG Yes
|
||||
AES Yes
|
||||
TIM Yes
|
||||
LPTIM No
|
||||
IRTIM No
|
||||
IWDG No
|
||||
WWDG No
|
||||
RTC No
|
||||
TAMP No
|
||||
I2C Yes
|
||||
USART Yes
|
||||
LPUSART No
|
||||
SPI Yes
|
||||
UCPD No
|
||||
USB ?
|
||||
HDIM_CEC No
|
||||
========== ======= =====
|
||||
|
||||
Supported Boards
|
||||
================
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
ST B-G474E-DPOW1
|
||||
================
|
||||
|
||||
This is the README file for a port of NuttX to the ST Micro B-G474E-DPOW1
|
||||
This page is for a port of NuttX to the ST Micro B-G474E-DPOW1
|
||||
Discovery kit with STM32G474RE MCU. For more information about this board,
|
||||
see:
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
================
|
||||
ST Nucleo-G431KB
|
||||
ST Nucleo G431KB
|
||||
================
|
||||
|
||||
The Nucleo-G431KB is a member of the Nucleo-32 board family.
|
||||
The Nucleo G431KB is a member of the Nucleo-32 board family.
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
ST Nucleo G431RB
|
||||
================
|
||||
|
||||
The Nucleo-G431RB is a member of the Nucleo-64 board family.
|
||||
The Nucleo G431RB is a member of the Nucleo-64 board family.
|
||||
|
||||
Configurations
|
||||
==============
|
||||
|
||||
@ -10,7 +10,50 @@ TODO
|
||||
Peripheral Support
|
||||
==================
|
||||
|
||||
TODO
|
||||
The following list indicates peripherals supported in NuttX:
|
||||
|
||||
========== ======= =====
|
||||
Peripheral Support Notes
|
||||
========== ======= =====
|
||||
FLASH Yes
|
||||
PM ?
|
||||
RCC Yes
|
||||
CRS No
|
||||
GPIO Yes
|
||||
SYSCFG Yes
|
||||
DMA Yes
|
||||
DMAMUX Yes
|
||||
EXTI Yes
|
||||
CRC ?
|
||||
CORDIC Yes
|
||||
FMAC No
|
||||
FSMC ?
|
||||
QUADSPI ?
|
||||
ADC Yes
|
||||
DAC Yes
|
||||
VREFBUS ?
|
||||
COMP ?
|
||||
OPAMP Yes
|
||||
RNG ?
|
||||
HRTIM Yes
|
||||
TIM Yes
|
||||
LPTIM No
|
||||
IRTIM No
|
||||
AES ?
|
||||
RTC Yes
|
||||
TAMP No
|
||||
USART Yes
|
||||
LPUART No
|
||||
SPI Yes
|
||||
I2S ?
|
||||
SAI No
|
||||
I2C Yes
|
||||
IWDG ?
|
||||
WWDG ?
|
||||
FDCAN Yes
|
||||
USB Yes
|
||||
UCPD No
|
||||
========== ======= =====
|
||||
|
||||
Supported Boards
|
||||
================
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
ST Nucle H743ZI
|
||||
===============
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the
|
||||
This page discusses issues unique to NuttX configurations for the
|
||||
STMicro NUCLEO-H743ZI development board featuring the STM32H743ZI
|
||||
MCU. The STM32H743ZI is a 400MHz Cortex-M7 operation with 2MBytes Flash
|
||||
memory and 1MByte SRAM. The board features:
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
ST Nucle H743ZI2
|
||||
================
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the
|
||||
This page discusses issues unique to NuttX configurations for the
|
||||
STMicro NUCLEO-H743ZI2 development board featuring the STM32H743ZI
|
||||
MCU. The STM32H743ZI is a 400MHz Cortex-M7 operation with 2MBytes Flash
|
||||
memory and 1MByte SRAM. The board features:
|
||||
|
||||
@ -1,3 +1,3 @@
|
||||
================
|
||||
ST Nucleo H745zi
|
||||
ST Nucleo H745ZI
|
||||
================
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
ST STM32H747I-DISCO
|
||||
===================
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the
|
||||
This page discusses issues unique to NuttX configurations for the
|
||||
STMicro STM32H747I-DISCO development board featuring the STM32H747I
|
||||
MCU. The STM32H747I is a Cortex-M7 and -M4 dual core with 2MBytes Flash
|
||||
memory and 1MByte SRAM. The board features:
|
||||
|
||||
@ -10,7 +10,63 @@ TODO
|
||||
Peripheral Support
|
||||
==================
|
||||
|
||||
TODO
|
||||
|
||||
The following list indicates peripherals supported in NuttX:
|
||||
|
||||
========== ======= =====
|
||||
Peripheral Support Notes
|
||||
========== ======= =====
|
||||
RAMECC No
|
||||
FLASH Yes
|
||||
SMM No
|
||||
PM ?
|
||||
RCC Yes
|
||||
CRS No
|
||||
HSEM Yes
|
||||
GPIO Yes
|
||||
SYSCFG Yes
|
||||
MDMA ?
|
||||
DMA Yes
|
||||
BDMA Yes
|
||||
DMA2D Yes
|
||||
EXTI Yes
|
||||
CRC Yes
|
||||
FMC Yes
|
||||
QUADSPI Yes
|
||||
DLYB No
|
||||
ADC Yes
|
||||
DAC Yes
|
||||
VREFBUF No
|
||||
COMP No
|
||||
OPAMP No
|
||||
DFSDM No
|
||||
DCMI No
|
||||
LTDC Yes
|
||||
JPEG No
|
||||
RNG Yes
|
||||
CRYP No
|
||||
HASH ?
|
||||
HRTIM No
|
||||
TIM Yes
|
||||
LPTIM No
|
||||
IWDG Yes
|
||||
WWDG Yes
|
||||
RTC Yes
|
||||
I2C Yes
|
||||
USART Yes
|
||||
SPI Yes
|
||||
I2S ?
|
||||
SAI No
|
||||
SPIDIFRX No
|
||||
SWPMI No
|
||||
MDIOS ?
|
||||
SDMMC Yes
|
||||
FDCAN Yes
|
||||
OTG_FS Yes
|
||||
OTG_HS Yes
|
||||
ETH Yes
|
||||
HDMI_CEC No
|
||||
========== ======= =====
|
||||
|
||||
Supported Boards
|
||||
================
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
ST STM32L0538-DISO
|
||||
==================
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the
|
||||
This page discusses issues unique to NuttX configurations for the
|
||||
STMicro STM32L0538-DISO development board. The STM32L0538-DISO board
|
||||
is based on the STM32L053C8 MCU (64Kbytes FLASH, 8Kbytes of SRAM and
|
||||
6Kbytes of EEPROM).
|
||||
|
||||
@ -10,7 +10,40 @@ STM32L071, STM32L072 and STM32L073
|
||||
Peripheral Support
|
||||
==================
|
||||
|
||||
TODO
|
||||
The following list indicates peripherals supported in NuttX:
|
||||
|
||||
========== ======= =====
|
||||
Peripheral Support Notes
|
||||
========== ======= =====
|
||||
FLASH No
|
||||
CRC No
|
||||
FIREWALL No
|
||||
PM No
|
||||
RCC Yes
|
||||
CSR No
|
||||
GPIO Yes
|
||||
SYSCFG Yes
|
||||
DMA Yes
|
||||
EXTI Yes
|
||||
ADC Yes
|
||||
DAC No
|
||||
COMP No
|
||||
LCD No
|
||||
TSC No
|
||||
AES Yes
|
||||
RNG Yes
|
||||
TIM Yes
|
||||
LPTIM No
|
||||
IWDG No
|
||||
WWDG No
|
||||
RTC No
|
||||
I2C Yes
|
||||
USART Yes
|
||||
LPUSART No
|
||||
SPI Yes
|
||||
I2S No
|
||||
USB Yes
|
||||
========== ======= =====
|
||||
|
||||
Supported Boards
|
||||
================
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
================
|
||||
ST Nucleo-L152RE
|
||||
ST Nucleo L152RE
|
||||
================
|
||||
|
||||
The Nucleo-L152RE is a member of the Nucleo-64 board family.
|
||||
The Nucleo L152RE is a member of the Nucleo-64 board family.
|
||||
|
||||
@ -10,36 +10,65 @@ TODO
|
||||
Peripheral Support
|
||||
==================
|
||||
|
||||
TODO
|
||||
The following list indicates peripherals supported in NuttX:
|
||||
|
||||
========== ======= =====
|
||||
Peripheral Support Notes
|
||||
========== ======= =====
|
||||
FLASH Yes
|
||||
PM ?
|
||||
RCC Yes
|
||||
GPIO Yes
|
||||
SYSCFG ?
|
||||
EXTI Yes
|
||||
DMA Yes
|
||||
ADC Yes
|
||||
DAC Yes
|
||||
COMP ?
|
||||
OPAMP ?
|
||||
LCD ?
|
||||
TIM Yes
|
||||
RTC Yes
|
||||
IWDG Yes
|
||||
WWDG Yes
|
||||
AES ?
|
||||
USB ?
|
||||
FSMC ?
|
||||
I2C Yes
|
||||
USART Yes
|
||||
SPI Yes
|
||||
SDIO Yes
|
||||
========== ======= =====
|
||||
|
||||
Memory
|
||||
------
|
||||
|
||||
CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case):
|
||||
- CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case)
|
||||
|
||||
CONFIG_RAM_SIZE=16384 (16Kb)
|
||||
- CONFIG_RAM_START - The start address of installed DRAM
|
||||
|
||||
- CONFIG_STM32_CCMEXCLUDE - Exclude CCM SRAM from the HEAP
|
||||
|
||||
CONFIG_RAM_START - The start address of installed DRAM
|
||||
- CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
|
||||
stack. If defined, this symbol is the size of the interrupt
|
||||
stack in bytes. If not defined, the user task stacks will be
|
||||
used during interrupt handling.
|
||||
|
||||
CONFIG_RAM_START=0x20000000
|
||||
|
||||
CONFIG_STM32_CCMEXCLUDE - Exclude CCM SRAM from the HEAP
|
||||
|
||||
CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
|
||||
stack. If defined, this symbol is the size of the interrupt
|
||||
stack in bytes. If not defined, the user task stacks will be
|
||||
used during interrupt handling.
|
||||
- CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
|
||||
|
||||
Clock
|
||||
-----
|
||||
|
||||
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
|
||||
configuration features.::
|
||||
- CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG - Enables special STM32 clock
|
||||
configuration features.::
|
||||
|
||||
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
|
||||
CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG=n
|
||||
|
||||
TIMER
|
||||
-----
|
||||
- CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
|
||||
of delay loops
|
||||
|
||||
Timers
|
||||
------
|
||||
|
||||
Timer devices may be used for different purposes. One special purpose is
|
||||
to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
|
||||
@ -49,11 +78,11 @@ or DAC conversion. Note that ADC/DAC require two definition: Not only do you ha
|
||||
to assign the timer (n) for used by the ADC or DAC, but then you also have to
|
||||
configure which ADC or DAC (m) it is assigned to.
|
||||
|
||||
CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
|
||||
CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
|
||||
CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
|
||||
CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
|
||||
CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
|
||||
- CONFIG_STM32_TIMn_PWM Reserve timer n for use by PWM, n=1,..,14
|
||||
- CONFIG_STM32_TIMn_ADC Reserve timer n for use by ADC, n=1,..,14
|
||||
- CONFIG_STM32_TIMn_ADCm Reserve timer n to trigger ADCm, n=1,..,14, m=1,..,3
|
||||
- CONFIG_STM32_TIMn_DAC Reserve timer n for use by DAC, n=1,..,14
|
||||
- CONFIG_STM32_TIMn_DACm Reserve timer n to trigger DACm, n=1,..,14, m=1,..,2
|
||||
|
||||
For each timer that is enabled for PWM usage, we need the following additional
|
||||
configuration settings:
|
||||
@ -67,76 +96,51 @@ not supported by this driver: Only one output channel per timer.
|
||||
JTAG
|
||||
----
|
||||
|
||||
CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
JTAG Enable settings (by default JTAG-DP and SW-DP are disabled):
|
||||
|
||||
CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
but without JNTRST.
|
||||
- CONFIG_STM32_JTAG_FULL_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
|
||||
CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
|
||||
- CONFIG_STM32_JTAG_NOJNTRST_ENABLE - Enables full SWJ (JTAG-DP + SW-DP)
|
||||
but without JNTRST.
|
||||
|
||||
- CONFIG_STM32_JTAG_SW_ENABLE - Set JTAG-DP disabled and SW-DP enabled
|
||||
|
||||
USART
|
||||
-----
|
||||
|
||||
CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART
|
||||
m (m=4,5) for the console and ttys0 (default is the USART1).
|
||||
Options:
|
||||
|
||||
CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
This specific the size of the receive buffer
|
||||
- CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UARTm (m=4,5)
|
||||
for the console and ttys0 (default is the USART1).
|
||||
|
||||
CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
|
||||
being sent. This specific the size of the transmit buffer
|
||||
- CONFIG_U[S]ARTn_RXBUFSIZE - Characters are buffered as received.
|
||||
This specific the size of the receive buffer
|
||||
|
||||
CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
|
||||
- CONFIG_U[S]ARTn_TXBUFSIZE - Characters are buffered before
|
||||
being sent. This specific the size of the transmit buffer
|
||||
|
||||
CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
|
||||
- CONFIG_U[S]ARTn_BAUD - The configure BAUD of the UART. Must be
|
||||
|
||||
CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
- CONFIG_U[S]ARTn_BITS - The number of bits. Must be either 7 or 8.
|
||||
|
||||
CONFIG_U[S]ARTn_2STOP - Two stop bits
|
||||
- CONFIG_U[S]ARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
|
||||
|
||||
CAN
|
||||
---
|
||||
|
||||
CONFIG_CAN - Enables CAN support (one or both of CONFIG_STM32_CAN1 or
|
||||
CONFIG_STM32_CAN2 must also be defined)
|
||||
|
||||
CONFIG_CAN_EXTID - Enables support for the 29-bit extended ID. Default
|
||||
Standard 11-bit IDs.
|
||||
|
||||
CONFIG_CAN_FIFOSIZE - The size of the circular buffer of CAN messages.
|
||||
Default: 8
|
||||
|
||||
CONFIG_CAN_NPENDINGRTR - The size of the list of pending RTR requests.
|
||||
Default: 4
|
||||
|
||||
CONFIG_CAN_LOOPBACK - A CAN driver may or may not support a loopback
|
||||
mode for testing. The STM32 CAN driver does support loopback mode.
|
||||
|
||||
CONFIG_STM32_CAN1_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN1
|
||||
is defined.
|
||||
|
||||
CONFIG_STM32_CAN2_BAUD - CAN1 BAUD rate. Required if CONFIG_STM32_CAN2
|
||||
is defined.
|
||||
|
||||
CONFIG_STM32_CAN_TSEG1 - The number of CAN time quanta in segment 1.
|
||||
Default: 6
|
||||
|
||||
CONFIG_STM32_CAN_TSEG2 - the number of CAN time quanta in segment 2.
|
||||
Default: 7
|
||||
|
||||
CONFIG_STM32_CAN_REGDEBUG - If CONFIG_DEBUG_FEATURES is set, this will generate an
|
||||
dump of all CAN registers.
|
||||
- CONFIG_U[S]ARTn_2STOP - Two stop bits
|
||||
|
||||
SPI
|
||||
---
|
||||
|
||||
CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
|
||||
support. Non-interrupt-driven, poll-waiting is recommended if the
|
||||
interrupt rate would be to high in the interrupt driven case.
|
||||
- CONFIG_STM32_SPI_INTERRUPTS - Select to enable interrupt driven SPI
|
||||
support. Non-interrupt-driven, poll-waiting is recommended if the
|
||||
interrupt rate would be to high in the interrupt driven case.
|
||||
|
||||
CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
|
||||
Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
|
||||
- CONFIG_STM32_SPIx_DMA - Use DMA to improve SPIx transfer performance.
|
||||
Cannot be used with CONFIG_STM32_SPI_INTERRUPT.
|
||||
|
||||
USB
|
||||
---
|
||||
|
||||
TODO
|
||||
|
||||
SLCD
|
||||
----
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
ST STEVAL-STLCS01V1
|
||||
===================
|
||||
|
||||
This README discusses issues unique to NuttX configurations for the ST
|
||||
This page discusses issues unique to NuttX configurations for the ST
|
||||
STEVAL-STLCS01V1 board (SensorTile module) from ST Micro based on
|
||||
STM32L476JG MCU. The board features:
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
=============
|
||||
STM32L562E-DK
|
||||
=============
|
||||
================
|
||||
ST STM32L562E-DK
|
||||
================
|
||||
|
||||
This page discusses the port of NuttX to the STMicro STM32L562E-DK
|
||||
board. That board features the STM32L562QEI6QU MCU with 512KiB of FLASH
|
||||
|
||||
@ -1,13 +1,14 @@
|
||||
==============
|
||||
B-U585I-IOT02A
|
||||
==============
|
||||
=================
|
||||
ST B-U585I-IOT02A
|
||||
=================
|
||||
|
||||
This README file discusses the port of NuttX to the STMicroelectronics
|
||||
This page discusses the port of NuttX to the STMicroelectronics
|
||||
B-U585I-IOT02A board. That board features the STM32U585AII6QU MCU with 2MiB
|
||||
of Flash and 768KiB of SRAM.
|
||||
|
||||
Status
|
||||
======
|
||||
|
||||
2022-02-13: With TrustedFirmware-M from STM32CubeU5 and signing the Apache
|
||||
NuttX binary image to get a tfm_ns_init.bin, the board now boots and the
|
||||
basic NSH configuration works with Apache NuttX as the OS running in the
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
===============
|
||||
NUCLEO-U5A5ZJ-Q
|
||||
===============
|
||||
==================
|
||||
ST Nucleo U5A5ZJ-Q
|
||||
==================
|
||||
|
||||
This README file discusses the port of NuttX to the STMicroelectronics
|
||||
This page file discusses the port of NuttX to the STMicroelectronics
|
||||
NUCLEO-U5A5ZJ-Q board. That board features the STM32U5A5ZJT6Q MCU with 4MiB
|
||||
of Flash and 2500KiB of SRAM.
|
||||
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
Flipper Zero
|
||||
============
|
||||
|
||||
This README file discusses the port of NuttX to the Flipper Zero multi-tool
|
||||
This page file discusses the port of NuttX to the Flipper Zero multi-tool
|
||||
device. See https://flipperzero.one/ for device details.
|
||||
|
||||
Device features
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
================
|
||||
ST NUCLEO-WB55RG
|
||||
ST Nucleo WB55RG
|
||||
================
|
||||
|
||||
This README file discusses the port of NuttX to the STMicroelectronics
|
||||
This page file discusses the port of NuttX to the STMicroelectronics
|
||||
NUCLEO-WB55RG board. That board features the multi-protocol wireless and
|
||||
ultra-low-power STM32WB55RGV6 MCU with 1MiB of Flash and 256KiB of SRAM.
|
||||
A dedicated M0+ coprocessor is responsible for performing the real-time
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
=============
|
||||
Nucleo-WL55JC
|
||||
=============
|
||||
================
|
||||
ST Nucleo WL55JC
|
||||
================
|
||||
|
||||
The `Nucleo-WL55JC <https://www.st.com/en/evaluation-tools/nucleo-wl55jc.html>`_
|
||||
is a development board for the STM32WL55 SoC from ST. It features 64 I/O,
|
||||
@ -11,17 +11,17 @@ via virtual serial port from usb.
|
||||
Features
|
||||
========
|
||||
|
||||
- STM32WL55JC MCU, 256K FLASH, 64K SRAM
|
||||
- 32768 Hz LSE crystal
|
||||
- 32 MHz HSE crystal
|
||||
- Embedded stlink-v3 debugger (debug/flash and virtual serial port)
|
||||
- Reset button
|
||||
- 3 user programmable LEDs
|
||||
- 3 user programmable buttons
|
||||
- Power indicator LED
|
||||
- LoRa radio with antenna
|
||||
- 64 Nucleo I/O
|
||||
- Arduino compatible pinout
|
||||
- STM32WL55JC MCU, 256K FLASH, 64K SRAM
|
||||
- 32768 Hz LSE crystal
|
||||
- 32 MHz HSE crystal
|
||||
- Embedded stlink-v3 debugger (debug/flash and virtual serial port)
|
||||
- Reset button
|
||||
- 3 user programmable LEDs
|
||||
- 3 user programmable buttons
|
||||
- Power indicator LED
|
||||
- LoRa radio with antenna
|
||||
- 64 Nucleo I/O
|
||||
- Arduino compatible pinout
|
||||
|
||||
Pin Mapping
|
||||
===========
|
||||
|
||||
Loading…
Reference in New Issue
Block a user