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Fix a cut'n'paste error in the last commit

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This commit is contained in:
Gregory Nutt 2015-05-10 10:23:23 -06:00
parent e6ebdba913
commit c7a02488c6
3 changed files with 13 additions and 3 deletions
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13
TODO
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@ -1135,11 +1135,20 @@ o USB (drivers/usbdev, drivers/usbhost)
removed. If I skip the 'cat /dev/ttyACM0', then the removed. If I skip the 'cat /dev/ttyACM0', then the
crash does not occur when the cable is removed. crash does not occur when the cable is removed.
UPDATE: A similar crash occurs on the SAMA5Dx OCHI driver.
Both the LPC17 and the SAMA5Dx are OHCI drivers.
Most of these problems are unique to the Olimex LPC1766STK Most of these problems are unique to the Olimex LPC1766STK
DCD; some are probably design problems in the CDC/ACM host DCD; some are probably design problems in the CDC/ACM host
driver. The bottom line is that the host CDC/ACM driver is driver. The bottom line is that the host CDC/ACM driver is
immature and you should probably not use it unless you want still immature and you could experience issues in some
to invest some effort. configurations if you use it.
That all being said, I know of know no issues with the current
CDC/ACM driver if the interrupt IN endpoint is not used, i.e.,
in "reduced" mode. The only loss of functionality is output
flow control.
Status: Open Status: Open
Priority: Medium-Low unless you really need host CDC/ACM support. Priority: Medium-Low unless you really need host CDC/ACM support.

2
arch/arm/src/sama5/sam_ohci.c
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@ -2167,7 +2167,7 @@ static void sam_wdh_bottomhalf(void)
{ {
/* Set the (fake) CBP to the end of the buffer + 1 */ /* Set the (fake) CBP to the end of the buffer + 1 */
tmp = xfrinfo->buflen; tmp = eplist->buflen;
} }
else else
{ {

1
drivers/usbhost/Kconfig
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@ -154,6 +154,7 @@ endchoice # CDC/ACM Protocol
config USBHOST_CDCACM_NTDELAY config USBHOST_CDCACM_NTDELAY
int "CDC/ACM notification polling interval (MSec)" int "CDC/ACM notification polling interval (MSec)"
default 400 default 400
depends on USBHOST_CDCACM_COMPLIANT
---help--- ---help---
On higher end host controllers (OHCI and EHCI), the asynchronous, On higher end host controllers (OHCI and EHCI), the asynchronous,
interrupt IN transfers will pend until data is available from the interrupt IN transfers will pend until data is available from the