Kinetis:Add FTM3 to PWM

arch/arm/src/kinetis/Kconfig

@@ -470,6 +470,13 @@ config KINETIS_FTM2
 	---help---
 		Support FlexTimer 2
 
+config KINETIS_FTM3
+	bool "FTM3"
+	default n
+	depends on ARCH_FAMILY_K64 || ARCH_FAMILY_K66
+	---help---
+		Support FlexTimer 3
+
 config KINETIS_LPTIMER
 	bool "Low power timer (LPTIMER)"
 	default n
@@ -558,7 +565,7 @@ config KINETIS_PIT
 endmenu
 
 menu "Kinetis FTM PWM Configuration"
-	depends on KINETIS_FTM0 || KINETIS_FTM1 || KINETIS_FTM2
+	depends on KINETIS_FTM0 || KINETIS_FTM1 || KINETIS_FTM2 || KINETIS_FTM3
 
 config KINETIS_FTM0_PWM
 	bool "FTM0 PWM"
@@ -623,6 +630,27 @@ config KINETIS_FTM2_CHANNEL
 		If FTM2 is enabled for PWM usage, you also need specifies the timer output
 		channel {0,..,1}
 
+config KINETIS_FTM3_PWM
+	bool "FTM3 PWM"
+	default n
+	depends on KINETIS_FTM3
+	---help---
+		Reserve timer 3 for use by PWM
+
+		Timer devices may be used for different purposes.  One special purpose is
+		to generate modulated outputs for such things as motor control.  If KINETIS_FTM3
+		is defined then THIS following may also be defined to indicate that
+		the timer is intended to be used for pulsed output modulation.
+
+config KINETIS_FTM3_CHANNEL
+	int "FTM3 PWM Output Channel"
+	default 0
+	range 0 7
+	depends on KINETIS_FTM3_PWM
+	---help---
+		If FTM3 is enabled for PWM usage, you also need specifies the timer output
+		channel {0,..,7}
+
 endmenu # Kinetis FTM PWM Configuration
 
 menu "Kinetis GPIO Interrupt Configuration"

arch/arm/src/kinetis/chip/kinetis_sim.h

@@ -174,6 +174,10 @@
                                                 /* Bits 5-7: Reserved */
 #define SIM_SOPT4_FTM2FLT0            (1 << 8)  /* Bit 8:  FTM2 Fault 0 Select */
                                                 /* Bits 9-17: Reserved */
+#if defined(CONFIG_KINETIS_FTM3)
+                                                /* Bits 9-11,13-17: Reserved */
+#  define SIM_SOPT4_FTM3FLT0          (1 << 12) /* Bit 12:  FTM3 Fault 0 Select */
+#endif
 #define SIM_SOPT4_FTM1CH0SRC_SHIFT    (18)      /* Bits 18-19: FTM1 channel 0 input capture source select */
 #define SIM_SOPT4_FTM1CH0SRC_MASK     (3 << SIM_SOPT4_FTM1CH0SRC_SHIFT)
 #  define SIM_SOPT4_FTM1CH0SRC_CH0    (0 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* FTM1_CH0 signal */
@@ -189,6 +193,11 @@
 #define SIM_SOPT4_FTM1CLKSEL          (1 << 25) /* Bit 25:  FTM1 External Clock Pin Select */
 #define SIM_SOPT4_FTM2CLKSEL          (1 << 26) /* Bit 26:  FlexTimer 2 External Clock Pin Select */
                                                 /* Bits 27-31: Reserved */
+#if defined(CONFIG_KINETIS_FTM3)
+#  define SIM_SOPT4_FTM3CLKSEL        (1 << 27) /* Bit 27: FlexTimer 3 External Clock Pin Select */
+#  define SIM_SOPT4_FTM3TRG0SRC       (1 << 30) /* Bit 30: FlexTimer 3 Hardware Trigger 0 Source Select */
+#  define SIM_SOPT4_FTM3TRG1SRC       (1 << 31) /* Bit 31: FlexTimer 3 Hardware Trigger 1 Source Select */
+#endif
 
 /* System Options Register 5 */
 
@@ -241,6 +250,9 @@
 #  define SIM_SOPT7_ADC0TRGSEL_FTM0   (8 << SIM_SOPT7_ADC0TRGSEL_SHIFT)  /* FTM0 trigger */
 #  define SIM_SOPT7_ADC0TRGSEL_FTM1   (9 << SIM_SOPT7_ADC0TRGSEL_SHIFT)  /* FTM1 trigger */
 #  define SIM_SOPT7_ADC0TRGSEL_FTM2   (10 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM2 trigger */
+#if defined(CONFIG_KINETIS_FTM3)
+#    define SIM_SOPT7_ADC0TRGSEL_FTM3 (11 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM3 trigger */
+#endif
 #  define SIM_SOPT7_ADC0TRGSEL_ALARM  (12 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* RTC alarm */
 #  define SIM_SOPT7_ADC0TRGSEL_SECS   (13 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* RTC seconds */
 #  define SIM_SOPT7_ADC0TRGSEL_LPTMR  (14 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* Low-power timer trigger */
@@ -261,6 +273,9 @@
 #  define SIM_SOPT7_ADC1TRGSEL_FTM1   (9 << SIM_SOPT7_ADC1TRGSEL_SHIFT)  /* FTM1 trigger */
 #  define SIM_SOPT7_ADC1TRGSEL_FTM2   (10 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM2 trigger */
 #  define SIM_SOPT7_ADC1TRGSEL_ALARM  (12 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* RTC alarm */
+#if defined(CONFIG_KINETIS_FTM3)
+#    define SIM_SOPT7_ADC1TRGSEL_FTM3 (11 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM3 trigger */
+#endif
 #  define SIM_SOPT7_ADC1TRGSEL_SECS   (13 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* RTC seconds */
 #  define SIM_SOPT7_ADC1TRGSEL_LPTMR  (14 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* Low-power timer trigger */
 #define SIM_SOPT7_ADC1PRETRGSEL       (1 << 12) /* Bit 12: ADC1 pre-trigger select */
@@ -323,6 +338,9 @@
                                                 /* Bits 18-23: Reserved */
 #define SIM_SCGC3_FTM2                (1 << 24) /* Bit 24: FTM2 Clock Gate Control */
                                                 /* Bits 25-26: Reserved */
+#if defined(CONFIG_KINETIS_FTM3)
+#  define SIM_SCGC3_FTM3              (1 << 25) /* Bit 25: FTM3 Clock Gate Control */
+#endif
 #define SIM_SCGC3_ADC1                (1 << 27) /* Bit 27: ADC1 Clock Gate Control */
                                                 /* Bits 28-29: Reserved */
 #if defined(KINETIS_NSLCD) && KINETIS_NSLCD > 0

arch/arm/src/kinetis/kinetis_pwm.c

@@ -1,10 +1,11 @@
 /****************************************************************************
  * arch/arm/src/kinetis/kinetis_pwm.c
  *
- *   Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013, 2016, 2017 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
- *           Alan Carvalho de Assis <acassis@gmail.com>
+ *            Alan Carvalho de Assis <acassis@gmail.com>
- *           Ken Fazzone <kfazz01@gmail.com>
+ *            Ken Fazzone <kfazz01@gmail.com>
+ *            David Sidrane <david_s5@nscdg.com>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -68,7 +69,7 @@
  */
 
 #if defined(CONFIG_KINETIS_FTM0_PWM)  || defined(CONFIG_KINETIS_FTM1_PWM)  || \
-    defined(CONFIG_KINETIS_FTM2_PWM)
+    defined(CONFIG_KINETIS_FTM2_PWM)  || defined(CONFIG_KINETIS_FTM3_PWM)
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -183,6 +184,18 @@ static struct kinetis_pwmtimer_s g_pwm2dev =
 };
 #endif
 
+#ifdef CONFIG_KINETIS_FTM3_PWM
+static struct kinetis_pwmtimer_s g_pwm3dev =
+{
+  .ops        = &g_pwmops,
+  .tpmid      = 3,
+  .channel    = CONFIG_KINETIS_FTM3_CHANNEL,
+  .base       = KINETIS_FTM3_BASE,
+  .pincfg     = PWM_FTM3_PINCFG,
+  .pclk       = BOARD_CORECLK_FREQ,
+};
+#endif
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -549,6 +562,9 @@ static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
 
   regval = getreg32(KINETIS_SIM_SCGC3);
   regval |= SIM_SCGC3_FTM2;
+#if defined(CONFIG_KINETIS_FTM3_PWM)
+  regval |= SIM_SCGC3_FTM3;
+#endif
   putreg32(regval, KINETIS_SIM_SCGC3);
 
   pwminfo("FTM%d pincfg: %08x\n", priv->tpmid, priv->pincfg);
@@ -778,6 +794,13 @@ FAR struct pwm_lowerhalf_s *kinetis_pwminitialize(int timer)
         break;
 #endif
 
+#ifdef CONFIG_KINETIS_FTM3_PWM
+      case 3:
+        lower = &g_pwm3dev;
+
+        break;
+#endif
+
       default:
         pwmerr("ERROR: No such timer configured\n");
         return NULL;
@@ -786,4 +809,4 @@ FAR struct pwm_lowerhalf_s *kinetis_pwminitialize(int timer)
   return (FAR struct pwm_lowerhalf_s *)lower;
 }
 
-#endif /* CONFIG_KINETIS_FTMn_PWM, n = 0,...,2 */
+#endif /* CONFIG_KINETIS_FTMn_PWM, n = 0,...,3 */

arch/arm/src/kinetis/kinetis_pwm.h

@@ -1,10 +1,11 @@
 /************************************************************************************
  * arch/arm/src/kinetis/kinetis_pwm.h
  *
- *   Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2013, 2016, 2017 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
- *           Alan Carvalho de Assis <acassis@gmail.com>
+ *            Alan Carvalho de Assis <acassis@gmail.com>
- *           Ken Fazzone <kfazz01@gmail.com>
+ *            Ken Fazzone <kfazz01@gmail.com>
+ *            David Sidrane <david_s5@nscdg.com>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -66,11 +67,14 @@
 #ifndef CONFIG_KINETIS_FTM2
 #  undef CONFIG_KINETIS_FTM2_PWM
 #endif
+#ifndef CONFIG_KINETIS_FTM3
+#  undef CONFIG_KINETIS_FTM3_PWM
+#endif
 
 /* Check if PWM support for any channel is enabled. */
 
 #if defined(CONFIG_KINETIS_FTM0_PWM)  || defined(CONFIG_KINETIS_FTM1_PWM)  || \
-    defined(CONFIG_KINETIS_FTM2_PWM)
+    defined(CONFIG_KINETIS_FTM2_PWM)  || defined(CONFIG_KINETIS_FTM3_PWM)
 
 #include <arch/board/board.h>
 #include "chip/kinetis_pinmux.h"
@@ -148,6 +152,30 @@
 #  endif
 #endif
 
+#ifdef CONFIG_KINETIS_FTM3_PWM
+#  if !defined(CONFIG_KINETIS_FTM3_CHANNEL)
+#    error "CONFIG_KINETIS_FTM3_CHANNEL must be provided"
+#  elif CONFIG_KINETIS_FTM3_CHANNEL == 0
+#    define PWM_FTM3_PINCFG GPIO_FTM3_CH0OUT
+#  elif CONFIG_KINETIS_FTM3_CHANNEL == 1
+#    define PWM_FTM3_PINCFG GPIO_FTM3_CH1OUT
+#  elif CONFIG_KINETIS_FTM3_CHANNEL == 2
+#    define PWM_FTM3_PINCFG GPIO_FTM3_CH2OUT
+#  elif CONFIG_KINETIS_FTM3_CHANNEL == 3
+#    define PWM_FTM3_PINCFG GPIO_FTM3_CH3OUT
+#  elif CONFIG_KINETIS_FTM3_CHANNEL == 4
+#    define PWM_FTM3_PINCFG GPIO_FTM3_CH4OUT
+#  elif CONFIG_KINETIS_FTM3_CHANNEL == 5
+#    define PWM_FTM3_PINCFG GPIO_FTM3_CH5OUT
+#  elif CONFIG_KINETIS_FTM3_CHANNEL == 6
+#    define PWM_FTM3_PINCFG GPIO_FTM3_CH6OUT
+#  elif CONFIG_KINETIS_FTM3_CHANNEL == 7
+#    define PWM_FTM3_PINCFG GPIO_FTM3_CH7OUT
+#  else
+#    error "Unsupported value of CONFIG_KINETIS_FTM3_CHANNEL"
+#  endif
+#endif
+
 /************************************************************************************
  * Public Types
  ************************************************************************************/