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Xtensa ESP32: Fix some compilation errors that snuck with some of the last changes

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This commit is contained in:
Gregory Nutt 2016-11-14 13:29:08 -06:00
parent 3b6c4b37b0
commit c84db68103
5 changed files with 42 additions and 9 deletions
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6
arch/xtensa/src/common/xtensa_windowspill.S
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@ -40,7 +40,7 @@
****************************************************************************/
#include <arch/esp32/core-isa.h>
#include <arch/xtensa_specregs.h>
#include <arch/xtensa/xtensa_specregs.h>
#include "xtensa_abi.h"
/****************************************************************************
@ -148,7 +148,7 @@ _xtensa_window_spill:
rsr a3, WINDOWSTART
srl a2, a3 /* a2 is 0... | 000000xxxxxxxxxx = WINDOWSTART >> sar */
sll a3, a3 /* a3 is 1yyyyy0000000000 | 0... = WINDOWSTART << (32 - sar) */
bgez a3, .Linvalid_ws /* verify that msbit is indeed set
bgez a3, .Linvalid_ws /* verify that msbit is indeed set */
srli a3, a3, 32-WSBITS /* a3 is 0... | 1yyyyy0000000000 = a3 >> (32-NAREG/4) */
or a2, a2, a3 /* a2 is 0... | 1yyyyyxxxxxxxxxx */
@ -202,7 +202,7 @@ _xtensa_window_spill:
add a3, a2, a3 /* a3 = WINDOWBASE + index */
#endif /* XCHAL_HAVE_NSA */
wsr a 3, WINDOWBASE /* Effectively do: rotw index */
wsr a3, WINDOWBASE /* Effectively do: rotw index */
rsync /* Wait for write to WINDOWBASE to complete */
/* Now our registers have changed! */

11
configs/esp32-core/Kconfig
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@ -5,4 +5,15 @@
if ARCH_BOARD_ESP32CORE
choice
prompt "On-board Crystal Frequency"
default ESP32CORE_XTAL_40MZ
config ESP32CORE_XTAL_40MZ
bool "40MHz"
config ESP32CORE_XTAL_26MHz
bool "26MHz"
endchoice # On-board Crystal Frequency
endif # ARCH_BOARD_ESP32CORE

17
configs/esp32-core/README.txt
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@ -303,6 +303,20 @@ Debug Issues
sudo ./src/openocd -s ./tcl -f tcl/interface/ftdi/olimex-arm-usb-ocd.cfg -f ./esp32.cfg
I then see:
Open On-Chip Debugger 0.10.0-dev-g3098897 (2016-11-14-12:19)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
adapter speed: 200 kHz
force hard breakpoints
Info : clock speed 200 kHz
Info : JTAG tap: esp32.cpu0 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : JTAG tap: esp32.cpu1 tap/device found: 0x120034e5 (mfg: 0x272 (Tensilica), part: 0x2003, ver: 0x1)
Info : esp32.cpu0: Debug controller was reset (pwrstat=0x5F, after clear 0x0F).
Info : esp32.cpu0: Core was reset (pwrstat=0x5F, after clear 0x0F).
Connecting a debugger to OpenOCD
--------------------------------
OpenOCD should now be ready to accept gdb connections. If you have
@ -318,7 +332,8 @@ Debug Issues
cd esp-idf-template
xtensa-esp32-elf-gdb -ex 'target remote localhost:3333' ./build/app-template.elf
This should give you a gdb prompt.
This should give you a gdb prompt.
JTAG Emulator
-------------

8
configs/esp32-core/include/board.h
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@ -41,9 +41,13 @@
****************************************************************************/
/* Clocking ****************************************************************/
/* The ESP32 Core board V2 is fitted with a 40MHz crystal */
/* The ESP32 Core board V2 is fitted with either a 26 a 40MHz crystal */
#define BOARD_XTAL_FREQUENCY 40000000
#ifdef CONFIG_ESP32CORE_XTAL_26MHz
# define BOARD_XTAL_FREQUENCY 26000000
#else
# define BOARD_XTAL_FREQUENCY 40000000
#endif
/* Clock reconfiguration is currently disabled, so the CPU will be running
* at the XTAL frequency.

9
configs/esp32-core/nsh/defconfig
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@ -62,6 +62,7 @@ CONFIG_DEBUG_FULLOPT=y
# CONFIG_ARCH_AVR is not set
# CONFIG_ARCH_HC is not set
# CONFIG_ARCH_MIPS is not set
# CONFIG_ARCH_MISOC is not set
# CONFIG_ARCH_RGMP is not set
# CONFIG_ARCH_RENESAS is not set
# CONFIG_ARCH_RISCV is not set
@ -170,6 +171,8 @@ CONFIG_ARCH_BOARD="esp32-core"
#
# Board-Specific Options
#
CONFIG_ESP32CORE_XTAL_40MZ=y
# CONFIG_ESP32CORE_XTAL26MHz is not set
# CONFIG_BOARD_CRASHDUMP is not set
# CONFIG_LIB_BOARDCTL is not set
@ -299,14 +302,14 @@ CONFIG_DEV_NULL=y
# CONFIG_ARCH_HAVE_I2CRESET is not set
# CONFIG_I2C is not set
CONFIG_SPI=y
# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set
# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set
# CONFIG_ARCH_HAVE_SPI_BITORDER is not set
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_EXCHANGE=y
# CONFIG_SPI_CMDDATA is not set
# CONFIG_SPI_CALLBACK is not set
# CONFIG_SPI_HWFEATURES is not set
# CONFIG_ARCH_HAVE_SPI_CRCGENERATION is not set
# CONFIG_ARCH_HAVE_SPI_CS_CONTROL is not set
# CONFIG_ARCH_HAVE_SPI_BITORDER is not set
# CONFIG_SPI_CS_DELAY_CONTROL is not set
# CONFIG_SPI_DRIVER is not set
# CONFIG_SPI_BITBANG is not set