xtensa/esp32s3: Move SPI RAM configuration out of Peripheral menu
Menu for configuration of SPI RAM was wrongly placed inside the menu for peripheral selection. Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
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@ -55,7 +55,7 @@ config ESP32S3_DEFAULT_CPU_FREQ_MHZ
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default 160 if ESP32S3_DEFAULT_CPU_FREQ_160
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default 240 if ESP32S3_DEFAULT_CPU_FREQ_240
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menu "Cache config"
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menu "Cache configuration"
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choice
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prompt "Instruction cache size"
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@ -298,11 +298,6 @@ config ESP32S3_RUN_IRAM
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menu "ESP32-S3 Peripheral Selection"
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config ESP32S3_SPIRAM
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bool "SPI RAM Support"
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default n
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select ARCH_HAVE_HEAP2
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config ESP32S3_UART
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bool
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default n
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@ -315,6 +310,10 @@ config ESP32S3_WDT
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bool
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default n
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config ESP32S3_SPIRAM
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bool "SPI RAM Support"
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default n
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config ESP32S3_UART0
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bool "UART 0"
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default n
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@ -336,13 +335,70 @@ config ESP32S3_UART2
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select UART2_SERIALDRIVER
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select ARCH_HAVE_SERIAL_TERMIOS
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menu "SPI RAM Config"
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config ESP32S3_TIMER0
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bool "54-bit Timer 0 (Group 0 Timer 0)"
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default n
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select ESP32S3_TIMER
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---help---
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Enables Timer 0
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config ESP32S3_TIMER1
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bool "54-bit Timer 1 (Group 0 Timer 1)"
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default n
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select ESP32S3_TIMER
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---help---
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Enables Timer 1
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config ESP32S3_TIMER2
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bool "54-bit Timer 2 (Group 1 Timer 0)"
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default n
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select ESP32S3_TIMER
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---help---
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Enables Timer 2
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config ESP32S3_TIMER3
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bool "54-bit Timer 3 (Group 1 Timer 1)"
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default n
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select ESP32S3_TIMER
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---help---
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Enables Timer 3
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config ESP32S3_MWDT0
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bool "Main System Watchdog Timer (Group 0)"
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default n
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select ESP32S3_WDT
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---help---
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Includes MWDT0. This watchdog timer is part of the Group 0
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timer submodule.
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config ESP32S3_MWDT1
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bool "Main System Watchdog Timer (Group 1)"
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default n
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select ESP32S3_WDT
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---help---
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Includes MWDT1. This watchdog timer is part of the Group 0
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timer submodule.
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config ESP32S3_RWDT
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bool "RTC Watchdog Timer"
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default n
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select ESP32S3_WDT
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---help---
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Includes RWDT. This watchdog timer is from the RTC module.
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When it is selected, if the developer sets it to reset on expiration
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it will reset Main System and the RTC module. If you don't want
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to have the RTC module reset, please, use the Timers' Module WDTs.
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They will only reset Main System.
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endmenu # ESP32-S3 Peripheral Selection
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menu "SPI RAM Configuration"
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depends on ESP32S3_SPIRAM
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choice ESP32S3_SPIRAM_MODE
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prompt "Mode (QUAD/OCT) of SPI RAM chip"
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default ESP32S3_SPIRAM_MODE_QUAD
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config ESP32S3_SPIRAM_MODE_QUAD
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bool "Quad Mode PSRAM"
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@ -447,64 +503,7 @@ config ESP32S3_SPIRAM_IGNORE_NOTFOUND
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panic. If this is enabled, booting will complete but no PSRAM
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will be available.
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endmenu #SPI RAM Config
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config ESP32S3_TIMER0
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bool "54-bit Timer 0 (Group 0 Timer 0)"
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default n
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select ESP32S3_TIMER
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---help---
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Enables Timer 0
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config ESP32S3_TIMER1
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bool "54-bit Timer 1 (Group 0 Timer 1)"
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default n
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select ESP32S3_TIMER
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---help---
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Enables Timer 1
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config ESP32S3_TIMER2
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bool "54-bit Timer 2 (Group 1 Timer 0)"
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default n
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select ESP32S3_TIMER
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---help---
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Enables Timer 2
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config ESP32S3_TIMER3
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bool "54-bit Timer 3 (Group 1 Timer 1)"
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default n
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select ESP32S3_TIMER
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---help---
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Enables Timer 3
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config ESP32S3_MWDT0
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bool "Main System Watchdog Timer (Group 0)"
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default n
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select ESP32S3_WDT
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---help---
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Includes MWDT0. This watchdog timer is part of the Group 0
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timer submodule.
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config ESP32S3_MWDT1
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bool "Main System Watchdog Timer (Group 1)"
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default n
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select ESP32S3_WDT
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---help---
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Includes MWDT1. This watchdog timer is part of the Group 0
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timer submodule.
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config ESP32S3_RWDT
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bool "RTC Watchdog Timer"
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default n
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select ESP32S3_WDT
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---help---
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Includes RWDT. This watchdog timer is from the RTC module.
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When it is selected, if the developer sets it to reset on expiration
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it will reset Main System and the RTC module. If you don't want
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to have the RTC module reset, please, use the Timers' Module WDTs.
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They will only reset Main System.
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endmenu # ESP32-S3 Peripheral Selection
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endmenu # SPI RAM Configuration
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menu "UART Configuration"
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depends on ESP32S3_UART
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