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BL602: Use sig mask instead of number for AHB swrst

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This commit is contained in:
Brennan Ashton 2020-12-30 13:06:13 -08:00 committed by Xiang Xiao
parent e062bd08ce
commit c8db3293bb
1 changed files with 26 additions and 25 deletions
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51
arch/risc-v/src/bl602/hardware/bl602_glb.h
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@ -823,30 +823,31 @@
#define TZC_GLB_CTRL_2_GPIO_1_LOCK (1 << 1)
#define TZC_GLB_CTRL_2_GPIO_0_LOCK (1 << 0)
#define AHB_SLAVE1_
#define AHB_SLAVE1_GLB (0)
#define AHB_SLAVE1_RF (1)
#define AHB_SLAVE1_GPIP (2)
#define AHB_SLAVE1_DBG (3)
#define AHB_SLAVE1_SEC (4)
#define AHB_SLAVE1_TZ1 (5)
#define AHB_SLAVE1_TZ2 (6)
#define AHB_SLAVE1_EFUSE (7)
#define AHB_SLAVE1_CCI (8)
#define AHB_SLAVE1_L1C (9)
#define AHB_SLAVE1_RESV10 (10)
#define AHB_SLAVE1_SFC (11)
#define AHB_SLAVE1_DMA (12)
#define AHB_SLAVE1_SDU (13)
#define AHB_SLAVE1_PDSHBN (14)
#define AHB_SLAVE1_WRAM (15)
#define AHB_SLAVE1_UART0 (16)
#define AHB_SLAVE1_UART1 (17)
#define AHB_SLAVE1_SPI (18)
#define AHB_SLAVE1_I2C (19)
#define AHB_SLAVE1_PWM (20)
#define AHB_SLAVE1_TMR (21)
#define AHB_SLAVE1_IRR (22)
#define AHB_SLAVE1_CKS (23)
/* Map common names to these SWRST signals */
#define AHB_SLAVE1_GLB (SWRST_CFG1_SWRST_S10)
#define AHB_SLAVE1_RF (SWRST_CFG1_SWRST_S11)
#define AHB_SLAVE1_GPIP (SWRST_CFG1_SWRST_S12)
#define AHB_SLAVE1_DBG (SWRST_CFG1_SWRST_S13)
#define AHB_SLAVE1_SEC (SWRST_CFG1_SWRST_S14)
#define AHB_SLAVE1_TZ1 (SWRST_CFG1_SWRST_S15)
#define AHB_SLAVE1_TZ2 (SWRST_CFG1_SWRST_S16)
#define AHB_SLAVE1_EFUSE (SWRST_CFG1_SWRST_S17)
#define AHB_SLAVE1_CCI (SWRST_CFG1_SWRST_S18)
#define AHB_SLAVE1_L1C (SWRST_CFG1_SWRST_S19)
#define AHB_SLAVE1_SFC (SWRST_CFG1_SWRST_S1B)
#define AHB_SLAVE1_DMA (SWRST_CFG1_SWRST_S1C)
#define AHB_SLAVE1_SDU (SWRST_CFG1_SWRST_S1D)
#define AHB_SLAVE1_PDSHBN (SWRST_CFG1_SWRST_S1E)
#define AHB_SLAVE1_WRAM (SWRST_CFG1_SWRST_S1F)
#define AHB_SLAVE1_UART0 (SWRST_CFG1_SWRST_S1A0)
#define AHB_SLAVE1_UART1 (SWRST_CFG1_SWRST_S1A1)
#define AHB_SLAVE1_SPI (SWRST_CFG1_SWRST_S1A2)
#define AHB_SLAVE1_I2C (SWRST_CFG1_SWRST_S1A3)
#define AHB_SLAVE1_PWM (SWRST_CFG1_SWRST_S1A4)
#define AHB_SLAVE1_TMR (SWRST_CFG1_SWRST_S1A5)
#define AHB_SLAVE1_IRR (SWRST_CFG1_SWRST_S1A6)
#define AHB_SLAVE1_CKS (SWRST_CFG1_SWRST_S1A7)
#endif /* __ARCH_RISCV_SRC_HARDWARE_GLB_H */