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Fields of vector offset table appear to vary with MCU

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5758 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2013-03-19 01:28:50 +00:00
parent aaa240782b
commit c8e9fcbe69
3 changed files with 41 additions and 18 deletions
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34
arch/arm/src/armv7-m/nvic.h
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@ -483,6 +483,26 @@
#define NVIC_SYSH_PRIORITY_PR15_SHIFT 24
#define NVIC_SYSH_PRIORITY_PR15_MASK (0xff << NVIC_SYSH_PRIORITY_PR15_SHIFT)
/* Vector Table Offset Register (VECTAB) */
#define NVIC_VECTAB_TBLOFF_MASK (0xffffffc0)
#define NVIC_VECTAB_TBLBASE (0)
#define NVIC_VECTAB_ALIGN_MASK (0x0000003f)
/* Application Interrupt and Reset Control Register (AIRCR) */
#define NVIC_AIRCR_VECTRESET (1 << 0) /* Bit 0: VECTRESET */
#define NVIC_AIRCR_VECTCLRACTIVE (1 << 1) /* Bit 1: Reserved for debug use */
#define NVIC_AIRCR_SYSRESETREQ (1 << 2) /* Bit 2: System reset */
/* Bits 2-7: Reserved */
#define NVIC_AIRCR_PRIGROUP_SHIFT (8) /* Bits 8-14: PRIGROUP */
#define NVIC_AIRCR_PRIGROUP_MASK (7 << NVIC_AIRCR_PRIGROUP_SHIFT)
#define NVIC_AIRCR_ENDIANNESS (1 << 15) /* Bit 15: 1=Big endian */
#define NVIC_AIRCR_VECTKEY_SHIFT (16) /* Bits 16-31: VECTKEY */
#define NVIC_AIRCR_VECTKEY_MASK (0xffff << NVIC_AIRCR_VECTKEY_SHIFT)
#define NVIC_AIRCR_VECTKEYSTAT_SHIFT (16) /* Bits 16-31: VECTKEYSTAT */
#define NVIC_AIRCR_VECTKEYSTAT_MASK (0xffff << NVIC_AIRCR_VECTKEYSTAT_SHIFT)
/* System handler control and state register (SYSHCON) */
#define NVIC_SYSHCON_MEMFAULTACT (1 << 0) /* Bit 0: MemManage is active */
@ -500,20 +520,6 @@
#define NVIC_SYSHCON_BUSFAULTENA (1 << 17) /* Bit 17: BusFault enabled */
#define NVIC_SYSHCON_USGFAULTENA (1 << 18) /* Bit 18: UsageFault enabled */
/* Application Interrupt and Reset Control Register (AIRCR) */
#define NVIC_AIRCR_VECTRESET (1 << 0) /* Bit 0: VECTRESET */
#define NVIC_AIRCR_VECTCLRACTIVE (1 << 1) /* Bit 1: Reserved for debug use */
#define NVIC_AIRCR_SYSRESETREQ (1 << 2) /* Bit 2: System reset */
/* Bits 2-7: Reserved */
#define NVIC_AIRCR_PRIGROUP_SHIFT (8) /* Bits 8-14: PRIGROUP */
#define NVIC_AIRCR_PRIGROUP_MASK (7 << NVIC_AIRCR_PRIGROUP_SHIFT)
#define NVIC_AIRCR_ENDIANNESS (1 << 15) /* Bit 15: 1=Big endian */
#define NVIC_AIRCR_VECTKEY_SHIFT (16) /* Bits 16-31: VECTKEY */
#define NVIC_AIRCR_VECTKEY_MASK (0xffff << NVIC_AIRCR_VECTKEY_SHIFT)
#define NVIC_AIRCR_VECTKEYSTAT_SHIFT (16) /* Bits 16-31: VECTKEYSTAT */
#define NVIC_AIRCR_VECTKEYSTAT_MASK (0xffff << NVIC_AIRCR_VECTKEYSTAT_SHIFT)
/* Debug Exception and Monitor Control Register (DEMCR) */
#define NVIC_DEMCR_VCCORERESET (1 << 0) /* Bit 0: Reset Vector Catch */

12
arch/arm/src/armv7-m/up_ramvec_initialize.c
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@ -43,6 +43,8 @@
#include "nvic.h"
#include "ram_vectors.h"
#include "chip.h" /* May redefine VECTAB fields */
#include "up_arch.h"
#include "up_internal.h"
@ -98,7 +100,7 @@ void up_ramvec_initialize(void)
/* The vector table must be aligned */
DEBUGASSERT(((uintptr)g_ram_vectors & 0x3f) == 0);
DEBUGASSERT(((uintptr)g_ram_vectors & NVIC_VECTAB_ALIGN_MASK) == 0);
/* Copy the ROM vector table at address zero to RAM vector table.
*
@ -114,11 +116,13 @@ void up_ramvec_initialize(void)
*dest++ = *src++;
}
/* Now configure the NVIC to use the new vector table. Bit 29 indicates
* that the vector table is in RAM.
/* Now configure the NVIC to use the new vector table. The TBLBASE bit
* indicates that the vectors are in RAM. NOTE: These fields appear to
* differ among various ARMv7-M implementations.
*/
putreg32((uint32_t)g_ram_vectors | (1 << 29), NVIC_VECTAB);
putreg32(((uint32_t)g_ram_vectors & NVIC_VECTAB_TBLOFF_MASK) | NVIC_VECTAB_TBLBASE,
NVIC_VECTAB);
}
#endif /* !CONFIG_ARCH_RAMVECTORS */

13
arch/arm/src/lpc17xx/chip.h
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@ -41,6 +41,7 @@
************************************************************************************/
#include <nuttx/config.h>
#include "nvic.h"
/* Include the chip capabilities file */
@ -60,6 +61,18 @@
# endif
#endif
/* Vector Table Offset Register (VECTAB). Redefine some bits defined in
* arch/arm/src/armv7-m/nvic.h; The LPC178x/7x User manual definitions
* do not match the ARMv7M field definitions.
*/
#undef NVIC_VECTAB_TBLOFF_MASK
#define NVIC_VECTAB_TBLOFF_MASK (0x3fffff00)
#undef NVIC_VECTAB_TBLBASE
#define NVIC_VECTAB_TBLBASE (1 << 29)
#undef NVIC_VECTAB_ALIGN_MASK
#define NVIC_VECTAB_ALIGN_MASK (0x000000ff)
/* Include the memory map file. Other chip hardware files should then include
* this file for the proper setup.
*/