stm32f777zit6-meadow: Fix external RAM pinout and add board profile
This patch will fix an issue that was preventing the stm32f7 board from working with external SDRAM memory.
This commit is contained in:
Alan Carvalho de Assis
Xiang Xiao
parent
c5641b0252
commit
c9f610f44f
@ -0,0 +1,48 @@
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#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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# CONFIG_STM32F7_USE_LEGACY_PINMAP is not set
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CONFIG_ARCH="arm"
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CONFIG_ARCH_BOARD="stm32f777zit6-meadow"
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CONFIG_ARCH_BOARD_MEADOW_F7MICRO=y
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CONFIG_ARCH_CHIP="stm32f7"
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CONFIG_ARCH_CHIP_STM32F777ZI=y
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CONFIG_ARCH_CHIP_STM32F7=y
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_ARMV7M_DCACHE=y
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CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
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CONFIG_ARMV7M_DTCM=y
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CONFIG_ARMV7M_ICACHE=y
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CONFIG_BOARD_LOOPSPERMSEC=43103
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CONFIG_BUILTIN=y
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CONFIG_HAVE_CXX=y
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CONFIG_HAVE_CXXINITIALIZE=y
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CONFIG_HEAP2_BASE=0xc0000000
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CONFIG_HEAP2_SIZE=33554432
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CONFIG_INIT_ENTRYPOINT="nsh_main"
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CONFIG_INTELHEX_BINARY=y
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CONFIG_MM_REGIONS=3
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CONFIG_NSH_ARCHINIT=y
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_FILEIOSIZE=512
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CONFIG_NSH_LINELEN=64
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CONFIG_NSH_READLINE=y
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CONFIG_PREALLOC_TIMERS=4
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CONFIG_RAM_SIZE=245760
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CONFIG_RAM_START=0x20010000
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CONFIG_RAW_BINARY=y
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CONFIG_RR_INTERVAL=200
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CONFIG_SCHED_WAITPID=y
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CONFIG_SPI=y
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CONFIG_START_DAY=14
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CONFIG_STM32F7_EXTERNAL_RAM=y
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CONFIG_STM32F7_FMC=y
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CONFIG_STM32F7_USART1=y
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CONFIG_SYSTEM_NSH=y
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CONFIG_SYSTEM_RAMTEST=y
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CONFIG_TASK_NAME_SIZE=0
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CONFIG_USART1_SERIAL_CONSOLE=y
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@ -494,10 +494,54 @@
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#define GPIO_SDMMC2_D2 (GPIO_SDMMC2_D2_1|GPIO_SPEED_50MHz)
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#define GPIO_SDMMC2_D3 (GPIO_SDMMC2_D3_1|GPIO_SPEED_50MHz)
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/* OTGFS */
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#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0|GPIO_SPEED_100MHz)
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#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0|GPIO_SPEED_100MHz)
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#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0|GPIO_SPEED_100MHz)
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/* FMC - SDRAM */
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#define GPIO_FMC_A0 (GPIO_FMC_A0_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_A1 (GPIO_FMC_A1_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_A2 (GPIO_FMC_A2_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_A3 (GPIO_FMC_A3_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_A4 (GPIO_FMC_A4_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_A5 (GPIO_FMC_A5_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_A6 (GPIO_FMC_A6_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_A7 (GPIO_FMC_A7_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_A8 (GPIO_FMC_A8_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_A9 (GPIO_FMC_A9_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_A10 (GPIO_FMC_A10_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_A11 (GPIO_FMC_A11_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_A12 (GPIO_FMC_A12_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_BA0 (GPIO_FMC_BA0_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_BA1 (GPIO_FMC_BA1_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D0 (GPIO_FMC_D0_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D1 (GPIO_FMC_D1_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D2 (GPIO_FMC_D2_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D3 (GPIO_FMC_D3_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D4 (GPIO_FMC_D4_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D5 (GPIO_FMC_D5_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D6 (GPIO_FMC_D6_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D7 (GPIO_FMC_D7_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D8 (GPIO_FMC_D8_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D9 (GPIO_FMC_D9_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D10 (GPIO_FMC_D10_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D11 (GPIO_FMC_D11_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D12 (GPIO_FMC_D12_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D13 (GPIO_FMC_D13_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D14 (GPIO_FMC_D14_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_D15 (GPIO_FMC_D15_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_NBL0 (GPIO_FMC_NBL0_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_NBL1 (GPIO_FMC_NBL1_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_SDCLK (GPIO_FMC_SDCLK_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_SDCKE0 (GPIO_FMC_SDCKE0_3|GPIO_SPEED_100MHz)
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#define GPIO_FMC_SDCKE1 (GPIO_FMC_SDCKE1_1|GPIO_SPEED_100MHz)
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#define GPIO_FMC_SDNE0 (GPIO_FMC_SDNE0_3|GPIO_SPEED_100MHz)
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#define GPIO_FMC_SDNE1 (GPIO_FMC_SDNE1_1|GPIO_SPEED_100MHz)
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#define GPIO_FMC_SDNWE (GPIO_FMC_SDNWE_1|GPIO_SPEED_100MHz)
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#define GPIO_FMC_SDNCAS (GPIO_FMC_SDNCAS_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_SDNRAS (GPIO_FMC_SDNRAS_0|GPIO_SPEED_100MHz)
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#define GPIO_FMC_SDNWE (GPIO_FMC_SDNWE_3|GPIO_SPEED_100MHz)
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#endif /* __BOARDS_ARM_STM32F777ZIT6_MEADOW_INCLUDE_BOARD_H */
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@ -34,6 +34,9 @@ endif
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ifeq ($(CONFIG_BOARDCTL),y)
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CSRCS += stm32_appinitialize.c
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ifeq ($(CONFIG_BOARDCTL_IOCTL),y)
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CSRCS += stm32_ioctl.c
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endif
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endif
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ifeq ($(CONFIG_PWM),y)
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@ -48,4 +51,10 @@ ifeq ($(CONFIG_STM32F7_FMC),y)
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CSRCS += stm32_extmem.c
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endif
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ifeq ($(CONFIG_STM32F7_OTGFS),y)
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CSRCS += stm32_usb.c
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else ifeq ($(CONFIG_STM32F7_OTGFSHS),y)
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CSRCS += stm32_usb.c
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endif
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include $(TOPDIR)/boards/Board.mk
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@ -129,9 +129,6 @@ void board_late_initialize(void)
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#ifdef CONFIG_STM32F7_QUADSPI
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FAR struct qspi_dev_s *qspi;
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FAR struct mtd_dev_s *mtd;
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#endif
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#ifdef CONFIG_STM32F7_QUADSPI
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struct qspi_meminfo_s meminfo;
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@ -167,9 +164,15 @@ void board_late_initialize(void)
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stm32f7_qspi_enter_memorymapped(qspi, &meminfo, 80000000);
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stm32_mpu_uheap((uintptr_t)0x90000000, 0x4000000);
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}
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#endif
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stm32_bringup();
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#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_BOARDCTL)
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/* Perform NSH initialization here instead of from the NSH. This
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* alternative NSH initialization is necessary when NSH is ran in
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* user-space but the initialization function must run in kernel space.
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*/
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board_app_initialize();
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#endif
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}
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#endif
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@ -52,15 +52,16 @@
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#define STM32_FMC_NADDRCONFIGS 23
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#define STM32_FMC_NDATACONFIGS 16
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#define STM32_SDRAM_CLKEN FMC_SDRAM_MODE_CMD_CLK_ENABLE | FMC_SDRAM_CMD_BANK_1
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#define STM32_SDRAM_PALL FMC_SDRAM_MODE_CMD_PALL | FMC_SDRAM_CMD_BANK_1
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#define STM32_SDRAM_REFRESH FMC_SDRAM_MODE_CMD_AUTO_REFRESH | FMC_SDRAM_CMD_BANK_1 |\
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(3 << FMC_SDRAM_AUTO_REFRESH_SHIFT)
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#define STM32_SDRAM_MODEREG FMC_SDRAM_MODE_CMD_LOAD_MODE | FMC_SDRAM_CMD_BANK_1 |\
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FMC_SDRAM_MODEREG_BURST_LENGTH_1 | \
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FMC_SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |\
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FMC_SDRAM_MODEREG_CAS_LATENCY_3 |\
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FMC_SDRAM_MODEREG_WRITEBURST_MODE_SINGLE
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#define STM32_SDRAM_CLKEN FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_CLK_ENABLE
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#define STM32_SDRAM_PALL FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_PALL
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#define STM32_SDRAM_REFRESH FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_AUTO_REFRESH |\
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FMC_SDCMR_NRFS(8)
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#define STM32_SDRAM_MODEREG FMC_SDCMR_CTB1 | FMC_SDCMR_MODE_LOAD_MODE |\
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FMC_SDCMR_MRD_BURST_LENGTH_1 | \
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FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |\
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FMC_SDCMR_MRD_CAS_LATENCY_3 |\
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FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |\
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FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE
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/****************************************************************************
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* Public Data
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@ -74,15 +75,15 @@ static const uint32_t g_addressconfig[STM32_FMC_NADDRCONFIGS] =
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GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7, GPIO_FMC_A8, GPIO_FMC_A9,
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GPIO_FMC_A10, GPIO_FMC_A11, GPIO_FMC_A12,
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GPIO_FMC_SDCKE0_3, GPIO_FMC_SDNE0_3, GPIO_FMC_SDNWE_3, GPIO_FMC_NBL0,
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GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1,
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GPIO_FMC_SDCLK, GPIO_FMC_SDNCAS
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GPIO_FMC_SDCKE0, GPIO_FMC_SDNE0, GPIO_FMC_SDNWE, GPIO_FMC_NBL0,
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GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1,
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GPIO_FMC_SDCLK, GPIO_FMC_SDNCAS
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};
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static const uint32_t g_dataconfig[STM32_FMC_NDATACONFIGS] =
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{
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GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, GPIO_FMC_D4,
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GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, GPIO_FMC_D8, GPIO_FMC_D9,
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GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, GPIO_FMC_D4,
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GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, GPIO_FMC_D8, GPIO_FMC_D9,
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GPIO_FMC_D10, GPIO_FMC_D11, GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14,
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GPIO_FMC_D15
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};
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@ -115,6 +116,33 @@ static void stm32_extmemgpios(const uint32_t *gpios, int ngpios)
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}
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}
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/****************************************************************************
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* Name: stm32_sdramcommand
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*
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* Description:
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* Initialize data line GPIOs for external memory access
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*/
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static void stm32_sdramcommand(uint32_t command)
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{
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uint32_t regval;
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volatile uint32_t timeout = 0xffff;
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regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
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while ((regval != 0) && timeout-- > 0)
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{
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regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
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}
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putreg32(command, STM32_FMC_SDCMR);
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timeout = 0xffff;
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regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
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while ((regval != 0) && timeout-- > 0)
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{
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regval = getreg32(STM32_FMC_SDSR) & 0x00000020;
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}
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -129,7 +157,7 @@ static void stm32_extmemgpios(const uint32_t *gpios, int ngpios)
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void stm32_sdram_initialize(void)
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{
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uint32_t val;
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uint32_t regval;
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volatile int count;
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/* Enable GPIOs as FMC / memory pins */
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@ -148,37 +176,37 @@ void stm32_sdram_initialize(void)
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* All timings from the datasheet for Speedgrade -7 (=7ns)
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*/
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putreg32(FMC_SDRAM_CR_RPIPE_1 |
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FMC_SDRAM_CR_SDCLK_2X |
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FMC_SDRAM_CR_CASLAT_3 |
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FMC_SDRAM_CR_BANKS_4 |
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FMC_SDRAM_CR_WIDTH_16 |
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FMC_SDRAM_CR_ROWBITS_13 |
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FMC_SDRAM_CR_COLBITS_9,
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putreg32(FMC_SDCR_RPIPE_1 |
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FMC_SDCR_SDCLK_2X |
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FMC_SDCR_CASLAT_3 |
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FMC_SDCR_BANKS_4 |
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FMC_SDCR_WIDTH_16 |
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FMC_SDCR_ROWBITS_13 |
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FMC_SDCR_COLBITS_9,
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STM32_FMC_SDCR1);
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putreg32(FMC_SDRAM_CR_RPIPE_1 |
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FMC_SDRAM_CR_SDCLK_2X |
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FMC_SDRAM_CR_CASLAT_3 |
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FMC_SDRAM_CR_BANKS_4 |
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FMC_SDRAM_CR_WIDTH_16 |
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FMC_SDRAM_CR_ROWBITS_13 |
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FMC_SDRAM_CR_COLBITS_9,
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putreg32(FMC_SDCR_RPIPE_1 |
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FMC_SDCR_SDCLK_2X |
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FMC_SDCR_CASLAT_3 |
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FMC_SDCR_BANKS_4 |
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FMC_SDCR_WIDTH_16 |
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FMC_SDCR_ROWBITS_13 |
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FMC_SDCR_COLBITS_9,
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STM32_FMC_SDCR2);
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putreg32((2 << FMC_SDRAM_TR_TRCD_SHIFT) | /* tRCD min = 15ns */
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(2 << FMC_SDRAM_TR_TRP_SHIFT) | /* tRP min = 15ns */
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(2 << FMC_SDRAM_TR_TWR_SHIFT) | /* tWR = 2CLK */
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(7 << FMC_SDRAM_TR_TRC_SHIFT) | /* tRC min = 63ns */
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(4 << FMC_SDRAM_TR_TRAS_SHIFT) | /* tRAS min = 42ns */
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(7 << FMC_SDRAM_TR_TXSR_SHIFT) | /* tXSR min = 70ns */
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(2 << FMC_SDRAM_TR_TMRD_SHIFT), /* tMRD = 2CLK */
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putreg32((2 << FMC_SDTR_TRCD_SHIFT) | /* tRCD min = 15ns */
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(2 << FMC_SDTR_TRP_SHIFT) | /* tRP min = 15ns */
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(2 << FMC_SDTR_TWR_SHIFT) | /* tWR = 2CLK */
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(7 << FMC_SDTR_TRC_SHIFT) | /* tRC min = 63ns */
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(4 << FMC_SDTR_TRAS_SHIFT) | /* tRAS min = 42ns */
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(7 << FMC_SDTR_TXSR_SHIFT) | /* tXSR min = 70ns */
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(2 << FMC_SDTR_TMRD_SHIFT), /* tMRD = 2CLK */
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STM32_FMC_SDTR1);
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/* SDRAM Initialization sequence */
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stm32_sdramcommand(STM32_SDRAM_CLKEN); /* Clock enable command */
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for (count = 0; count < 10000; count++) ; /* Delay */
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for (count = 0; count < 10000; count++); /* Delay */
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stm32_sdramcommand(STM32_SDRAM_PALL); /* Precharge ALL command */
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stm32_sdramcommand(STM32_SDRAM_REFRESH); /* Auto refresh command */
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stm32_sdramcommand(STM32_SDRAM_MODEREG); /* Mode Register program */
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341
boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c
Normal file
341
boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c
Normal file
@ -0,0 +1,341 @@
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/****************************************************************************
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* boards/arm/stm32f7/stm32f777zit6-meadow/src/stm32_usb.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <sched.h>
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#include <errno.h>
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#include <assert.h>
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#include <debug.h>
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#include <nuttx/kthread.h>
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#include <nuttx/usb/usbdev.h>
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#include <nuttx/usb/usbhost.h>
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#include <nuttx/usb/usbdev_trace.h>
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#include <arch/board/board.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
#include "stm32_otg.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32f777zit6-meadow.h"
|
||||
|
||||
#ifdef CONFIG_STM32F7_OTGFS
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST)
|
||||
# define HAVE_USB 1
|
||||
#else
|
||||
# warning "CONFIG_STM32F7_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST"
|
||||
# undef HAVE_USB
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_STM32F7F4DISCO_USBHOST_PRIO
|
||||
# define CONFIG_STM32F7F4DISCO_USBHOST_PRIO 100
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_STM32F7F4DISCO_USBHOST_STACKSIZE
|
||||
# define CONFIG_STM32F7F4DISCO_USBHOST_STACKSIZE 1024
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
static struct usbhost_connection_s *g_usbconn;
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: usbhost_waiter
|
||||
*
|
||||
* Description:
|
||||
* Wait for USB devices to be connected.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
static int usbhost_waiter(int argc, char *argv[])
|
||||
{
|
||||
struct usbhost_hubport_s *hport;
|
||||
|
||||
uinfo("Running\n");
|
||||
for (; ; )
|
||||
{
|
||||
/* Wait for the device to change state */
|
||||
|
||||
DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport));
|
||||
uinfo("%s\n", hport->connected ? "connected" : "disconnected");
|
||||
|
||||
/* Did we just become connected? */
|
||||
|
||||
if (hport->connected)
|
||||
{
|
||||
/* Yes.. enumerate the newly connected device */
|
||||
|
||||
CONN_ENUMERATE(g_usbconn, hport);
|
||||
}
|
||||
}
|
||||
|
||||
/* Keep the compiler from complaining */
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_usbinitialize
|
||||
*
|
||||
* Description:
|
||||
* Called from stm32_usbinitialize very early in inialization to setup
|
||||
* USB-related GPIO pins for the STM32F4Discovery board.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_usbinitialize(void)
|
||||
{
|
||||
/* The OTG FS has an internal soft pull-up.
|
||||
* No GPIO configuration is required
|
||||
*/
|
||||
|
||||
/* Configure the OTG FS VBUS sensing GPIO,
|
||||
* Power On, and Overcurrent GPIOs
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32F7_OTGFS
|
||||
stm32_configgpio(GPIO_OTGFS_VBUS);
|
||||
# ifdef CONFIG_USBHOST
|
||||
stm32_configgpio(GPIO_OTGFS_PWRON);
|
||||
stm32_configgpio(GPIO_OTGFS_OVER);
|
||||
# endif
|
||||
#endif
|
||||
stm32_configgpio(GPIO_OTGFS_VBUS);
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
stm32_configgpio(GPIO_OTGFS_PWRON);
|
||||
stm32_configgpio(GPIO_OTGFS_OVER);
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_usbhost_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called at application startup time to initialize the USB host
|
||||
* functionality.
|
||||
* This function will start a thread that will monitor for device
|
||||
* connection/disconnection events.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
int stm32_usbhost_initialize(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/* First, register all of the class drivers needed to support the drivers
|
||||
* that we care about:
|
||||
*/
|
||||
|
||||
uinfo("Register class drivers\n");
|
||||
|
||||
#ifdef CONFIG_USBHOST_HUB
|
||||
/* Initialize USB hub class support */
|
||||
|
||||
ret = usbhost_hub_initialize();
|
||||
if (ret < 0)
|
||||
{
|
||||
uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USBHOST_MSC
|
||||
/* Register the USB mass storage class class */
|
||||
|
||||
ret = usbhost_msc_initialize();
|
||||
if (ret != OK)
|
||||
{
|
||||
uerr("ERROR: Failed to register the mass storage class: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USBHOST_CDCACM
|
||||
/* Register the CDC/ACM serial class */
|
||||
|
||||
ret = usbhost_cdcacm_initialize();
|
||||
if (ret != OK)
|
||||
{
|
||||
uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USBHOST_HIDKBD
|
||||
/* Initialize the HID keyboard class */
|
||||
|
||||
ret = usbhost_kbdinit();
|
||||
if (ret != OK)
|
||||
{
|
||||
uerr("ERROR: Failed to register the HID keyboard class\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_USBHOST_HIDMOUSE
|
||||
/* Initialize the HID mouse class */
|
||||
|
||||
ret = usbhost_mouse_init();
|
||||
if (ret != OK)
|
||||
{
|
||||
uerr("ERROR: Failed to register the HID mouse class\n");
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Then get an instance of the USB host interface */
|
||||
|
||||
uinfo("Initialize USB host\n");
|
||||
g_usbconn = stm32_otgfshost_initialize(0);
|
||||
if (g_usbconn)
|
||||
{
|
||||
/* Start a thread to handle device connection. */
|
||||
|
||||
uinfo("Start usbhost_waiter\n");
|
||||
|
||||
ret = kthread_create("usbhost", CONFIG_STM32F7F4DISCO_USBHOST_PRIO,
|
||||
CONFIG_STM32F7F4DISCO_USBHOST_STACKSIZE,
|
||||
(main_t)usbhost_waiter, (char * const *)NULL);
|
||||
return ret < 0 ? -ENOEXEC : OK;
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_usbhost_vbusdrive
|
||||
*
|
||||
* Description:
|
||||
* Enable/disable driving of VBUS 5V output. This function must be
|
||||
* provided be each platform that implements the STM32 OTG FS host
|
||||
* interface
|
||||
*
|
||||
* "On-chip 5 V VBUS generation is not supported. For this reason, a
|
||||
* charge pump or, if 5 V are available on the application board, a
|
||||
* basic power switch, must be added externally to drive the 5 V VBUS
|
||||
* line. The external charge pump can be driven by any GPIO output.
|
||||
* When the application decides to power on VBUS using the chosen GPIO,
|
||||
* it must also set the port power bit in the host port control and
|
||||
* status register (PPWR bit in OTG_FS_HPRT).
|
||||
*
|
||||
* "The application uses this field to control power to this port,
|
||||
* and the core clears this bit on an overcurrent condition."
|
||||
*
|
||||
* Input Parameters:
|
||||
* iface - For future growth to handle multiple USB host interface.
|
||||
* Should be zero.
|
||||
* enable - true: enable VBUS power; false: disable VBUS power
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
void stm32_usbhost_vbusdrive(int iface, bool enable)
|
||||
{
|
||||
DEBUGASSERT(iface == 0);
|
||||
|
||||
syslog(LOG_INFO, "USB Drive %i %i", iface, (int)enable);
|
||||
|
||||
if (enable)
|
||||
{
|
||||
/* Enable the Power Switch by driving the enable pin low */
|
||||
|
||||
stm32_gpiowrite(GPIO_OTGFS_PWRON, false);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Power Switch by driving the enable pin high */
|
||||
|
||||
stm32_gpiowrite(GPIO_OTGFS_PWRON, true);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_setup_overcurrent
|
||||
*
|
||||
* Description:
|
||||
* Setup to receive an interrupt-level callback if an overcurrent
|
||||
* condition is detected.
|
||||
*
|
||||
* Input Parameters:
|
||||
* handler - New overcurrent interrupt handler
|
||||
* arg - The argument provided for the interrupt handler
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. Otherwise, a negated errno value
|
||||
* is returned to indicate the nature of the failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBHOST
|
||||
int stm32_setup_overcurrent(xcpt_t handler, void *arg)
|
||||
{
|
||||
return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler, arg);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_usbsuspend
|
||||
*
|
||||
* Description:
|
||||
* Board logic must provide the stm32_usbsuspend logic if the USBDEV
|
||||
* driver is used. This function is called whenever the USB enters or
|
||||
* leaves suspend mode. This is an opportunity for the board logic to
|
||||
* shutdown clocks, power, etc. while the USB is suspended.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_USBDEV
|
||||
void stm32_usbsuspend(struct usbdev_s *dev, bool resume)
|
||||
{
|
||||
uinfo("resume: %d\n", resume);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* CONFIG_STM32F7_OTGFS */
|
||||
@ -76,6 +76,9 @@
|
||||
#define GPIO_SCHED_RUNNING (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | \
|
||||
GPIO_PORTJ | GPIO_PIN0)
|
||||
|
||||
#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\
|
||||
GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
|
||||
|
||||
/****************************************************************************
|
||||
* Public data
|
||||
****************************************************************************/
|
||||
@ -147,6 +150,7 @@ void arch_sporadic_initialize(void);
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32F7_FMC
|
||||
void stm32_sdram_initialize(void);
|
||||
void stm32_disablefmc(void);
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user