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If LOWVECTORS is selected, then we need to clear the VBAR register. A bootloader may have left the VBAR in an bad state

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This commit is contained in:
Gregory Nutt 2014-04-03 13:09:30 -06:00
parent 11c7386dab
commit c9fc03d52f
4 changed files with 60 additions and 35 deletions
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4
arch/arm/src/armv7-a/arm_head.S
View File

@ -192,10 +192,10 @@ __start:
/* The MMU and caches should be disabled */
mrc p15, 0, r0, c1, c0, 0
mrc CP15_SCTLR(r0)
bic r0, r0, #(SCTLR_M | SCTLR_C)
bic r0, r0, #(SCTLR_I)
mcr p15, 0, r0, c1, c0, 0
mcr CP15_SCTLR(r0)
/* Clear the 16K level 1 page table */

30
arch/arm/src/armv7-a/sctlr.h
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@ -204,7 +204,8 @@
*/
/* Vector Base Address Register (VBAR) */
/* TODO: To be provided */
#define VBAR_MASK (0xffffffe0)
/* Monitor Vector Base Address Register (MVBAR) */
/* TODO: To be provided */
@ -313,6 +314,33 @@ static inline void cp15_wrsctlr(unsigned int sctlr)
);
}
/* Read/write the vector base address register (VBAR) */
static inline unsigned int cp15_rdvbar(void)
{
unsigned int sctlr;
__asm__ __volatile__
(
"\tmrc p15, 0, %0, c12, c0, 0\n"
: "=r" (sctlr)
:
: "memory"
);
return sctlr;
}
static inline void cp15_wrvbar(unsigned int sctlr)
{
__asm__ __volatile__
(
"\tmcr p15, 0, %0, c12, c0, 0\n"
:
: "r" (sctlr)
: "memory"
);
}
#endif /* __ASSEMBLY__ */
/****************************************************************************

15
arch/arm/src/sama5/sam_irq.c
View File

@ -56,6 +56,7 @@
#include "mmu.h"
#include "cache.h"
#include "sctlr.h"
#include "chip/sam_aic.h"
#include "chip/sam_matrix.h"
#include "chip/sam_aximx.h"
@ -121,7 +122,7 @@ static void sam_dumpaic(const char *msg, int irq)
lldbg(" SSR: %08x SMR: %08x SVR: %08x IVR: %08x\n",
getreg32(SAM_AIC_SSR), getreg32(SAM_AIC_SMR),
getreg32(SAM_AIC_SVR), getreg32(SAM_AIC_IVR));
lldbg(" FVR: %08x ISR: %08x\n",
lldbg(" FVR: %08x ISR: %08x\n",
getreg32(SAM_AIC_FVR), getreg32(SAM_AIC_ISR));
lldbg(" IPR: %08x %08x %08x %08x\n",
getreg32(SAM_AIC_IPR0), getreg32(SAM_AIC_IPR1),
@ -129,9 +130,9 @@ static void sam_dumpaic(const char *msg, int irq)
lldbg(" IMR: %08x CISR: %08x SPU: %08x FFSR: %08x\n",
getreg32(SAM_AIC_IMR), getreg32(SAM_AIC_CISR),
getreg32(SAM_AIC_SPU), getreg32(SAM_AIC_FFSR));
lldbg(" DCR: %08x WPMR: %08x WPMR: %08x\n",
lldbg(" DCR: %08x WPMR: %08x WPSR: %08x\n",
getreg32(SAM_AIC_DCR), getreg32(SAM_AIC_WPMR),
getreg32(SAM_AIC_WPMR));
getreg32(SAM_AIC_WPSR));
irqrestore(flags);
}
#else
@ -308,9 +309,13 @@ void up_irqinitialize(void)
putreg32(AIC_WPMR_WPKEY | AIC_WPMR_WPEN, SAM_AIC_WPMR);
#if defined(CONFIG_ARCH_LOWVECTORS)
/* Disable MATRIX write protection */
/* Set the vector base address register to zero */
cp15_wrvbar(0);
#if 0 /* Disabled on reset */
/* Disable MATRIX write protection */
putreg32(MATRIX_WPMR_WPKEY, SAM_MATRIX_WPMR);
#endif
@ -348,9 +353,9 @@ void up_irqinitialize(void)
cp15_invalidate_dcache(0, vectorsize);
mmu_invalidate_region(0, vectorsize);
#if 0 /* Disabled on reset */
/* Restore MATRIX write protection */
#if 0 /* Disabled on reset */
putreg32(MATRIX_WPMR_WPKEY | MATRIX_WPMR_WPEN, SAM_MATRIX_WPMR);
#endif

46
configs/sama5d3-xplained/README.txt
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@ -546,6 +546,7 @@ Load NuttX with U-Boot on AT91 boards
U-Boot> fatload mmc 0 0x22000000 uimage
reading uimage
97744 bytes read in 21 ms (4.4 MiB/s)
U-Boot> bootm 0x22000000
## Booting kernel from Legacy Image at 0x22000000 ...
Image Name: nuttx
@ -560,18 +561,21 @@ Load NuttX with U-Boot on AT91 boards
This, however, appears to be a usable workaround:
U-Boot> fatload mmc 0 0x20008000 nuttx.bin
mci: setting clock 257812 Hz, block size 512
mci: setting clock 257812 Hz, block size 512
mci: setting clock 257812 Hz, block size 512
gen_atmel_mci: CMDR 00001048 ( 8) ARGR 000001aa (SR: 0c100025) Command Time Out
mci: setting clock 257812 Hz, block size 512
mci: setting clock 22000000 Hz, block size 512
reading nuttx.bin
108076 bytes read in 23 ms (4.5 MiB/s)
U-Boot> go 0x20008040
## Starting application at 0x20008040 ...
os_start: Entry
U-Boot> fatload mmc 0 0x20008000 nuttx.bin
mci: setting clock 257812 Hz, block size 512
mci: setting clock 257812 Hz, block size 512
mci: setting clock 257812 Hz, block size 512
gen_atmel_mci: CMDR 00001048 ( 8) ARGR 000001aa (SR: 0c100025) Command Time Out
mci: setting clock 257812 Hz, block size 512
mci: setting clock 22000000 Hz, block size 512
reading nuttx.bin
108076 bytes read in 23 ms (4.5 MiB/s)
U-Boot> go 0x20008040
## Starting application at 0x20008040 ...
NuttShell (NSH) NuttX-7.2
nsh>
Loading through network
@ -2729,26 +2733,14 @@ Configurations
STATUS:
See the To-Do list below
I2C
2014-9-12: The I2C tool, however, seems to work well. It succesfully
enumerates the devices on the bus and successfully exchanges a few
commands. The real test of the come later when a real I2C device is
integrated.
To-Do List
==========
1) Currently the SAMA5Dx is running at 396MHz in these configurations. This
is because the timing for the PLLs, NOR FLASH, and SDRAM came from the
Atmel NoOS sample code which runs at that rate. The SAMA5Dx is capable
of running at 536MHz, however. The setup for that configuration exists
in the BareBox assembly language setup and should be incorporated.
2) Neither USB OHCI nor EHCI support Isochronous endpoints. Interrupt
1) Neither USB OHCI nor EHCI support Isochronous endpoints. Interrupt
endpoint support in the EHCI driver is untested (but works in similar
EHCI drivers).
3) HSCMI TX DMA support is currently commented out.
2) HSCMI TX DMA support is currently commented out.
7) GMAC has only been tested on a 10/100Base-T network. I don't have a
3) GMAC has only been tested on a 10/100Base-T network. I don't have a
1000Base-T network to support additional testing.