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Fix typo is STM32 ADC driver for F2 and F4: ADC not ACD

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This commit is contained in:
Gregory Nutt 2013-05-08 21:45:46 -06:00
parent 44dc7c713b
commit c9fcc7eef4
3 changed files with 17 additions and 15 deletions
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2
ChangeLog
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@ -4695,3 +4695,5 @@
From Ken Pettit (2013-5-7).
* arch/arm/src/lpc17xx/lpc17_i2c.c: Fix for lpc17xx i2c single byte read
timeout error problem from M.Kannan (2013-5-8).
* arch/arm/src/stm32/stm32_adc.c: Typo in F2/F4 specific logic: ACD_
instead of ADC_. From Ken Pettit (2013-5-8).

24
arch/arm/src/stm32/chip/stm32f30xxx_adc.h
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@ -243,22 +243,22 @@
/* ADC configuration register */
#define ADC_CFGR_DMACFG (1 << 1) /* Bit 0: Direct memory access configuration */
#define ACD_CFGR_RES_SHIFT (3) /* Bits 3-4: Data resolution */
#define ACD_CFGR_RES_MASK (3 << ACD_CFGR_RES_SHIFT)
# define ACD_CFGR_RES_12BIT (0 << ACD_CFGR_RES_SHIFT) /* 15 ADCCLK clyes */
# define ACD_CFGR_RES_10BIT (1 << ACD_CFGR_RES_SHIFT) /* 13 ADCCLK clyes */
# define ACD_CFGR_RES_8BIT (2 << ACD_CFGR_RES_SHIFT) /* 11 ADCCLK clyes */
# define ACD_CFGR_RES_6BIT (3 << ACD_CFGR_RES_SHIFT) /* 9 ADCCLK clyes */
#define ADC_CFGR_RES_SHIFT (3) /* Bits 3-4: Data resolution */
#define ADC_CFGR_RES_MASK (3 << ADC_CFGR_RES_SHIFT)
# define ADC_CFGR_RES_12BIT (0 << ADC_CFGR_RES_SHIFT) /* 15 ADCCLK clyes */
# define ADC_CFGR_RES_10BIT (1 << ADC_CFGR_RES_SHIFT) /* 13 ADCCLK clyes */
# define ADC_CFGR_RES_8BIT (2 << ADC_CFGR_RES_SHIFT) /* 11 ADCCLK clyes */
# define ADC_CFGR_RES_6BIT (3 << ADC_CFGR_RES_SHIFT) /* 9 ADCCLK clyes */
#define ADC_CFGR_ALIGN (1 << 5) /* Bit 5: Data Alignment */
#define ADC_CFGR_EXTSEL_SHIFT (6) /* Bits 6-9: External Event Select for regular group */
#define ADC_CFGR_EXTSEL_MASK (15 << ADC_CFGR_EXTSEL_SHIFT)
# define ADC_CFGR_EXTSEL(event) ((event) << ADC_CFGR_EXTSEL_SHIFT) /* Event = 0..15 */
#define ACD_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */
#define ACD_CFGR_EXTEN_MASK (3 << ACD_CFGR_EXTEN_SHIFT)
# define ACD_CFGR_EXTEN_NONE (0 << ACD_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */
# define ACD_CFGR_EXTEN_RISING (1 << ACD_CFGR_EXTEN_SHIFT) /* Trigger detection on the rising edge */
# define ACD_CFGR_EXTEN_FALLING (2 << ACD_CFGR_EXTEN_SHIFT) /* Trigger detection on the falling edge */
# define ACD_CFGR_EXTEN_BOTH (3 << ACD_CFGR_EXTEN_SHIFT) /* Trigger detection on both edges */
#define ADC_CFGR_EXTEN_SHIFT (10) /* Bits 10-11: External trigger/polarity selection regular channels */
#define ADC_CFGR_EXTEN_MASK (3 << ADC_CFGR_EXTEN_SHIFT)
# define ADC_CFGR_EXTEN_NONE (0 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection disabled */
# define ADC_CFGR_EXTEN_RISING (1 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the rising edge */
# define ADC_CFGR_EXTEN_FALLING (2 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on the falling edge */
# define ADC_CFGR_EXTEN_BOTH (3 << ADC_CFGR_EXTEN_SHIFT) /* Trigger detection on both edges */
#define ADC_CFGR_OVRMOD (1 << 12) /* Bit 12: Overrun Mode */
#define ADC_CFGR_CONT (1 << 13) /* Bit 13: Continuous mode for regular conversions */
#define ADC_CFGR_AUTDLY (1 << 14) /* Bit 14: Delayed conversion mode */

6
arch/arm/src/stm32/stm32_adc.c
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@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_adc.c
*
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
* Copyright (C) 2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* Diego Sanchez <dsanchez@nx-engineering.com>
*
@ -1043,7 +1043,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
/* Set the resolution of the conversion */
regval |= ACD_CR1_RES_12BIT;
regval |= ADC_CR1_RES_12BIT;
#endif
adc_putreg(priv, STM32_ADC_CR1_OFFSET, regval);
@ -1063,7 +1063,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
#if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
/* External trigger enable for regular channels */
regval |= ACD_CR2_EXTEN_RISING;
regval |= ADC_CR2_EXTEN_RISING;
#endif
adc_putreg(priv, STM32_ADC_CR2_OFFSET, regval);