SAMV7: Add SPI header files and driver
This commit is contained in:
Gregory Nutt
parent
f8c73c3499
commit
ca48fbfc4a
@ -484,3 +484,44 @@ config SAMV7_GPIOE_IRQ
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endif # SAMV7_GPIO_IRQ
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endif # ARCH_CHIP_SAMV7
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if SAMV7_SPI0 || SAMV7_SPI1
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menu "SAMV7 SPI device driver options"
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config SAMV7_SPI_DMA
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bool "SPI DMA"
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default n
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depends on SAMV7_XDMAC
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---help---
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Use DMA to improve SPI transfer performance.
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config SAMV7_SPI_DMATHRESHOLD
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int "SPI DMA threshold"
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default 4
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depends on SAMV7_SPI_DMA
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---help---
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When SPI DMA is enabled, small DMA transfers will still be performed
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by polling logic. But we need a threshold value to determine what
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is small. That value is provided by SAMV7_SPI_DMATHRESHOLD.
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config SAMV7_SPI_DMADEBUG
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bool "SPI DMA transfer debug"
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depends on SAMV7_SPI_DMA && DEBUG && DEBUG_DMA
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default n
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---help---
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Enable special debug instrumentation analyze SPI DMA data transfers.
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This logic is as non-invasive as possible: It samples DMA
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registers at key points in the data transfer and then dumps all of
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the registers at the end of the transfer.
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config SAMV7_SPI_REGDEBUG
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bool "SPI Register level debug"
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depends on DEBUG
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default n
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---help---
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Output detailed register-level SPI device debug information.
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Requires also DEBUG.
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endmenu # SAMV7 SPI device driver options
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endif # SAMV7_SPI0 || SAMV7_SPI1
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@ -118,3 +118,9 @@ endif
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ifeq ($(CONFIG_SAMV7_XDMAC),y)
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CHIP_CSRCS += sam_xdmac.c
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endif
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ifeq ($(CONFIG_SAMV7_SPI0),y)
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CHIP_CSRCS += sam_spi.c
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else ifeq ($(CONFIG_SAMV7_SPI1),y)
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CHIP_CSRCS += sam_spi.c
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endif
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229
arch/arm/src/samv7/chip/sam_spi.h
Normal file
229
arch/arm/src/samv7/chip/sam_spi.h
Normal file
@ -0,0 +1,229 @@
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/****************************************************************************************
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* arch/arm/src/samv7/chip/sam_spi.h
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* Serial Peripheral Interface (SPI) definitions for the SAMV71
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SPI_H
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#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SPI_H
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/****************************************************************************************
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* Included Files
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****************************************************************************************/
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#include <nuttx/config.h>
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#include <arch/samv7/chip.h>
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#include "chip/sam_memorymap.h"
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#if SAMV7_NSPI > 0
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/****************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************/
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/* General definitions ******************************************************************/
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#define SAM_SPI_NCS 4 /* Four chip selects */
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/* SPI register offsets *****************************************************************/
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#define SAM_SPI_CR_OFFSET 0x0000 /* Control Register */
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#define SAM_SPI_MR_OFFSET 0x0004 /* Mode Register */
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#define SAM_SPI_RDR_OFFSET 0x0008 /* Receive Data Register */
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#define SAM_SPI_TDR_OFFSET 0x000c /* Transmit Data Register */
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#define SAM_SPI_SR_OFFSET 0x0010 /* Status Register */
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#define SAM_SPI_IER_OFFSET 0x0014 /* Interrupt Enable Register */
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#define SAM_SPI_IDR_OFFSET 0x0018 /* Interrupt Disable Register */
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#define SAM_SPI_IMR_OFFSET 0x001c /* Interrupt Mask Register */
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/* 0x20-0x2c: Reserved */
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#define SAM_SPI_CSR0_OFFSET 0x0030 /* Chip Select Register 0 */
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#define SAM_SPI_CSR1_OFFSET 0x0034 /* Chip Select Register 1 */
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#define SAM_SPI_CSR2_OFFSET 0x0038 /* Chip Select Register 2 */
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#define SAM_SPI_CSR3_OFFSET 0x003c /* Chip Select Register 3 */
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/* 0x40-0xe0: Reserved */
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#define SAM_SPI_WPCR_OFFSET 0x00e4 /* Write Protection Control Register */
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#define SAM_SPI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */
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/* 0xec-0xfc: Reserved */
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/* SPI register addresses ***************************************************************/
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#define SAM_SPI0_CR (SAM_SPI0_BASE+SAM_SPI_CR_OFFSET) /* Control Register */
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#define SAM_SPI0_MR (SAM_SPI0_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */
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#define SAM_SPI0_RDR (SAM_SPI0_BASE+SAM_SPI_RDR_OFFSET) /* Receive Data Register */
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#define SAM_SPI0_TDR (SAM_SPI0_BASE+SAM_SPI_TDR_OFFSET) /* Transmit Data Register */
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#define SAM_SPI0_SR (SAM_SPI0_BASE+SAM_SPI_SR_OFFSET) /* Status Register */
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#define SAM_SPI0_IER (SAM_SPI0_BASE+SAM_SPI_IER_OFFSET) /* Interrupt Enable Register */
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#define SAM_SPI0_IDR (SAM_SPI0_BASE+SAM_SPI_IDR_OFFSET) /* Interrupt Disable Register */
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#define SAM_SPI0_IMR (SAM_SPI0_BASE+SAM_SPI_IMR_OFFSET) /* Interrupt Mask Register */
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#define SAM_SPI0_CSR0 (SAM_SPI0_BASE+SAM_SPI_CSR0_OFFSET) /* Chip Select Register 0 */
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#define SAM_SPI0_CSR1 (SAM_SPI0_BASE+SAM_SPI_CSR1_OFFSET) /* Chip Select Register 1 */
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#define SAM_SPI0_CSR2 (SAM_SPI0_BASE+SAM_SPI_CSR2_OFFSET) /* Chip Select Register 2 */
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#define SAM_SPI0_CSR3 (SAM_SPI0_BASE+SAM_SPI_CSR3_OFFSET) /* Chip Select Register 3 */
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#define SAM_SPI0_WPCR (SAM_SPI0_BASE+SAM_SPI_WPCR_OFFSET) /* Write Protection Control Register */
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#define SAM_SPI0_WPSR (SAM_SPI0_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */
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#if SAMV7_NSPI > 1
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# define SAM_SPI1_CR (SAM_SPI1_BASE+SAM_SPI_CR_OFFSET) /* Control Register */
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# define SAM_SPI1_MR (SAM_SPI1_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */
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# define SAM_SPI1_RDR (SAM_SPI1_BASE+SAM_SPI_RDR_OFFSET) /* Receive Data Register */
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# define SAM_SPI1_TDR (SAM_SPI1_BASE+SAM_SPI_TDR_OFFSET) /* Transmit Data Register */
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# define SAM_SPI1_SR (SAM_SPI1_BASE+SAM_SPI_SR_OFFSET) /* Status Register */
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# define SAM_SPI1_IER (SAM_SPI1_BASE+SAM_SPI_IER_OFFSET) /* Interrupt Enable Register */
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# define SAM_SPI1_IDR (SAM_SPI1_BASE+SAM_SPI_IDR_OFFSET) /* Interrupt Disable Register */
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# define SAM_SPI1_IMR (SAM_SPI1_BASE+SAM_SPI_IMR_OFFSET) /* Interrupt Mask Register */
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# define SAM_SPI1_CSR0 (SAM_SPI1_BASE+SAM_SPI_CSR0_OFFSET) /* Chip Select Register 0 */
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# define SAM_SPI1_CSR1 (SAM_SPI1_BASE+SAM_SPI_CSR1_OFFSET) /* Chip Select Register 1 */
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# define SAM_SPI1_CSR2 (SAM_SPI1_BASE+SAM_SPI_CSR2_OFFSET) /* Chip Select Register 2 */
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# define SAM_SPI1_CSR3 (SAM_SPI1_BASE+SAM_SPI_CSR3_OFFSET) /* Chip Select Register 3 */
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# define SAM_SPI1_WPCR (SAM_SPI1_BASE+SAM_SPI_WPCR_OFFSET) /* Write Protection Control Register */
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# define SAM_SPI1_WPSR (SAM_SPI1_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */
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#endif
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/* SPI register bit definitions *********************************************************/
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/* SPI Control Register */
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#define SPI_CR_SPIEN (1 << 0) /* Bit 0: SPI Enable */
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#define SPI_CR_SPIDIS (1 << 1) /* Bit 1: SPI Disable */
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#define SPI_CR_SWRST (1 << 7) /* Bit 7: SPI Software Reset */
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#define SPI_CR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
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/* SPI Mode Register */
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#define SPI_MR_MSTR (1 << 0) /* Bit 0: Master/Slave Mode */
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#define SPI_MR_PS (1 << 1) /* Bit 1: Peripheral Select */
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#define SPI_MR_PCSDEC (1 << 2) /* Bit 2: Chip Select Decode */
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#define SPI_MR_MODFDIS (1 << 4) /* Bit 4: Mode Fault Detection */
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#define SPI_MR_WDRBT (1 << 5) /* Bit 5: Wait Data Read Before Transfer */
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#define SPI_MR_LLB (1 << 7) /* Bit 7: Local Loopback Enable */
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#define SPI_MR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
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#define SPI_MR_PCS_MASK (15 << SPI_MR_PCS_SHIFT)
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# define SPI_MR_PCS0 (0 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */
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# define SPI_MR_PCS1 (1 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */
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# define SPI_MR_PCS2 (3 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */
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# define SPI_MR_PCS3 (7 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */
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#define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */
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#define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT)
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# define SPI_MR_DLYBCS(n) ((uint32_t)(n) << SPI_MR_DLYBCS_SHIFT)
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/* SPI Receive Data Register */
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#define SPI_RDR_RD_SHIFT (0) /* Bits 0-15: Receive Data */
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#define SPI_RDR_RD_MASK (0xffff << SPI_RDR_RD_SHIFT)
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#define SPI_RDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
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#define SPI_RDR_PCS_MASK (15 << SPI_RDR_PCS_SHIFT)
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# define SPI_RDR_PCS0 (0 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */
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# define SPI_RDR_PCS1 (1 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */
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# define SPI_RDR_PCS2 (3 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */
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# define SPI_RDR_PCS3 (7 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */
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/* SPI Transmit Data Register */
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#define SPI_TDR_TD_SHIFT (0) /* Bits 0-15: Transmit Data */
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#define SPI_TDR_TD_MASK (0xffff << SPI_TDR_TD_SHIFT)
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#define SPI_TDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */
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#define SPI_TDR_PCS_MASK (15 << SPI_TDR_PCS_SHIFT)
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# define SPI_TDR_PCS0 (0 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */
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# define SPI_TDR_PCS1 (1 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */
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# define SPI_TDR_PCS2 (3 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */
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# define SPI_TDR_PCS3 (7 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */
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#define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
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/* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register,
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* and SPI Interrupt Mask Register (common bit fields)
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*/
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#define SPI_INT_RDRF (1 << 0) /* Bit 0: Receive Data Register Full Interrupt */
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#define SPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */
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#define SPI_INT_MODF (1 << 2) /* Bit 2: Mode Fault Error Interrupt */
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#define SPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */
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#define SPI_INT_NSSR (1 << 8) /* Bit 8: NSS Rising Interrupt */
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#define SPI_INT_TXEMPTY (1 << 9) /* Bit 9: Transmission Registers Empty Interrupt */
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#define SPI_INT_UNDES (1 << 10) /* Bit 10: Underrun Error Status Interrupt (slave) */
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#define SPI_SR_SPIENS (1 << 16) /* Bit 16: SPI Enable Status (SR only) */
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/* SPI Chip Select Registers 0-3 */
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#define SPI_CSR_CPOL (1 << 0) /* Bit 0: Clock Polarity */
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#define SPI_CSR_NCPHA (1 << 1) /* Bit 1: Clock Phase */
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#define SPI_CSR_CSNAAT (1 << 2) /* Bit 2: Chip Select Not Active After Transfer */
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#define SPI_CSR_CSAAT (1 << 3) /* Bit 3: Chip Select Active After Transfer */
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#define SPI_CSR_BITS_SHIFT (4) /* Bits 4-7: Bits Per Transfer */
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#define SPI_CSR_BITS_MASK (15 << SPI_CSR_BITS_SHIFT)
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# define SPI_CSR_BITS(n) (((n)-8) << SPI_CSR_BITS_SHIFT) /* n, n=8-16 */
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# define SPI_CSR_BITS8 (0 << SPI_CSR_BITS_SHIFT) /* 8 */
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# define SPI_CSR_BITS9 (1 << SPI_CSR_BITS_SHIFT) /* 9 */
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# define SPI_CSR_BITS10 (2 << SPI_CSR_BITS_SHIFT) /* 10 */
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# define SPI_CSR_BITS11 (3 << SPI_CSR_BITS_SHIFT) /* 11 */
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# define SPI_CSR_BITS12 (4 << SPI_CSR_BITS_SHIFT) /* 12 */
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# define SPI_CSR_BITS13 (5 << SPI_CSR_BITS_SHIFT) /* 13 */
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# define SPI_CSR_BITS14 (6 << SPI_CSR_BITS_SHIFT) /* 14 */
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# define SPI_CSR_BITS15 (7 << SPI_CSR_BITS_SHIFT) /* 15 */
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# define SPI_CSR_BITS16 (8 << SPI_CSR_BITS_SHIFT) /* 16 */
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#define SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */
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#define SPI_CSR_SCBR_MASK (0xff << SPI_CSR_SCBR_SHIFT)
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# define SPI_CSR_SCBR(n) ((uint32_t)(n) << SPI_CSR_SCBR_SHIFT)
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#define SPI_CSR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before SPCK */
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#define SPI_CSR_DLYBS_MASK (0xff << SPI_CSR_DLYBS_SHIFT)
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# define SPI_CSR_DLYBS(n) ((uint32_t)(n) << SPI_CSR_DLYBS_SHIFT)
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#define SPI_CSR_DLYBCT_SHIFT (24) /* Bits 24-31: Delay Between Consecutive Transfers */
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#define SPI_CSR_DLYBCT_MASK (0xff << SPI_CSR_DLYBCT_SHIFT)
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# define SPI_CSR_DLYBCT(n) ((uint32_t)(n) << SPI_CSR_DLYBCT_SHIFT)
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/* SPI Write Protection Control Register */
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#define SPI_WPCR_WPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */
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#define SPI_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */
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#define SPI_WPCR_WPKEY_MASK (0x00ffffff << SPI_WPCR_WPKEY_SHIFT)
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# define SPI_WPCR_WPKEY (0x00535049 << SPI_WPCR_WPKEY_SHIFT)
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/* SPI Write Protection Status Register */
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#define SPI_WPSR_WPVS (1 << 0) /* Bit 0: SPI Write Protection Violation Status */
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#define SPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */
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#define SPI_WPSR_WPVSRC_MASK (0xff << SPI_WPSR_WPVSRC_SHIFT)
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/****************************************************************************************
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* Public Types
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****************************************************************************************/
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/****************************************************************************************
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* Public Data
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****************************************************************************************/
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/****************************************************************************************
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* Public Functions
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****************************************************************************************/
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#endif /* SAMV7_NSPI > 0 */
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#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SPI_H */
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1941
arch/arm/src/samv7/sam_spi.c
Normal file
1941
arch/arm/src/samv7/sam_spi.c
Normal file
File diff suppressed because it is too large
Load Diff
244
arch/arm/src/samv7/sam_spi.h
Normal file
244
arch/arm/src/samv7/sam_spi.h
Normal file
@ -0,0 +1,244 @@
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/****************************************************************************
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* arch/arm/src/samv7/sam_spi.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
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* distribution.
|
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* 3. Neither the name NuttX nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMV7_SAM_SPI_H
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#define __ARCH_ARM_SRC_SAMV7_SAM_SPI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "chip.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* The SPI port number used as an input to up_spiinitialize encodes
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* information about the SPI controller (0 or 1) and the SPI chip select
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* (0-3).
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*
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* NOTE that this is this is backward compatible with older implementations
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* that support only SPI0 and provide only the chip select number to
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* up_spiinitialize().
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*/
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||||
|
||||
#define __SPI_CS_SHIFT (0) /* Bits 0-1: SPI chip select number */
|
||||
#define __SPI_CS_MASK (3 << __SPI_CS_SHIFT)
|
||||
# define __SPI_CS0 (0 << __SPI_CS_SHIFT)
|
||||
# define __SPI_CS1 (1 << __SPI_CS_SHIFT)
|
||||
# define __SPI_CS2 (2 << __SPI_CS_SHIFT)
|
||||
# define __SPI_CS3 (3 << __SPI_CS_SHIFT)
|
||||
#define __SPI_SPI_SHIFT (2) /* Bit 2: SPI controller number */
|
||||
#define __SPI_SPI_MASK (1 << __SPI_SPI_SHIFT)
|
||||
# define __SPI_SPI0 (0 << __SPI_SPI_SHIFT) /* SPI0 */
|
||||
# define __SPI_SPI1 (1 << __SPI_SPI_SHIFT) /* SPI1 */
|
||||
|
||||
#define SPI0_CS0 (__SPI_SPI0 | __SPI_CS0)
|
||||
#define SPI0_CS1 (__SPI_SPI0 | __SPI_CS1)
|
||||
#define SPI0_CS2 (__SPI_SPI0 | __SPI_CS2)
|
||||
#define SPI0_CS3 (__SPI_SPI0 | __SPI_CS3)
|
||||
|
||||
#define SPI1_CS0 (__SPI_SPI1 | __SPI_CS0)
|
||||
#define SPI1_CS1 (__SPI_SPI1 | __SPI_CS1)
|
||||
#define SPI1_CS2 (__SPI_SPI1 | __SPI_CS2)
|
||||
#define SPI1_CS3 (__SPI_SPI1 | __SPI_CS3)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_spi[0|1]select, sam_spi[0|1]status, and sam_spi[0|1]cmddata
|
||||
*
|
||||
* Description:
|
||||
* These external functions must be provided by board-specific logic.
|
||||
* They include:
|
||||
*
|
||||
* o sam_spi[0|1]select is a functions tomanage the board-specific chip
|
||||
* selects
|
||||
* o sam_spi[0|1]status and sam_spi[0|1]cmddata: Implementations of the
|
||||
* status and cmddata methods of the SPI interface defined by struct
|
||||
* spi_ops_ (see include/nuttx/spi/spi.h). All other methods including
|
||||
* up_spiinitialize()) are provided by common SAM3/4 logic.
|
||||
*
|
||||
* To use this common SPI logic on your board:
|
||||
*
|
||||
* 1. Provide logic in sam_boardinitialize() to configure SPI chip select
|
||||
* pins.
|
||||
* 2. Provide sam_spi[0|1]select() and sam_spi[0|1]status() functions in
|
||||
* our board-specific logic. These functions will perform chip selection
|
||||
* and status operations using PIOs in the way your board is configured.
|
||||
* 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
|
||||
* sam_spi[0|1]cmddata() functions in your board-specific logic. This
|
||||
* function will perform cmd/data selection operations using PIOs in
|
||||
* the way your board is configured.
|
||||
* 3. Add a call to up_spiinitialize() in your low level application
|
||||
* initialization logic
|
||||
* 4. The handle returned by up_spiinitialize() may then be used to bind the
|
||||
* SPI driver to higher level logic (e.g., calling
|
||||
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
|
||||
* the SPI MMC/SD driver).
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMV7_SPI0
|
||||
struct spi_dev_s;
|
||||
enum spi_dev_e;
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_spi[0|1]select
|
||||
*
|
||||
* Description:
|
||||
* PIO chip select pins may be programmed by the board specific logic in
|
||||
* one of two different ways. First, the pins may be programmed as SPI
|
||||
* peripherals. In that case, the pins are completely controlled by the
|
||||
* SPI driver. This method still needs to be provided, but it may be only
|
||||
* a stub.
|
||||
*
|
||||
* An alternative way to program the PIO chip select pins is as a normal
|
||||
* PIO output. In that case, the automatic control of the CS pins is
|
||||
* bypassed and this function must provide control of the chip select.
|
||||
* NOTE: In this case, the PIO output pin does *not* have to be the
|
||||
* same as the NPCS pin normal associated with the chip select number.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - SPI device info
|
||||
* devid - Identifies the (logical) device
|
||||
* selected - TRUE:Select the device, FALSE:De-select the device
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMV7_SPI0
|
||||
void sam_spi0select(enum spi_dev_e devid, bool selected);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMV7_SPI1
|
||||
void sam_spi1select(enum spi_dev_e devid, bool selected);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_spi[0|1]status
|
||||
*
|
||||
* Description:
|
||||
* Return status information associated with the SPI device.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - SPI device info
|
||||
* devid - Identifies the (logical) device
|
||||
*
|
||||
* Returned Values:
|
||||
* Bit-encoded SPI status (see include/nuttx/spi/spi.h.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMV7_SPI0
|
||||
uint8_t sam_spi0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMV7_SPI1
|
||||
uint8_t sam_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_spi[0|1]cmddata
|
||||
*
|
||||
* Description:
|
||||
* Some SPI devices require an additional control to determine if the SPI
|
||||
* data being sent is a command or is data. If CONFIG_SPI_CMDDATA then
|
||||
* this function will be called to different be command and data transfers.
|
||||
*
|
||||
* This is often needed, for example, by LCD drivers. Some LCD hardware
|
||||
* may be configured to use 9-bit data transfers with the 9th bit
|
||||
* indicating command or data. That same hardware may be configurable,
|
||||
* instead, to use 8-bit data but to require an additional, board-
|
||||
* specific PIO control to distinguish command and data. This function
|
||||
* would be needed in that latter case.
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - SPI device info
|
||||
* devid - Identifies the (logical) device
|
||||
*
|
||||
* Returned Values:
|
||||
* Zero on success; a negated errno on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SPI_CMDDATA
|
||||
#ifdef CONFIG_SAMV7_SPI0
|
||||
int sam_spi0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
#endif
|
||||
#ifdef CONFIG_SAMV7_SPI1
|
||||
int sam_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
#endif
|
||||
#endif
|
||||
#endif /* CONFIG_SAMV7_SPI0 */
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_SAMV7_SAM_SPI_H */
|
||||
Loading…
Reference in New Issue
Block a user