From ca48fbfc4a18bceadfd0aea14578b95acdc20e57 Mon Sep 17 00:00:00 2001 From: Gregory Nutt Date: Thu, 12 Mar 2015 09:12:37 -0600 Subject: [PATCH] SAMV7: Add SPI header files and driver --- arch/arm/src/samv7/Kconfig | 41 + arch/arm/src/samv7/Make.defs | 6 + arch/arm/src/samv7/chip/sam_spi.h | 229 ++++ arch/arm/src/samv7/sam_spi.c | 1941 +++++++++++++++++++++++++++++ arch/arm/src/samv7/sam_spi.h | 244 ++++ 5 files changed, 2461 insertions(+) create mode 100644 arch/arm/src/samv7/chip/sam_spi.h create mode 100644 arch/arm/src/samv7/sam_spi.c create mode 100644 arch/arm/src/samv7/sam_spi.h diff --git a/arch/arm/src/samv7/Kconfig b/arch/arm/src/samv7/Kconfig index 5215ad1cb9..f71ab452a8 100644 --- a/arch/arm/src/samv7/Kconfig +++ b/arch/arm/src/samv7/Kconfig @@ -484,3 +484,44 @@ config SAMV7_GPIOE_IRQ endif # SAMV7_GPIO_IRQ endif # ARCH_CHIP_SAMV7 + +if SAMV7_SPI0 || SAMV7_SPI1 + +menu "SAMV7 SPI device driver options" + +config SAMV7_SPI_DMA + bool "SPI DMA" + default n + depends on SAMV7_XDMAC + ---help--- + Use DMA to improve SPI transfer performance. + +config SAMV7_SPI_DMATHRESHOLD + int "SPI DMA threshold" + default 4 + depends on SAMV7_SPI_DMA + ---help--- + When SPI DMA is enabled, small DMA transfers will still be performed + by polling logic. But we need a threshold value to determine what + is small. That value is provided by SAMV7_SPI_DMATHRESHOLD. + +config SAMV7_SPI_DMADEBUG + bool "SPI DMA transfer debug" + depends on SAMV7_SPI_DMA && DEBUG && DEBUG_DMA + default n + ---help--- + Enable special debug instrumentation analyze SPI DMA data transfers. + This logic is as non-invasive as possible: It samples DMA + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. + +config SAMV7_SPI_REGDEBUG + bool "SPI Register level debug" + depends on DEBUG + default n + ---help--- + Output detailed register-level SPI device debug information. + Requires also DEBUG. + +endmenu # SAMV7 SPI device driver options +endif # SAMV7_SPI0 || SAMV7_SPI1 diff --git a/arch/arm/src/samv7/Make.defs b/arch/arm/src/samv7/Make.defs index 763953b5e6..6083349358 100644 --- a/arch/arm/src/samv7/Make.defs +++ b/arch/arm/src/samv7/Make.defs @@ -118,3 +118,9 @@ endif ifeq ($(CONFIG_SAMV7_XDMAC),y) CHIP_CSRCS += sam_xdmac.c endif + +ifeq ($(CONFIG_SAMV7_SPI0),y) +CHIP_CSRCS += sam_spi.c +else ifeq ($(CONFIG_SAMV7_SPI1),y) +CHIP_CSRCS += sam_spi.c +endif diff --git a/arch/arm/src/samv7/chip/sam_spi.h b/arch/arm/src/samv7/chip/sam_spi.h new file mode 100644 index 0000000000..44ec25e875 --- /dev/null +++ b/arch/arm/src/samv7/chip/sam_spi.h @@ -0,0 +1,229 @@ +/**************************************************************************************** + * arch/arm/src/samv7/chip/sam_spi.h + * Serial Peripheral Interface (SPI) definitions for the SAMV71 + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SPI_H +#define __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SPI_H + +/**************************************************************************************** + * Included Files + ****************************************************************************************/ + +#include +#include + +#include "chip/sam_memorymap.h" + +#if SAMV7_NSPI > 0 + +/**************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************/ +/* General definitions ******************************************************************/ + +#define SAM_SPI_NCS 4 /* Four chip selects */ + +/* SPI register offsets *****************************************************************/ + +#define SAM_SPI_CR_OFFSET 0x0000 /* Control Register */ +#define SAM_SPI_MR_OFFSET 0x0004 /* Mode Register */ +#define SAM_SPI_RDR_OFFSET 0x0008 /* Receive Data Register */ +#define SAM_SPI_TDR_OFFSET 0x000c /* Transmit Data Register */ +#define SAM_SPI_SR_OFFSET 0x0010 /* Status Register */ +#define SAM_SPI_IER_OFFSET 0x0014 /* Interrupt Enable Register */ +#define SAM_SPI_IDR_OFFSET 0x0018 /* Interrupt Disable Register */ +#define SAM_SPI_IMR_OFFSET 0x001c /* Interrupt Mask Register */ + /* 0x20-0x2c: Reserved */ +#define SAM_SPI_CSR0_OFFSET 0x0030 /* Chip Select Register 0 */ +#define SAM_SPI_CSR1_OFFSET 0x0034 /* Chip Select Register 1 */ +#define SAM_SPI_CSR2_OFFSET 0x0038 /* Chip Select Register 2 */ +#define SAM_SPI_CSR3_OFFSET 0x003c /* Chip Select Register 3 */ + /* 0x40-0xe0: Reserved */ +#define SAM_SPI_WPCR_OFFSET 0x00e4 /* Write Protection Control Register */ +#define SAM_SPI_WPSR_OFFSET 0x00e8 /* Write Protection Status Register */ + /* 0xec-0xfc: Reserved */ + +/* SPI register addresses ***************************************************************/ + +#define SAM_SPI0_CR (SAM_SPI0_BASE+SAM_SPI_CR_OFFSET) /* Control Register */ +#define SAM_SPI0_MR (SAM_SPI0_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */ +#define SAM_SPI0_RDR (SAM_SPI0_BASE+SAM_SPI_RDR_OFFSET) /* Receive Data Register */ +#define SAM_SPI0_TDR (SAM_SPI0_BASE+SAM_SPI_TDR_OFFSET) /* Transmit Data Register */ +#define SAM_SPI0_SR (SAM_SPI0_BASE+SAM_SPI_SR_OFFSET) /* Status Register */ +#define SAM_SPI0_IER (SAM_SPI0_BASE+SAM_SPI_IER_OFFSET) /* Interrupt Enable Register */ +#define SAM_SPI0_IDR (SAM_SPI0_BASE+SAM_SPI_IDR_OFFSET) /* Interrupt Disable Register */ +#define SAM_SPI0_IMR (SAM_SPI0_BASE+SAM_SPI_IMR_OFFSET) /* Interrupt Mask Register */ +#define SAM_SPI0_CSR0 (SAM_SPI0_BASE+SAM_SPI_CSR0_OFFSET) /* Chip Select Register 0 */ +#define SAM_SPI0_CSR1 (SAM_SPI0_BASE+SAM_SPI_CSR1_OFFSET) /* Chip Select Register 1 */ +#define SAM_SPI0_CSR2 (SAM_SPI0_BASE+SAM_SPI_CSR2_OFFSET) /* Chip Select Register 2 */ +#define SAM_SPI0_CSR3 (SAM_SPI0_BASE+SAM_SPI_CSR3_OFFSET) /* Chip Select Register 3 */ +#define SAM_SPI0_WPCR (SAM_SPI0_BASE+SAM_SPI_WPCR_OFFSET) /* Write Protection Control Register */ +#define SAM_SPI0_WPSR (SAM_SPI0_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */ + +#if SAMV7_NSPI > 1 +# define SAM_SPI1_CR (SAM_SPI1_BASE+SAM_SPI_CR_OFFSET) /* Control Register */ +# define SAM_SPI1_MR (SAM_SPI1_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */ +# define SAM_SPI1_RDR (SAM_SPI1_BASE+SAM_SPI_RDR_OFFSET) /* Receive Data Register */ +# define SAM_SPI1_TDR (SAM_SPI1_BASE+SAM_SPI_TDR_OFFSET) /* Transmit Data Register */ +# define SAM_SPI1_SR (SAM_SPI1_BASE+SAM_SPI_SR_OFFSET) /* Status Register */ +# define SAM_SPI1_IER (SAM_SPI1_BASE+SAM_SPI_IER_OFFSET) /* Interrupt Enable Register */ +# define SAM_SPI1_IDR (SAM_SPI1_BASE+SAM_SPI_IDR_OFFSET) /* Interrupt Disable Register */ +# define SAM_SPI1_IMR (SAM_SPI1_BASE+SAM_SPI_IMR_OFFSET) /* Interrupt Mask Register */ +# define SAM_SPI1_CSR0 (SAM_SPI1_BASE+SAM_SPI_CSR0_OFFSET) /* Chip Select Register 0 */ +# define SAM_SPI1_CSR1 (SAM_SPI1_BASE+SAM_SPI_CSR1_OFFSET) /* Chip Select Register 1 */ +# define SAM_SPI1_CSR2 (SAM_SPI1_BASE+SAM_SPI_CSR2_OFFSET) /* Chip Select Register 2 */ +# define SAM_SPI1_CSR3 (SAM_SPI1_BASE+SAM_SPI_CSR3_OFFSET) /* Chip Select Register 3 */ +# define SAM_SPI1_WPCR (SAM_SPI1_BASE+SAM_SPI_WPCR_OFFSET) /* Write Protection Control Register */ +# define SAM_SPI1_WPSR (SAM_SPI1_BASE+SAM_SPI_WPSR_OFFSET) /* Write Protection Status Register */ +#endif + +/* SPI register bit definitions *********************************************************/ + +/* SPI Control Register */ + +#define SPI_CR_SPIEN (1 << 0) /* Bit 0: SPI Enable */ +#define SPI_CR_SPIDIS (1 << 1) /* Bit 1: SPI Disable */ +#define SPI_CR_SWRST (1 << 7) /* Bit 7: SPI Software Reset */ +#define SPI_CR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */ + +/* SPI Mode Register */ + +#define SPI_MR_MSTR (1 << 0) /* Bit 0: Master/Slave Mode */ +#define SPI_MR_PS (1 << 1) /* Bit 1: Peripheral Select */ +#define SPI_MR_PCSDEC (1 << 2) /* Bit 2: Chip Select Decode */ +#define SPI_MR_MODFDIS (1 << 4) /* Bit 4: Mode Fault Detection */ +#define SPI_MR_WDRBT (1 << 5) /* Bit 5: Wait Data Read Before Transfer */ +#define SPI_MR_LLB (1 << 7) /* Bit 7: Local Loopback Enable */ +#define SPI_MR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ +#define SPI_MR_PCS_MASK (15 << SPI_MR_PCS_SHIFT) +# define SPI_MR_PCS0 (0 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */ +# define SPI_MR_PCS1 (1 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */ +# define SPI_MR_PCS2 (3 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ +# define SPI_MR_PCS3 (7 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ +#define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */ +#define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT) +# define SPI_MR_DLYBCS(n) ((uint32_t)(n) << SPI_MR_DLYBCS_SHIFT) + +/* SPI Receive Data Register */ + +#define SPI_RDR_RD_SHIFT (0) /* Bits 0-15: Receive Data */ +#define SPI_RDR_RD_MASK (0xffff << SPI_RDR_RD_SHIFT) +#define SPI_RDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ +#define SPI_RDR_PCS_MASK (15 << SPI_RDR_PCS_SHIFT) +# define SPI_RDR_PCS0 (0 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */ +# define SPI_RDR_PCS1 (1 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */ +# define SPI_RDR_PCS2 (3 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ +# define SPI_RDR_PCS3 (7 << SPI_RDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ + +/* SPI Transmit Data Register */ + +#define SPI_TDR_TD_SHIFT (0) /* Bits 0-15: Transmit Data */ +#define SPI_TDR_TD_MASK (0xffff << SPI_TDR_TD_SHIFT) +#define SPI_TDR_PCS_SHIFT (16) /* Bits 16-19: Peripheral Chip Select */ +#define SPI_TDR_PCS_MASK (15 << SPI_TDR_PCS_SHIFT) +# define SPI_TDR_PCS0 (0 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1110 (w/PCSDEC=0) */ +# define SPI_TDR_PCS1 (1 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */ +# define SPI_TDR_PCS2 (3 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */ +# define SPI_TDR_PCS3 (7 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */ +#define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */ + +/* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register, + * and SPI Interrupt Mask Register (common bit fields) + */ + +#define SPI_INT_RDRF (1 << 0) /* Bit 0: Receive Data Register Full Interrupt */ +#define SPI_INT_TDRE (1 << 1) /* Bit 1: Transmit Data Register Empty Interrupt */ +#define SPI_INT_MODF (1 << 2) /* Bit 2: Mode Fault Error Interrupt */ +#define SPI_INT_OVRES (1 << 3) /* Bit 3: Overrun Error Interrupt */ +#define SPI_INT_NSSR (1 << 8) /* Bit 8: NSS Rising Interrupt */ +#define SPI_INT_TXEMPTY (1 << 9) /* Bit 9: Transmission Registers Empty Interrupt */ +#define SPI_INT_UNDES (1 << 10) /* Bit 10: Underrun Error Status Interrupt (slave) */ +#define SPI_SR_SPIENS (1 << 16) /* Bit 16: SPI Enable Status (SR only) */ + +/* SPI Chip Select Registers 0-3 */ + +#define SPI_CSR_CPOL (1 << 0) /* Bit 0: Clock Polarity */ +#define SPI_CSR_NCPHA (1 << 1) /* Bit 1: Clock Phase */ +#define SPI_CSR_CSNAAT (1 << 2) /* Bit 2: Chip Select Not Active After Transfer */ +#define SPI_CSR_CSAAT (1 << 3) /* Bit 3: Chip Select Active After Transfer */ +#define SPI_CSR_BITS_SHIFT (4) /* Bits 4-7: Bits Per Transfer */ +#define SPI_CSR_BITS_MASK (15 << SPI_CSR_BITS_SHIFT) +# define SPI_CSR_BITS(n) (((n)-8) << SPI_CSR_BITS_SHIFT) /* n, n=8-16 */ +# define SPI_CSR_BITS8 (0 << SPI_CSR_BITS_SHIFT) /* 8 */ +# define SPI_CSR_BITS9 (1 << SPI_CSR_BITS_SHIFT) /* 9 */ +# define SPI_CSR_BITS10 (2 << SPI_CSR_BITS_SHIFT) /* 10 */ +# define SPI_CSR_BITS11 (3 << SPI_CSR_BITS_SHIFT) /* 11 */ +# define SPI_CSR_BITS12 (4 << SPI_CSR_BITS_SHIFT) /* 12 */ +# define SPI_CSR_BITS13 (5 << SPI_CSR_BITS_SHIFT) /* 13 */ +# define SPI_CSR_BITS14 (6 << SPI_CSR_BITS_SHIFT) /* 14 */ +# define SPI_CSR_BITS15 (7 << SPI_CSR_BITS_SHIFT) /* 15 */ +# define SPI_CSR_BITS16 (8 << SPI_CSR_BITS_SHIFT) /* 16 */ +#define SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */ +#define SPI_CSR_SCBR_MASK (0xff << SPI_CSR_SCBR_SHIFT) +# define SPI_CSR_SCBR(n) ((uint32_t)(n) << SPI_CSR_SCBR_SHIFT) +#define SPI_CSR_DLYBS_SHIFT (16) /* Bits 16-23: Delay Before SPCK */ +#define SPI_CSR_DLYBS_MASK (0xff << SPI_CSR_DLYBS_SHIFT) +# define SPI_CSR_DLYBS(n) ((uint32_t)(n) << SPI_CSR_DLYBS_SHIFT) +#define SPI_CSR_DLYBCT_SHIFT (24) /* Bits 24-31: Delay Between Consecutive Transfers */ +#define SPI_CSR_DLYBCT_MASK (0xff << SPI_CSR_DLYBCT_SHIFT) +# define SPI_CSR_DLYBCT(n) ((uint32_t)(n) << SPI_CSR_DLYBCT_SHIFT) + +/* SPI Write Protection Control Register */ + +#define SPI_WPCR_WPEN (1 << 0) /* Bit 0: SPI Write Protection Enable */ +#define SPI_WPCR_WPKEY_SHIFT (8) /* Bits 8-31: SPI Write Protection Key Password */ +#define SPI_WPCR_WPKEY_MASK (0x00ffffff << SPI_WPCR_WPKEY_SHIFT) +# define SPI_WPCR_WPKEY (0x00535049 << SPI_WPCR_WPKEY_SHIFT) + +/* SPI Write Protection Status Register */ + +#define SPI_WPSR_WPVS (1 << 0) /* Bit 0: SPI Write Protection Violation Status */ +#define SPI_WPSR_WPVSRC_SHIFT (8) /* Bits 8-15: SPI Write Protection Violation Source */ +#define SPI_WPSR_WPVSRC_MASK (0xff << SPI_WPSR_WPVSRC_SHIFT) + +/**************************************************************************************** + * Public Types + ****************************************************************************************/ + +/**************************************************************************************** + * Public Data + ****************************************************************************************/ + +/**************************************************************************************** + * Public Functions + ****************************************************************************************/ + +#endif /* SAMV7_NSPI > 0 */ +#endif /* __ARCH_ARM_SRC_SAMV7_CHIP_SAM_SPI_H */ diff --git a/arch/arm/src/samv7/sam_spi.c b/arch/arm/src/samv7/sam_spi.c new file mode 100644 index 0000000000..1fc521d2d2 --- /dev/null +++ b/arch/arm/src/samv7/sam_spi.c @@ -0,0 +1,1941 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_spi.c + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * Diego Sanchez + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include "up_internal.h" +#include "up_arch.h" + +#include "sam_gpio.h" +#include "sam_xdmac.h" +#include "sam_periphclks.h" +#include "sam_spi.h" +#include "chip/sam_pmc.h" +#include "chip/sam_xdmac.h" +#include "chip/sam_spi.h" +#include "chip/sam_pinmap.h" + +#if defined(CONFIG_SAMV7_SPI0) || defined(CONFIG_SAMV7_SPI1) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +/* When SPI DMA is enabled, small DMA transfers will still be performed by + * polling logic. But we need a threshold value to determine what is small. + * That value is provided by CONFIG_SAMV7_SPI_DMATHRESHOLD. + */ + +#ifndef CONFIG_SAMV7_SPI_DMATHRESHOLD +# define CONFIG_SAMV7_SPI_DMATHRESHOLD 4 +#endif + +#ifdef CONFIG_SAMV7_SPI_DMA + +# if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_DMAC0) +# define SAMV7_SPI0_DMA true +# else +# define SAMV7_SPI0_DMA false +# endif + +# if defined(CONFIG_SAMV7_SPI1) && defined(CONFIG_SAMV7_DMAC1) +# define SAMV7_SPI1_DMA true +# else +# define SAMV7_SPI1_DMA false +# endif +#endif + +#ifndef CONFIG_SAMV7_SPI_DMA +# undef CONFIG_SAMV7_SPI_DMADEBUG +#endif + +/* Clocking *****************************************************************/ +/* The SPI Baud rate clock is generated by dividing the peripheral clock by + * a value between 1 and 255 + */ + +#define SAM_SPI_CLOCK BOARD_MCK_FREQUENCY /* Frequency of the main clock */ + +/* DMA timeout. The value is not critical; we just don't want the system to + * hang in the event that a DMA does not finish. This is set to + */ + +#define DMA_TIMEOUT_MS (800) +#define DMA_TIMEOUT_TICKS MSEC2TICK(DMA_TIMEOUT_MS) + +/* Debug *******************************************************************/ +/* Check if SPI debut is enabled (non-standard.. no support in + * include/debug.h + */ + +#ifndef CONFIG_DEBUG +# undef CONFIG_DEBUG_VERBOSE +# undef CONFIG_DEBUG_SPI +# undef CONFIG_SAMV7_SPI_DMADEBUG +# undef CONFIG_SAMV7_SPI_REGDEBUG +#endif + +#ifndef CONFIG_DEBUG_DMA +# undef CONFIG_SAMV7_SPI_DMADEBUG +#endif + +#ifdef CONFIG_DEBUG_SPI +# define spidbg lldbg +# ifdef CONFIG_DEBUG_VERBOSE +# define spivdbg lldbg +# else +# define spivdbg(x...) +# endif +#else +# define spidbg(x...) +# define spivdbg(x...) +#endif + +#define DMA_INITIAL 0 +#define DMA_AFTER_SETUP 1 +#define DMA_AFTER_START 2 +#define DMA_CALLBACK 3 +#define DMA_TIMEOUT 3 +#define DMA_END_TRANSFER 4 +#define DMA_NSAMPLES 5 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The state of the one SPI chip select */ + +struct sam_spics_s +{ + struct spi_dev_s spidev; /* Externally visible part of the SPI interface */ + +#ifndef CONFIG_SPI_OWNBUS + uint32_t frequency; /* Requested clock frequency */ + uint32_t actual; /* Actual clock frequency */ + uint8_t mode; /* Mode 0,1,2,3 */ +#endif + uint8_t nbits; /* Width of word in bits (8 to 16) */ + +#if defined(CONFIG_SAMV7_SPI0) || defined(CONFIG_SAMV7_SPI1) + uint8_t spino; /* SPI controller number (0 or 1) */ +#endif + uint8_t cs; /* Chip select number */ + +#ifdef CONFIG_SAMV7_SPI_DMA + bool candma; /* DMA is supported */ + sem_t dmawait; /* Used to wait for DMA completion */ + WDOG_ID dmadog; /* Watchdog that handles DMA timeouts */ + int result; /* DMA result */ + DMA_HANDLE rxdma; /* SPI RX DMA handle */ + DMA_HANDLE txdma; /* SPI TX DMA handle */ +#endif + + /* Debug stuff */ + +#ifdef CONFIG_SAMV7_SPI_DMADEBUG + struct sam_dmaregs_s rxdmaregs[DMA_NSAMPLES]; + struct sam_dmaregs_s txdmaregs[DMA_NSAMPLES]; +#endif +}; + +/* Type of board-specific SPI status function */ + +typedef void (*select_t)(enum spi_dev_e devid, bool selected); + +/* Chip select register offsetrs */ + +/* The overall state of one SPI controller */ + +struct sam_spidev_s +{ + uint32_t base; /* SPI controller register base address */ + sem_t spisem; /* Assures mutually exclusive access to SPI */ + select_t select; /* SPI select call-out */ + bool initialized; /* TRUE: Controller has been initialized */ +#ifdef CONFIG_SAMV7_SPI_DMA + uint8_t rxintf; /* RX hardware interface number */ + uint8_t txintf; /* TX hardware interface number */ +#endif + + /* Debug stuff */ + +#ifdef CONFIG_SAMV7_SPI_REGDEBUG + bool wrlast; /* Last was a write */ + uint32_t addresslast; /* Last address */ + uint32_t valuelast; /* Last value */ + int ntimes; /* Number of times */ +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Helpers */ + +#ifdef CONFIG_SAMV7_SPI_REGDEBUG +static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, + uint32_t value, uint32_t address); +#else +# define spi_checkreg(spi,wr,value,address) (false) +#endif + +static inline uint32_t spi_getreg(struct sam_spidev_s *spi, + unsigned int offset); +static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value, + unsigned int offset); +static inline struct sam_spidev_s *spi_device(struct sam_spics_s *spics); + +#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE) +static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg); +#else +# define spi_dumpregs(spi,msg) +#endif + +static inline void spi_flush(struct sam_spidev_s *spi); +static inline uint32_t spi_cs2pcs(struct sam_spics_s *spics); + +/* DMA support */ + +#ifdef CONFIG_SAMV7_SPI_DMA + +#ifdef CONFIG_SAMV7_SPI_DMADEBUG +# define spi_rxdma_sample(s,i) sam_dmasample((s)->rxdma, &(s)->rxdmaregs[i]) +# define spi_txdma_sample(s,i) sam_dmasample((s)->txdma, &(s)->txdmaregs[i]) +static void spi_dma_sampleinit(struct sam_spics_s *spics); +static void spi_dma_sampledone(struct sam_spics_s *spics); + +#else +# define spi_rxdma_sample(s,i) +# define spi_txdma_sample(s,i) +# define spi_dma_sampleinit(s) +# define spi_dma_sampledone(s) + +#endif + +static void spi_rxcallback(DMA_HANDLE handle, void *arg, int result); +static void spi_txcallback(DMA_HANDLE handle, void *arg, int result); +static inline uintptr_t spi_regaddr(struct sam_spics_s *spics, + unsigned int offset); +#endif + +/* SPI methods */ + +#ifndef CONFIG_SPI_OWNBUS +static int spi_lock(struct spi_dev_s *dev, bool lock); +#endif +static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid, + bool selected); +static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency); +static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode); +static void spi_setbits(struct spi_dev_s *dev, int nbits); +static uint16_t spi_send(struct spi_dev_s *dev, uint16_t ch); +#ifdef CONFIG_SAMV7_SPI_DMA +static void spi_exchange_nodma(struct spi_dev_s *dev, + const void *txbuffer, void *rxbuffer, size_t nwords); +#endif +static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords); +#ifndef CONFIG_SPI_EXCHANGE +static void spi_sndblock(struct spi_dev_s *dev, + const void *buffer, size_t nwords); +static void spi_recvblock(struct spi_dev_s *dev, void *buffer, + size_t nwords); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* This array maps chip select numbers (0-3) to CSR register offsets */ + +static const uint8_t g_csroffset[4] = +{ + SAM_SPI_CSR0_OFFSET, SAM_SPI_CSR1_OFFSET, + SAM_SPI_CSR2_OFFSET, SAM_SPI_CSR3_OFFSET +}; + +#ifdef CONFIG_SAMV7_SPI0 +/* SPI0 driver operations */ + +static const struct spi_ops_s g_spi0ops = +{ +#ifndef CONFIG_SPI_OWNBUS + .lock = spi_lock, +#endif + .select = spi_select, + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, + .status = sam_spi0status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = sam_spi0cmddata, +#endif + .send = spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = spi_exchange, +#else + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#endif + .registercallback = 0, /* Not implemented */ +}; + +/* This is the overall state of the SPI0 controller */ + +static struct sam_spidev_s g_spi0dev = +{ + .base = SAM_SPI0_BASE, + .select = sam_spi0select, +#ifdef CONFIG_SAMV7_SPI_DMA + .rxintf = DMACHAN_INTF_SPI0RX, + .txintf = DMACHAN_INTF_SPI0TX, +#endif +}; +#endif + +#ifdef CONFIG_SAMV7_SPI1 +/* SPI1 driver operations */ + +static const struct spi_ops_s g_spi1ops = +{ +#ifndef CONFIG_SPI_OWNBUS + .lock = spi_lock, +#endif + .select = spi_select, + .setfrequency = spi_setfrequency, + .setmode = spi_setmode, + .setbits = spi_setbits, + .status = sam_spi1status, +#ifdef CONFIG_SPI_CMDDATA + .cmddata = sam_spi1cmddata, +#endif + .send = spi_send, +#ifdef CONFIG_SPI_EXCHANGE + .exchange = spi_exchange, +#else + .sndblock = spi_sndblock, + .recvblock = spi_recvblock, +#endif + .registercallback = 0, /* Not implemented */ +}; + +/* This is the overall state of the SPI0 controller */ + +static struct sam_spidev_s g_spi1dev = +{ + .base = SAM_SPI1_BASE, + .select = sam_spi1select, +#ifdef CONFIG_SAMV7_SPI_DMA + .rxintf = DMACHAN_INTF_SPI1RX, + .txintf = DMACHAN_INTF_SPI1TX, +#endif +}; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: spi_checkreg + * + * Description: + * Check if the current register access is a duplicate of the preceding. + * + * Input Parameters: + * value - The value to be written + * address - The address of the register to write to + * + * Returned Value: + * true: This is the first register access of this type. + * flase: This is the same as the preceding register access. + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_SPI_REGDEBUG +static bool spi_checkreg(struct sam_spidev_s *spi, bool wr, uint32_t value, + uint32_t address) +{ + if (wr == spi->wrlast && /* Same kind of access? */ + value == spi->valuelast && /* Same value? */ + address == spi->addresslast) /* Same address? */ + { + /* Yes, then just keep a count of the number of times we did this. */ + + spi->ntimes++; + return false; + } + else + { + /* Did we do the previous operation more than once? */ + + if (spi->ntimes > 0) + { + /* Yes... show how many times we did it */ + + lldbg("...[Repeats %d times]...\n", spi->ntimes); + } + + /* Save information about the new access */ + + spi->wrlast = wr; + spi->valuelast = value; + spi->addresslast = address; + spi->ntimes = 0; + } + + /* Return true if this is the first time that we have done this operation */ + + return true; +} +#endif + +/**************************************************************************** + * Name: spi_getreg + * + * Description: + * Read an SPI register + * + ****************************************************************************/ + +static inline uint32_t spi_getreg(struct sam_spidev_s *spi, + unsigned int offset) +{ + uint32_t address = spi->base + offset; + uint32_t value = getreg32(address); + +#ifdef CONFIG_SAMV7_SPI_REGDEBUG + if (spi_checkreg(spi, false, value, address)) + { + lldbg("%08x->%08x\n", address, value); + } +#endif + + return value; +} + +/**************************************************************************** + * Name: spi_putreg + * + * Description: + * Write a value to an SPI register + * + ****************************************************************************/ + +static inline void spi_putreg(struct sam_spidev_s *spi, uint32_t value, + unsigned int offset) +{ + uint32_t address = spi->base + offset; + +#ifdef CONFIG_SAMV7_SPI_REGDEBUG + if (spi_checkreg(spi, true, value, address)) + { + lldbg("%08x<-%08x\n", address, value); + } +#endif + + putreg32(value, address); +} + +/**************************************************************************** + * Name: spi_dumpregs + * + * Description: + * Dump the contents of all SPI registers + * + * Input Parameters: + * spi - The SPI controller to dump + * msg - Message to print before the register data + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_DEBUG_SPI) && defined(CONFIG_DEBUG_VERBOSE) +static void spi_dumpregs(struct sam_spidev_s *spi, const char *msg) +{ + spivdbg("%s:\n", msg); + spivdbg(" MR:%08x SR:%08x IMR:%08x\n", + getreg32(spi->base + SAM_SPI_MR_OFFSET), + getreg32(spi->base + SAM_SPI_SR_OFFSET), + getreg32(spi->base + SAM_SPI_IMR_OFFSET)); + spivdbg(" CSR0:%08x CSR1:%08x CSR2:%08x CSR3:%08x\n", + getreg32(spi->base + SAM_SPI_CSR0_OFFSET), + getreg32(spi->base + SAM_SPI_CSR1_OFFSET), + getreg32(spi->base + SAM_SPI_CSR2_OFFSET), + getreg32(spi->base + SAM_SPI_CSR3_OFFSET)); + spivdbg(" WPCR:%08x WPSR:%08x\n", + getreg32(spi->base + SAM_SPI_WPCR_OFFSET), + getreg32(spi->base + SAM_SPI_WPSR_OFFSET)); +} +#endif + +/**************************************************************************** + * Name: spi_device + * + * Description: + * Given a chip select instance, return a pointer to the parent SPI + * controller instance. + * + ****************************************************************************/ + +static inline struct sam_spidev_s *spi_device(struct sam_spics_s *spics) +{ +#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1) + return spics->spino ? &g_spi1dev : &g_spi0dev; +#elif defined(CONFIG_SAMV7_SPI0) + return &g_spi0dev; +#else + return &g_spi1dev; +#endif +} + +/**************************************************************************** + * Name: spi_flush + * + * Description: + * Make sure that there are now dangling SPI transfer in progress + * + * Input Parameters: + * spi - SPI controller state + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void spi_flush(struct sam_spidev_s *spi) +{ + /* Make sure the no TX activity is in progress... waiting if necessary */ + + while ((spi_getreg(spi, SAM_SPI_SR_OFFSET) & SPI_INT_TXEMPTY) == 0); + + /* Then make sure that there is no pending RX data .. reading as + * discarding as necessary. + */ + + while ((spi_getreg(spi, SAM_SPI_SR_OFFSET) & SPI_INT_RDRF) != 0) + { + (void)spi_getreg(spi, SAM_SPI_RDR_OFFSET); + } +} + +/**************************************************************************** + * Name: spi_cs2pcs + * + * Description: + * Map the chip select number to the bit-set PCS field used in the SPI + * registers. A chip select number is used for indexing and identifying + * chip selects. However, the chip select information is represented by + * a bit set in the SPI registers. This function maps those chip select + * numbers to the correct bit set: + * + * CS Returned Spec Effective + * No. PCS Value NPCS + * ---- -------- -------- -------- + * 0 0000 xxx0 1110 + * 1 0001 xx01 1101 + * 2 0011 x011 1011 + * 3 0111 0111 0111 + * + * Input Parameters: + * spics - Device-specific state data + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline uint32_t spi_cs2pcs(struct sam_spics_s *spics) +{ + return ((uint32_t)1 << (spics->cs)) - 1; +} + +/**************************************************************************** + * Name: spi_dma_sampleinit + * + * Description: + * Initialize sampling of DMA registers (if CONFIG_SAMV7_SPI_DMADEBUG) + * + * Input Parameters: + * spics - Chip select doing the DMA + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_SPI_DMADEBUG +static void spi_dma_sampleinit(struct sam_spics_s *spics) +{ + /* Put contents of register samples into a known state */ + + memset(spics->rxdmaregs, 0xff, DMA_NSAMPLES * sizeof(struct sam_dmaregs_s)); + memset(spics->txdmaregs, 0xff, DMA_NSAMPLES * sizeof(struct sam_dmaregs_s)); + + /* Then get the initial samples */ + + sam_dmasample(spics->rxdma, &spics->rxdmaregs[DMA_INITIAL]); + sam_dmasample(spics->txdma, &spics->txdmaregs[DMA_INITIAL]); +} +#endif + +/**************************************************************************** + * Name: spi_dma_sampledone + * + * Description: + * Dump sampled DMA registers + * + * Input Parameters: + * spics - Chip select doing the DMA + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_SPI_DMADEBUG +static void spi_dma_sampledone(struct sam_spics_s *spics) +{ + /* Sample the final registers */ + + sam_dmasample(spics->rxdma, &spics->rxdmaregs[DMA_END_TRANSFER]); + sam_dmasample(spics->txdma, &spics->txdmaregs[DMA_END_TRANSFER]); + + /* Then dump the sampled DMA registers */ + /* Initial register values */ + + sam_dmadump(spics->txdma, &spics->txdmaregs[DMA_INITIAL], + "TX: Initial Registers"); + sam_dmadump(spics->rxdma, &spics->rxdmaregs[DMA_INITIAL], + "RX: Initial Registers"); + + /* Register values after DMA setup */ + + sam_dmadump(spics->txdma, &spics->txdmaregs[DMA_AFTER_SETUP], + "TX: After DMA Setup"); + sam_dmadump(spics->rxdma, &spics->rxdmaregs[DMA_AFTER_SETUP], + "RX: After DMA Setup"); + + /* Register values after DMA start */ + + sam_dmadump(spics->txdma, &spics->txdmaregs[DMA_AFTER_START], + "TX: After DMA Start"); + sam_dmadump(spics->rxdma, &spics->rxdmaregs[DMA_AFTER_START], + "RX: After DMA Start"); + + /* Register values at the time of the TX and RX DMA callbacks + * -OR- DMA timeout. + * + * If the DMA timed out, then there will not be any RX DMA + * callback samples. There is probably no TX DMA callback + * samples either, but we don't know for sure. + */ + + sam_dmadump(spics->txdma, &spics->txdmaregs[DMA_CALLBACK], + "TX: At DMA callback"); + + /* Register values at the end of the DMA */ + + if (spics->result == -ETIMEDOUT) + { + sam_dmadump(spics->rxdma, &spics->rxdmaregs[DMA_TIMEOUT], + "RX: At DMA timeout"); + } + else + { + sam_dmadump(spics->rxdma, &spics->rxdmaregs[DMA_CALLBACK], + "RX: At DMA callback"); + } + + sam_dmadump(spics->txdma, &spics->txdmaregs[DMA_END_TRANSFER], + "TX: At End-of-Transfer"); + sam_dmadump(spics->rxdma, &spics->rxdmaregs[DMA_END_TRANSFER], + "RX: At End-of-Transfer"); +} +#endif + +/**************************************************************************** + * Name: spi_dmatimeout + * + * Description: + * The watchdog timeout setup when a has expired without completion of a + * DMA. + * + * Input Parameters: + * argc - The number of arguments (should be 1) + * arg - The argument (state structure reference cast to uint32_t) + * + * Returned Value: + * None + * + * Assumptions: + * Always called from the interrupt level with interrupts disabled. + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_SPI_DMA +static void spi_dmatimeout(int argc, uint32_t arg) +{ + struct sam_spics_s *spics = (struct sam_spics_s *)arg; + DEBUGASSERT(spics != NULL); + + /* Sample DMA registers at the time of the timeout */ + + spi_rxdma_sample(spics, DMA_CALLBACK); + + /* Report timeout result, perhaps overwriting any failure reports from + * the TX callback. + */ + + spics->result = -ETIMEDOUT; + + /* Then wake up the waiting thread */ + + sem_post(&spics->dmawait); +} +#endif + +/**************************************************************************** + * Name: spi_rxcallback + * + * Description: + * This callback function is invoked at the completion of the SPI RX DMA. + * + * Input Parameters: + * handle - The DMA handler + * arg - A pointer to the chip select structure + * result - The result of the DMA transfer + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_SPI_DMA +static void spi_rxcallback(DMA_HANDLE handle, void *arg, int result) +{ + struct sam_spics_s *spics = (struct sam_spics_s *)arg; + DEBUGASSERT(spics != NULL); + + /* Cancel the watchdog timeout */ + + (void)wd_cancel(spics->dmadog); + + /* Sample DMA registers at the time of the callback */ + + spi_rxdma_sample(spics, DMA_CALLBACK); + + /* Report the result of the transfer only if the TX callback has not already + * reported an error. + */ + + if (spics->result == -EBUSY) + { + /* Save the result of the transfer if no error was previously reported */ + + spics->result = result; + } + + /* Then wake up the waiting thread */ + + sem_post(&spics->dmawait); +} +#endif + +/**************************************************************************** + * Name: spi_txcallback + * + * Description: + * This callback function is invoked at the completion of the SPI TX DMA. + * + * Input Parameters: + * handle - The DMA handler + * arg - A pointer to the chip select structure + * result - The result of the DMA transfer + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_SPI_DMA +static void spi_txcallback(DMA_HANDLE handle, void *arg, int result) +{ + struct sam_spics_s *spics = (struct sam_spics_s *)arg; + DEBUGASSERT(spics != NULL); + + spi_txdma_sample(spics, DMA_CALLBACK); + + /* Do nothing on the TX callback unless an error is reported. This + * callback is not really important because the SPI exchange is not + * complete until the RX callback is received. + */ + + if (result != OK && spics->result == -EBUSY) + { + /* Save the result of the transfer if an error is reported */ + + spics->result = result; + } +} +#endif + +/**************************************************************************** + * Name: spi_regaddr + * + * Description: + * Return the address of an SPI register + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_SPI_DMA +static inline uintptr_t spi_regaddr(struct sam_spics_s *spics, + unsigned int offset) +{ + struct sam_spidev_s *spi = spi_device(spics); + return spi->base + offset; +} +#endif + +/**************************************************************************** + * Name: spi_lock + * + * Description: + * On SPI buses where there are multiple devices, it will be necessary to + * lock SPI to have exclusive access to the buses for a sequence of + * transfers. The bus should be locked before the chip is selected. After + * locking the SPI bus, the caller should then also call the setfrequency, + * setbits, and setmode methods to make sure that the SPI is properly + * configured for the device. If the SPI bus is being shared, then it + * may have been left in an incompatible state. + * + * Input Parameters: + * dev - Device-specific state data + * lock - true: Lock spi bus, false: unlock SPI bus + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_OWNBUS +static int spi_lock(struct spi_dev_s *dev, bool lock) +{ + struct sam_spics_s *spics = (struct sam_spics_s *)dev; + struct sam_spidev_s *spi = spi_device(spics); + + spivdbg("lock=%d\n", lock); + if (lock) + { + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(&spi->spisem) != 0) + { + /* The only case that an error should occur here is if the wait was awakened + * by a signal. + */ + + ASSERT(errno == EINTR); + } + } + else + { + (void)sem_post(&spi->spisem); + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: spi_select + * + * Description: + * This function does not actually set the chip select line. Rather, it + * simply maps the device ID into a chip select number and retains that + * chip select number for later use. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + + static void spi_select(struct spi_dev_s *dev, enum spi_dev_e devid, + bool selected) + { + struct sam_spics_s *spics = (struct sam_spics_s *)dev; + struct sam_spidev_s *spi = spi_device(spics); + uint32_t regval; + + /* Are we selecting or de-selecting the device? */ + + spivdbg("selected=%d\n", selected); + if (selected) + { + spivdbg("cs=%d\n", spics->cs); + + /* Before writing the TDR, the PCS field in the SPI_MR register must be set + * in order to select a slave. + */ + + regval = spi_getreg(spi, SAM_SPI_MR_OFFSET); + regval &= ~SPI_MR_PCS_MASK; + regval |= (spi_cs2pcs(spics) << SPI_MR_PCS_SHIFT); + spi_putreg(spi, regval, SAM_SPI_MR_OFFSET); + } + + /* Perform any board-specific chip select operations. PIO chip select + * pins may be programmed by the board specific logic in one of two + * different ways. First, the pins may be programmed as SPI peripherals. + * In that case, the pins are completely controlled by the SPI driver. + * The sam_spi[0|1]select methods still needs to be provided, but they + * may be only stubs. + * + * An alternative way to program the PIO chip select pins is as normal + * PIO outputs. In that case, the automatic control of the CS pins is + * bypassed and this function must provide control of the chip select. + * NOTE: In this case, the PIO output pin does *not* have to be the + * same as the NPCS pin normal associated with the chip select number. + */ + + spi->select(devid, selected); +} + +/**************************************************************************** + * Name: spi_setfrequency + * + * Description: + * Set the SPI frequency. + * + * Input Parameters: + * dev - Device-specific state data + * frequency - The SPI frequency requested + * + * Returned Value: + * Returns the actual frequency selected + * + ****************************************************************************/ + +static uint32_t spi_setfrequency(struct spi_dev_s *dev, uint32_t frequency) +{ + struct sam_spics_s *spics = (struct sam_spics_s *)dev; + struct sam_spidev_s *spi = spi_device(spics); + uint32_t actual; + uint32_t scbr; + uint32_t dlybs; + uint32_t dlybct; + uint32_t regval; + unsigned int offset; + + spivdbg("cs=%d frequency=%d\n", spics->cs, frequency); + + /* Check if the requested frequency is the same as the frequency selection */ + +#ifndef CONFIG_SPI_OWNBUS + if (spics->frequency == frequency) + { + /* We are already at this frequency. Return the actual. */ + + return spics->actual; + } +#endif + + /* Configure SPI to a frequency as close as possible to the requested frequency. + * + * SPCK frequency = SPI_CLK / SCBR, or SCBR = SPI_CLK / frequency + */ + + scbr = SAM_SPI_CLOCK / frequency; + + if (scbr < 8) + { + scbr = 8; + } + else if (scbr > 254) + { + scbr = 254; + } + + scbr = (scbr + 1) & ~1; + + /* Save the new scbr value */ + + offset = (unsigned int)g_csroffset[spics->cs]; + regval = spi_getreg(spi, offset); + regval &= ~(SPI_CSR_SCBR_MASK | SPI_CSR_DLYBS_MASK | SPI_CSR_DLYBCT_MASK); + regval |= scbr << SPI_CSR_SCBR_SHIFT; + + /* DLYBS: Delay Before SPCK. This field defines the delay from NPCS valid to the + * first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK + * transition is 1/2 the SPCK clock period. Otherwise, the following equations + * determine the delay: + * + * Delay Before SPCK = DLYBS / SPI_CLK + * + * For a 2uS delay + * + * DLYBS = SPI_CLK * 0.000002 = SPI_CLK / 500000 + */ + + dlybs = SAM_SPI_CLOCK / 500000; + regval |= dlybs << SPI_CSR_DLYBS_SHIFT; + + /* DLYBCT: Delay Between Consecutive Transfers. This field defines the delay + * between two consecutive transfers with the same peripheral without removing + * the chip select. The delay is always inserted after each transfer and + * before removing the chip select if needed. + * + * Delay Between Consecutive Transfers = (32 x DLYBCT) / SPI_CLK + * + * For a 5uS delay: + * + * DLYBCT = SPI_CLK * 0.000005 / 32 = SPI_CLK / 200000 / 32 + */ + + dlybct = SAM_SPI_CLOCK / 200000 / 32; + regval |= dlybct << SPI_CSR_DLYBCT_SHIFT; + spi_putreg(spi, regval, offset); + + /* Calculate the new actual frequency */ + + actual = SAM_SPI_CLOCK / scbr; + spivdbg("csr[offset=%02x]=%08x actual=%d\n", offset, regval, actual); + + /* Save the frequency setting */ + +#ifndef CONFIG_SPI_OWNBUS + spics->frequency = frequency; + spics->actual = actual; +#endif + + spidbg("Frequency %d->%d\n", frequency, actual); + return actual; +} + +/**************************************************************************** + * Name: spi_setmode + * + * Description: + * Set the SPI mode. Optional. See enum spi_mode_e for mode definitions + * + * Input Parameters: + * dev - Device-specific state data + * mode - The SPI mode requested + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void spi_setmode(struct spi_dev_s *dev, enum spi_mode_e mode) +{ + struct sam_spics_s *spics = (struct sam_spics_s *)dev; + struct sam_spidev_s *spi = spi_device(spics); + uint32_t regval; + unsigned int offset; + + spivdbg("cs=%d mode=%d\n", spics->cs, mode); + + /* Has the mode changed? */ + +#ifndef CONFIG_SPI_OWNBUS + if (mode != spics->mode) + { +#endif + /* Yes... Set the mode appropriately: + * + * SPI CPOL NCPHA + * MODE + * 0 0 1 + * 1 0 0 + * 2 1 1 + * 3 1 0 + */ + + offset = (unsigned int)g_csroffset[spics->cs]; + regval = spi_getreg(spi, offset); + regval &= ~(SPI_CSR_CPOL | SPI_CSR_NCPHA); + + switch (mode) + { + case SPIDEV_MODE0: /* CPOL=0; NCPHA=1 */ + regval |= SPI_CSR_NCPHA; + break; + + case SPIDEV_MODE1: /* CPOL=0; NCPHA=0 */ + break; + + case SPIDEV_MODE2: /* CPOL=1; NCPHA=1 */ + regval |= (SPI_CSR_CPOL | SPI_CSR_NCPHA); + break; + + case SPIDEV_MODE3: /* CPOL=1; NCPHA=0 */ + regval |= SPI_CSR_CPOL; + break; + + default: + DEBUGASSERT(FALSE); + return; + } + + spi_putreg(spi, regval, offset); + spivdbg("csr[offset=%02x]=%08x\n", offset, regval); + + /* Save the mode so that subsequent re-configurations will be faster */ + +#ifndef CONFIG_SPI_OWNBUS + spics->mode = mode; + } +#endif +} + +/**************************************************************************** + * Name: spi_setbits + * + * Description: + * Set the number if bits per word. + * + * Input Parameters: + * dev - Device-specific state data + * nbits - The number of bits requests + * + * Returned Value: + * none + * + ****************************************************************************/ + +static void spi_setbits(struct spi_dev_s *dev, int nbits) +{ + struct sam_spics_s *spics = (struct sam_spics_s *)dev; + struct sam_spidev_s *spi = spi_device(spics); + uint32_t regval; + unsigned int offset; + + spivdbg("cs=%d nbits=%d\n", spics->cs, nbits); + DEBUGASSERT(spics && nbits > 7 && nbits < 17); + + /* Has the number of bits changed? */ + +#ifndef CONFIG_SPI_OWNBUS + if (nbits != spics->nbits) +#endif + { + /* Yes... Set number of bits appropriately */ + + offset = (unsigned int)g_csroffset[spics->cs]; + regval = spi_getreg(spi, offset); + regval &= ~SPI_CSR_BITS_MASK; + regval |= SPI_CSR_BITS(nbits); + spi_putreg(spi, regval, offset); + + spivdbg("csr[offset=%02x]=%08x\n", offset, regval); + + /* Save the selection so the subsequence re-configurations will be faster */ + + spics->nbits = nbits; + } +} + +/**************************************************************************** + * Name: spi_send + * + * Description: + * Exchange one word on SPI + * + * Input Parameters: + * dev - Device-specific state data + * wd - The word to send. the size of the data is determined by the + * number of bits selected for the SPI interface. + * + * Returned Value: + * response + * + ****************************************************************************/ + +static uint16_t spi_send(struct spi_dev_s *dev, uint16_t wd) +{ + uint8_t txbyte; + uint8_t rxbyte; + + /* spi_exchange can do this. Note: right now, this only deals with 8-bit + * words. If the SPI interface were configured for words of other sizes, + * this would fail. + */ + + txbyte = (uint8_t)wd; + rxbyte = (uint8_t)0; + spi_exchange(dev, &txbyte, &rxbyte, 1); + + spivdbg("Sent %02x received %02x\n", txbyte, rxbyte); + return (uint16_t)rxbyte; +} + +/**************************************************************************** + * Name: spi_exchange (and spi_exchange_nodma) + * + * Description: + * Exchange a block of data from SPI. There are two versions of this + * function: (1) One that is enabled only when CONFIG_SAMV7_SPI_DMA=y + * that performs DMA SPI transfers, but only when a larger block of + * data is being transferred. And (2) another version that does polled + * SPI transfers. When CONFIG_SAMV7_SPI_DMA=n the latter is the only + * version avaialable; when CONFIG_SAMV7_SPI_DMA=y, this version is only + * used for short SPI transfers and gets renamed as spi_exchange_nodma). + * + * Input Parameters: + * dev - Device-specific state data + * txbuffer - A pointer to the buffer of data to be sent + * rxbuffer - A pointer to the buffer in which to receive data + * nwords - the length of data that to be exchanged in units of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_SPI_DMA +static void spi_exchange_nodma(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords) +#else +static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords) +#endif +{ + struct sam_spics_s *spics = (struct sam_spics_s *)dev; + struct sam_spidev_s *spi = spi_device(spics); + uint32_t pcs; + uint32_t data; + uint16_t *rxptr16; + uint16_t *txptr16; + uint8_t *rxptr8; + uint8_t *txptr8; + + spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); + + /* Set up PCS bits */ + + pcs = spi_cs2pcs(spics) << SPI_TDR_PCS_SHIFT; + + /* Set up working pointers */ + + if (spics->nbits > 8) + { + rxptr16 = (uint16_t*)rxbuffer; + txptr16 = (uint16_t*)txbuffer; + rxptr8 = NULL; + txptr8 = NULL; + } + else + { + rxptr16 = NULL; + txptr16 = NULL; + rxptr8 = (uint8_t*)rxbuffer; + txptr8 = (uint8_t*)txbuffer; + } + + /* Make sure that any previous transfer is flushed from the hardware */ + + spi_flush(spi); + + /* Loop, sending each word in the user-provided data buffer. + * + * Note 1: Good SPI performance would require that we implement DMA + * transfers! + * Note 2: This loop might be made more efficient. Would logic + * like the following improve the throughput? Or would it + * just add the risk of overruns? + * + * Get word 1; + * Send word 1; Now word 1 is "in flight" + * nwords--; + * for ( ; nwords > 0; nwords--) + * { + * Get word N. + * Wait for TDRE meaning that word N-1 has moved to the shift + * register. + * Disable interrupts to keep the following atomic + * Send word N. Now both work N-1 and N are "in flight" + * Wait for RDRF meaning that word N-1 is available + * Read word N-1. + * Re-enable interrupts. + * Save word N-1. + * } + * Wait for RDRF meaning that the final word is available + * Read the final word. + * Save the final word. + */ + + for ( ; nwords > 0; nwords--) + { + /* Get the data to send (0xff if there is no data source). */ + + if (txptr8) + { + data = (uint32_t)*txptr8++; + } + else if (txptr16) + { + data = (uint32_t)*txptr16++; + } + else + { + data = 0xffff; + } + + /* Set the PCS field in the value written to the TDR */ + + data |= pcs; + + /* Do we need to set the LASTXFER bit in the TDR value too? */ + +#ifdef CONFIG_SPI_VARSELECT + if (nwords == 1) + { + data |= SPI_TDR_LASTXFER; + } +#endif + + /* Wait for any previous data written to the TDR to be transferred + * to the serializer. + */ + + while ((spi_getreg(spi, SAM_SPI_SR_OFFSET) & SPI_INT_TDRE) == 0); + + /* Write the data to transmitted to the Transmit Data Register (TDR) */ + + spi_putreg(spi, data, SAM_SPI_TDR_OFFSET); + + /* Wait for the read data to be available in the RDR. + * TODO: Data transfer rates would be improved using the RX FIFO + * (and also DMA) + */ + + while ((spi_getreg(spi, SAM_SPI_SR_OFFSET) & SPI_INT_RDRF) == 0); + + /* Read the received data from the SPI Data Register. */ + + data = spi_getreg(spi, SAM_SPI_RDR_OFFSET); + if (rxptr8) + { + *rxptr8++ = (uint8_t)data; + } + else if (rxptr16) + { + *rxptr16++ = (uint16_t)data; + } + } +} + +#ifdef CONFIG_SAMV7_SPI_DMA +static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer, + void *rxbuffer, size_t nwords) +{ + struct sam_spics_s *spics = (struct sam_spics_s *)dev; + struct sam_spidev_s *spi = spi_device(spics); + uint32_t rxflags; + uint32_t txflags; + uint32_t txdummy; + uint32_t rxdummy; + uint32_t regaddr; + uint32_t memaddr; + uint32_t width; + size_t nbytes; + int ret; + + /* Convert the number of word to a number of bytes */ + + nbytes = (spics->nbits > 8) ? nwords << 1 : nwords; + + /* If we cannot do DMA -OR- if this is a small SPI transfer, then let + * spi_exchange_nodma() do the work. + */ + + if (!spics->candma || nbytes <= CONFIG_SAMV7_SPI_DMATHRESHOLD) + { + spi_exchange_nodma(dev, txbuffer, rxbuffer, nwords); + return; + } + + spivdbg("txbuffer=%p rxbuffer=%p nwords=%d\n", txbuffer, rxbuffer, nwords); + + spics = (struct sam_spics_s *)dev; + spi = spi_device(spics); + DEBUGASSERT(spics && spi); + + /* Make sure that any previous transfer is flushed from the hardware */ + + spi_flush(spi); + + /* Sample initial DMA registers */ + + spi_dma_sampleinit(spics); + + /* Select the source and destination width bits */ + + if (spics->nbits > 8) + { + width = (DMACH_FLAG_PERIPHWIDTH_16BITS | DMACH_FLAG_MEMWIDTH_16BITS); + } + else + { + width = (DMACH_FLAG_PERIPHWIDTH_8BITS | DMACH_FLAG_MEMWIDTH_8BITS); + } + + /* Configure the DMA channels. There are four different cases: + * + * 1) A true exchange with the memory address incrementing on both + * RX and TX channels, + * 2) A read operation with the memory address incrementing only on + * the receive channel, + * 3) A write operation where the memory address increments only on + * the receive channel, and + * 4) A corner case where there the memory address does not increment + * on either channel. This case might be used in certain cases + * where you want to assure that certain number of clocks are + * provided on the SPI bus. + */ + + /* Configure the RX DMA channel */ + + rxflags = DMACH_FLAG_FIFOCFG_LARGEST | + ((uint32_t)spi->rxintf << DMACH_FLAG_PERIPHPID_SHIFT) | + DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | + DMACH_FLAG_PERIPHCHUNKSIZE_1 | + ((uint32_t)(15) << DMACH_FLAG_MEMPID_SHIFT) | + DMACH_FLAG_MEMCHUNKSIZE_1; + + /* Set the source and destination width bits */ + + rxflags |= width; + + /* Handle the case where there is no sink buffer */ + + if (!rxbuffer) + { + /* No sink data buffer. Point to our dummy buffer and leave + * the rxflags so that no address increment is performed. + */ + + rxbuffer = (void *)&rxdummy; + } + else + { + /* A receive buffer is available. + * + * Invalidate the RX buffer memory to force re-fetching from RAM when + * the DMA completes + */ + + sam_cmcc_invalidate((uintptr_t)rxbuffer, (uintptr_t)rxbuffer + nbytes); + + /* Use normal RX memory incrementing. */ + + rxflags |= DMACH_FLAG_MEMINCREMENT; + } + + /* Configure the TX DMA channel */ + + txflags = DMACH_FLAG_FIFOCFG_LARGEST | + ((uint32_t)spi->txintf << DMACH_FLAG_PERIPHPID_SHIFT) | + DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | + DMACH_FLAG_PERIPHCHUNKSIZE_1 | + ((uint32_t)(15) << DMACH_FLAG_MEMPID_SHIFT) | + DMACH_FLAG_MEMCHUNKSIZE_1; + + /* Set the source and destination width bits */ + + txflags |= width; + + /* Handle the case where there is no source buffer */ + + if (!txbuffer) + { + /* No source data buffer. Point to our dummy buffer and leave + * the txflags so that no address increment is performed. + */ + + txdummy = 0xffffffff; + txbuffer = (const void *)&txdummy; + } + else + { + /* Source data is available. Use normal TX memory incrementing. */ + + txflags |= DMACH_FLAG_MEMINCREMENT; + } + + /* Then configure the DMA channels to make it so */ + + sam_dmaconfig(spics->rxdma, rxflags); + sam_dmaconfig(spics->txdma, txflags); + + /* Configure the RX side of the exchange transfer */ + + regaddr = spi_regaddr(spics, SAM_SPI_RDR_OFFSET); + memaddr = (uintptr_t)rxbuffer; + + ret = sam_dmarxsetup(spics->rxdma, regaddr, memaddr, nwords); + if (ret < 0) + { + dmadbg("ERROR: sam_dmarxsetup failed: %d\n", ret); + return; + } + + spi_rxdma_sample(spics, DMA_AFTER_SETUP); + + /* Configure the TX side of the exchange transfer */ + + regaddr = spi_regaddr(spics, SAM_SPI_TDR_OFFSET); + memaddr = (uintptr_t)txbuffer; + + ret = sam_dmatxsetup(spics->txdma, regaddr, memaddr, nwords); + if (ret < 0) + { + dmadbg("ERROR: sam_dmatxsetup failed: %d\n", ret); + return; + } + + spi_txdma_sample(spics, DMA_AFTER_SETUP); + + /* Start the DMA transfer */ + + spics->result = -EBUSY; + ret = sam_dmastart(spics->rxdma, spi_rxcallback, (void *)spics); + if (ret < 0) + { + dmadbg("ERROR: RX sam_dmastart failed: %d\n", ret); + return; + } + + spi_rxdma_sample(spics, DMA_AFTER_START); + + ret = sam_dmastart(spics->txdma, spi_txcallback, (void *)spics); + if (ret < 0) + { + dmadbg("ERROR: RX sam_dmastart failed: %d\n", ret); + sam_dmastop(spics->rxdma); + return; + } + + spi_txdma_sample(spics, DMA_AFTER_START); + + /* Wait for DMA completion. This is done in a loop because there may be + * false alarm semaphore counts that cause sam_wait() not fail to wait + * or to wake-up prematurely (for example due to the receipt of a signal). + * We know that the DMA has completed when the result is anything other + * that -EBUSY. + */ + + do + { + /* Start (or re-start) the watchdog timeout */ + + ret = wd_start(spics->dmadog, DMA_TIMEOUT_TICKS, + (wdentry_t)spi_dmatimeout, 1, (uint32_t)spics); + if (ret != OK) + { + spidbg("ERROR: wd_start failed: %d\n", ret); + } + + /* Wait for the DMA complete */ + + ret = sem_wait(&spics->dmawait); + + /* Cancel the watchdog timeout */ + + (void)wd_cancel(spics->dmadog); + + /* Check if we were awakened by an error of some kind */ + + if (ret < 0) + { + /* EINTR is not a failure. That simply means that the wait + * was awakened by a signal. + */ + + int errorcode = errno; + if (errorcode != EINTR) + { + DEBUGPANIC(); + return; + } + } + + /* Not that we might be awakened before the wait is over due to + * residual counts on the semaphore. So, to handle, that case, + * we loop until something changes the DMA result to any value other + * than -EBUSY. + */ + } + while (spics->result == -EBUSY); + + /* Dump the sampled DMA registers */ + + spi_dma_sampledone(spics); + + /* Make sure that the DMA is stopped (it will be stopped automatically + * on normal transfers, but not necessarily when the transfer terminates + * on an error condition). + */ + + sam_dmastop(spics->rxdma); + sam_dmastop(spics->txdma); + + /* All we can do is complain if the DMA fails */ + + if (spics->result) + { + spidbg("ERROR: DMA failed with result: %d\n", spics->result); + } +} +#endif /* CONFIG_SAMV7_SPI_DMA */ + +/*************************************************************************** + * Name: spi_sndblock + * + * Description: + * Send a block of data on SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer of data to be sent + * nwords - the length of data to send from the buffer in number of words. + * The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void spi_sndblock(struct spi_dev_s *dev, const void *buffer, + size_t nwords) +{ + /* spi_exchange can do this. */ + + spi_exchange(dev, buffer, NULL, nwords); +} +#endif + +/**************************************************************************** + * Name: spi_recvblock + * + * Description: + * Revice a block of data from SPI + * + * Input Parameters: + * dev - Device-specific state data + * buffer - A pointer to the buffer in which to receive data + * nwords - the length of data that can be received in the buffer in number + * of words. The wordsize is determined by the number of bits-per-word + * selected for the SPI interface. If nbits <= 8, the data is + * packed into uint8_t's; if nbits >8, the data is packed into + * uint16_t's + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifndef CONFIG_SPI_EXCHANGE +static void spi_recvblock(struct spi_dev_s *dev, void *buffer, size_t nwords) +{ + /* spi_exchange can do this. */ + + spi_exchange(dev, NULL, buffer, nwords); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_spiinitialize + * + * Description: + * Initialize the selected SPI port + * + * Input Parameter: + * cs - Chip select number (identifying the "logical" SPI port) + * + * Returned Value: + * Valid SPI device structure reference on success; a NULL on failure + * + ****************************************************************************/ + +struct spi_dev_s *up_spiinitialize(int port) +{ + struct sam_spidev_s *spi; + struct sam_spics_s *spics; + int csno = (port & __SPI_CS_MASK) >> __SPI_CS_SHIFT; + int spino = (port & __SPI_SPI_MASK) >> __SPI_SPI_SHIFT; + irqstate_t flags; +#ifndef CONFIG_SPI_OWNBUS + uint32_t regval; + unsigned int offset; +#endif + + /* The support SAM parts have only a single SPI port */ + + spivdbg("port: %d csno: %d spino: %d\n", port, csno, spino); + DEBUGASSERT(csno >= 0 && csno <= SAM_SPI_NCS); + +#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1) + DEBUGASSERT(spino >= 0 && spino <= 1); +#elif defined(CONFIG_SAMV7_SPI0) + DEBUGASSERT(spino == 0); +#else + DEBUGASSERT(spino == 1); +#endif + + /* Allocate a new state structure for this chip select. NOTE that there + * is no protection if the same chip select is used in two different + * chip select structures. + */ + + spics = (struct sam_spics_s *)zalloc(sizeof(struct sam_spics_s)); + if (!spics) + { + spidbg("ERROR: Failed to allocate a chip select structure\n"); + return NULL; + } + + /* Set up the initial state for this chip select structure. Other fields + * were zeroed by zalloc(). + */ + +#ifdef CONFIG_SAMV7_SPI_DMA + /* Can we do DMA on this peripheral? */ + + spics->candma = spino ? SAMV7_SPI1_DMA : SAMV7_SPI0_DMA; + + /* Pre-allocate DMA channels. These allocations exploit that fact that + * SPI0 is managed by DMAC0 and SPI1 is managed by DMAC1. Hence, + * the SPI number (spino) is the same as the DMAC number. + */ + + if (spics->candma) + { + spics->rxdma = sam_dmachannel(0); + if (!spics->rxdma) + { + spidbg("ERROR: Failed to allocate the RX DMA channel\n"); + spics->candma = false; + } + } + + if (spics->candma) + { + spics->txdma = sam_dmachannel(0); + if (!spics->txdma) + { + spidbg("ERROR: Failed to allocate the TX DMA channel\n"); + sam_dmafree(spics->rxdma); + spics->rxdma = NULL; + spics->candma = false; + } + } +#endif + + /* Select the SPI operations */ + +#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1) + spics->spidev.ops = spino ? &g_spi1ops : &g_spi0ops; +#elif defined(CONFIG_SAMV7_SPI0) + spics->spidev.ops = &g_spi0ops; +#else + spics->spidev.ops = &g_spi1ops; +#endif + + /* Save the chip select and SPI controller numbers */ + + spics->cs = csno; +#if defined(CONFIG_SAMV7_SPI0) || defined(CONFIG_SAMV7_SPI1) + spics->spino = spino; +#endif + + /* Get the SPI device structure associated with the chip select */ + + spi = spi_device(spics); + + /* Has the SPI hardware been initialized? */ + + if (!spi->initialized) + { + /* Enable clocking to the SPI block */ + + flags = irqsave(); +#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1) + if (spino == 0) +#endif +#if defined(CONFIG_SAMV7_SPI0) + { + sam_spi0_enableclk(); + + /* Configure multiplexed pins as connected on the board. Chip + * select pins must be selected by board-specific logic. + */ + + sam_configgpio(GPIO_SPI0_MISO); + sam_configgpio(GPIO_SPI0_MOSI); + sam_configgpio(GPIO_SPI0_SPCK); + } +#endif +#if defined(CONFIG_SAMV7_SPI0) && defined(CONFIG_SAMV7_SPI1) + else +#endif +#if defined(CONFIG_SAMV7_SPI1) + { + sam_spi1_enableclk(); + + /* Configure multiplexed pins as connected on the board. Chip + * select pins must be selected by board-specific logic. + */ + + sam_configgpio(GPIO_SPI1_MISO); + sam_configgpio(GPIO_SPI1_MOSI); + sam_configgpio(GPIO_SPI1_SPCK); + } +#endif + + /* Disable SPI clocking */ + + spi_putreg(spi, SPI_CR_SPIDIS, SAM_SPI_CR_OFFSET); + + /* Execute a software reset of the SPI (twice) */ + + spi_putreg(spi, SPI_CR_SWRST, SAM_SPI_CR_OFFSET); + spi_putreg(spi, SPI_CR_SWRST, SAM_SPI_CR_OFFSET); + irqrestore(flags); + + /* Configure the SPI mode register */ + + spi_putreg(spi, SPI_MR_MSTR | SPI_MR_MODFDIS, SAM_SPI_MR_OFFSET); + + /* And enable the SPI */ + + spi_putreg(spi, SPI_CR_SPIEN, SAM_SPI_CR_OFFSET); + up_mdelay(20); + + /* Flush any pending transfers */ + + (void)spi_getreg(spi, SAM_SPI_SR_OFFSET); + (void)spi_getreg(spi, SAM_SPI_RDR_OFFSET); + +#ifndef CONFIG_SPI_OWNBUS + /* Initialize the SPI semaphore that enforces mutually exclusive + * access to the SPI registers. + */ + + sem_init(&spi->spisem, 0, 1); + spi->initialized = true; +#endif + +#ifdef CONFIG_SAMV7_SPI_DMA + /* Initialize the SPI semaphore that is used to wake up the waiting + * thread when the DMA transfer completes. + */ + + sem_init(&spics->dmawait, 0, 0); + + /* Create a watchdog time to catch DMA timeouts */ + + spics->dmadog = wd_create(); + DEBUGASSERT(spics->dmadog); +#endif + + spi_dumpregs(spi, "After initialization"); + } + +#ifndef CONFIG_SPI_OWNBUS + /* Set to mode=0 and nbits=8 and impossible frequency. It is only + * critical to do this if CONFIG_SPI_OWNBUS is not defined because in + * that case, the SPI will only be reconfigured if there is a change. + */ + + offset = (unsigned int)g_csroffset[csno]; + regval = spi_getreg(spi, offset); + regval &= ~(SPI_CSR_CPOL | SPI_CSR_NCPHA | SPI_CSR_BITS_MASK); + regval |= (SPI_CSR_NCPHA | SPI_CSR_BITS(8)); + spi_putreg(spi, regval, offset); + + spics->nbits = 8; + spivdbg("csr[offset=%02x]=%08x\n", offset, regval); +#endif + + return &spics->spidev; +} +#endif /* CONFIG_SAMV7_SPI0 || CONFIG_SAMV7_SPI1 */ diff --git a/arch/arm/src/samv7/sam_spi.h b/arch/arm/src/samv7/sam_spi.h new file mode 100644 index 0000000000..47afad02fd --- /dev/null +++ b/arch/arm/src/samv7/sam_spi.h @@ -0,0 +1,244 @@ +/**************************************************************************** + * arch/arm/src/samv7/sam_spi.h + * + * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_SAMV7_SAM_SPI_H +#define __ARCH_ARM_SRC_SAMV7_SAM_SPI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The SPI port number used as an input to up_spiinitialize encodes + * information about the SPI controller (0 or 1) and the SPI chip select + * (0-3). + * + * NOTE that this is this is backward compatible with older implementations + * that support only SPI0 and provide only the chip select number to + * up_spiinitialize(). + */ + +#define __SPI_CS_SHIFT (0) /* Bits 0-1: SPI chip select number */ +#define __SPI_CS_MASK (3 << __SPI_CS_SHIFT) +# define __SPI_CS0 (0 << __SPI_CS_SHIFT) +# define __SPI_CS1 (1 << __SPI_CS_SHIFT) +# define __SPI_CS2 (2 << __SPI_CS_SHIFT) +# define __SPI_CS3 (3 << __SPI_CS_SHIFT) +#define __SPI_SPI_SHIFT (2) /* Bit 2: SPI controller number */ +#define __SPI_SPI_MASK (1 << __SPI_SPI_SHIFT) +# define __SPI_SPI0 (0 << __SPI_SPI_SHIFT) /* SPI0 */ +# define __SPI_SPI1 (1 << __SPI_SPI_SHIFT) /* SPI1 */ + +#define SPI0_CS0 (__SPI_SPI0 | __SPI_CS0) +#define SPI0_CS1 (__SPI_SPI0 | __SPI_CS1) +#define SPI0_CS2 (__SPI_SPI0 | __SPI_CS2) +#define SPI0_CS3 (__SPI_SPI0 | __SPI_CS3) + +#define SPI1_CS0 (__SPI_SPI1 | __SPI_CS0) +#define SPI1_CS1 (__SPI_SPI1 | __SPI_CS1) +#define SPI1_CS2 (__SPI_SPI1 | __SPI_CS2) +#define SPI1_CS3 (__SPI_SPI1 | __SPI_CS3) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: sam_spi[0|1]select, sam_spi[0|1]status, and sam_spi[0|1]cmddata + * + * Description: + * These external functions must be provided by board-specific logic. + * They include: + * + * o sam_spi[0|1]select is a functions tomanage the board-specific chip + * selects + * o sam_spi[0|1]status and sam_spi[0|1]cmddata: Implementations of the + * status and cmddata methods of the SPI interface defined by struct + * spi_ops_ (see include/nuttx/spi/spi.h). All other methods including + * up_spiinitialize()) are provided by common SAM3/4 logic. + * + * To use this common SPI logic on your board: + * + * 1. Provide logic in sam_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide sam_spi[0|1]select() and sam_spi[0|1]status() functions in + * our board-specific logic. These functions will perform chip selection + * and status operations using PIOs in the way your board is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * sam_spi[0|1]cmddata() functions in your board-specific logic. This + * function will perform cmd/data selection operations using PIOs in + * the way your board is configured. + * 3. Add a call to up_spiinitialize() in your low level application + * initialization logic + * 4. The handle returned by up_spiinitialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_SPI0 +struct spi_dev_s; +enum spi_dev_e; + +/**************************************************************************** + * Name: sam_spi[0|1]select + * + * Description: + * PIO chip select pins may be programmed by the board specific logic in + * one of two different ways. First, the pins may be programmed as SPI + * peripherals. In that case, the pins are completely controlled by the + * SPI driver. This method still needs to be provided, but it may be only + * a stub. + * + * An alternative way to program the PIO chip select pins is as a normal + * PIO output. In that case, the automatic control of the CS pins is + * bypassed and this function must provide control of the chip select. + * NOTE: In this case, the PIO output pin does *not* have to be the + * same as the NPCS pin normal associated with the chip select number. + * + * Input Parameters: + * dev - SPI device info + * devid - Identifies the (logical) device + * selected - TRUE:Select the device, FALSE:De-select the device + * + * Returned Values: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_SPI0 +void sam_spi0select(enum spi_dev_e devid, bool selected); +#endif +#ifdef CONFIG_SAMV7_SPI1 +void sam_spi1select(enum spi_dev_e devid, bool selected); +#endif + +/**************************************************************************** + * Name: sam_spi[0|1]status + * + * Description: + * Return status information associated with the SPI device. + * + * Input Parameters: + * dev - SPI device info + * devid - Identifies the (logical) device + * + * Returned Values: + * Bit-encoded SPI status (see include/nuttx/spi/spi.h. + * + ****************************************************************************/ + +#ifdef CONFIG_SAMV7_SPI0 +uint8_t sam_spi0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#endif +#ifdef CONFIG_SAMV7_SPI1 +uint8_t sam_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid); +#endif + +/**************************************************************************** + * Name: sam_spi[0|1]cmddata + * + * Description: + * Some SPI devices require an additional control to determine if the SPI + * data being sent is a command or is data. If CONFIG_SPI_CMDDATA then + * this function will be called to different be command and data transfers. + * + * This is often needed, for example, by LCD drivers. Some LCD hardware + * may be configured to use 9-bit data transfers with the 9th bit + * indicating command or data. That same hardware may be configurable, + * instead, to use 8-bit data but to require an additional, board- + * specific PIO control to distinguish command and data. This function + * would be needed in that latter case. + * + * Input Parameters: + * dev - SPI device info + * devid - Identifies the (logical) device + * + * Returned Values: + * Zero on success; a negated errno on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_SPI_CMDDATA +#ifdef CONFIG_SAMV7_SPI0 +int sam_spi0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#ifdef CONFIG_SAMV7_SPI1 +int sam_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd); +#endif +#endif +#endif /* CONFIG_SAMV7_SPI0 */ + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_SAMV7_SAM_SPI_H */