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stm32: nxstyle fixes

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arch/arm/src/stm32/hardware/stm32_adc_v2.h
arch/arm/src/stm32/hardware/stm32_i2c_v2.h
arch/arm/src/stm32/hardware/stm32_tim.h

    * nxstyle fixes, mostly long lines and misaligned comments
This commit is contained in:
Nathan Hartman 2020-05-19 20:06:04 -04:00 committed by patacongo
parent 3b62765edd
commit ca8585e8e7
3 changed files with 250 additions and 246 deletions
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7
arch/arm/src/stm32/hardware/stm32_adc_v2.h
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@ -285,6 +285,7 @@
#endif
/* Register Bitfield Definitions ********************************************************************/
/* ADC interrupt and status register (ISR) and ADC interrupt enable register (IER) */
#define ADC_INT_ARDY (1 << 0) /* Bit 0: ADC ready */
@ -389,7 +390,8 @@
#define ADC_CFGR1_DISCEN (1 << 16) /* Bit 16: Discontinuous mode on regular channels */
#define ADC_CFGR1_DISCNUM_SHIFT (17) /* Bits 17-19: Discontinuous mode channel count */
#define ADC_CFGR1_DISCNUM_MASK (7 << ADC_CFGR1_DISCNUM_SHIFT)
# define ADC_CFGR1_DISCNUM(n) (((n) - 1) << ADC_CFGR1_DISCNUM_SHIFT) /* n = 1..8 channels */
# define ADC_CFGR1_DISCNUM(n) (((n) - 1) << \
ADC_CFGR1_DISCNUM_SHIFT) /* n = 1..8 channels */
#define ADC_CFGR1_JDISCEN (1 << 20) /* Bit 20: Discontinuous mode on injected channels */
#define ADC_CFGR1_JQM (1 << 21) /* Bit 21: JSQR queue mode */
#define ADC_CFGR1_AWD1SGL (1 << 22) /* Bit 22: Enable watchdog on single/all channels */
@ -702,7 +704,8 @@
# define ADC_CCR_DUAL_ALT (9 << ADC_CCR_DUAL_SHIFT) /* Alternate trigger mode only */
#define ADC_CCR_DELAY_SHIFT (8) /* Bits 8-11: Delay between 2 sampling phases */
#define ADC_CCR_DELAY_MASK (15 << ADC_CCR_DELAY_SHIFT)
# define ADC_CCR_DELAY(n) (((n)-1) << ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */
# define ADC_CCR_DELAY(n) (((n) - 1) << \
ADC_CCR_DELAY_SHIFT) /* n * TADCCLK, 1-13 */
#define ADC_CCR_DMACFG (1 << 13) /* Bit 13: DMA configuration (for dual ADC mode) */
#define ADC_CCR_MDMA_SHIFT (14) /* Bits 14-15: Direct memory access mode for dual ADC mode */
#define ADC_CCR_MDMA_MASK (3 << ADC_CCR_MDMA_SHIFT)

1
arch/arm/src/stm32/hardware/stm32_i2c_v2.h
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@ -209,6 +209,7 @@
#define I2C_TIMEOUTR_TEXTEN (1 << 31) /* Bits 31: Extended clock timeout enable */
/* Interrupt and Status register and interrupt clear register */
/* Common interrupt bits */
#define I2C_INT_ADDR (1 << 3) /* Bit 3: Address matched (slave) */

2
arch/arm/src/stm32/hardware/stm32_tim.h
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@ -923,7 +923,7 @@
# define ATIM_BDTR_BK2F_FDTSd326 (14 << ATIM_BDTR_BK2F_SHIFT) /* 1110: fSAMPLING=fDTS/32, N=6 */
# define ATIM_BDTR_BK2F_FDTSd328 (15 << ATIM_BDTR_BK2F_SHIFT) /* 1111: fSAMPLING=fDTS/32, N=8 */
# define ATIM_BDTR_BK2E (1 << 24) /* Bit 24: Break 2 enable */
# define ATIM_BDTR_BK2P (1 << 1525 /* Bit 25:Break 2 polarity */
# define ATIM_BDTR_BK2P (1 << 25) /* Bit 25: Break 2 polarity */
#endif
/* DMA control register */