TMS570: Add VIM header file
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Gregory Nutt
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199
arch/arm/src/tms570/chip/tms570_vim.h
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199
arch/arm/src/tms570/chip/tms570_vim.h
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/****************************************************************************************************
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* arch/arm/src/tms570/chip/tms570_vim.h
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* Vector Intererrupt Manager (VIM) Register Definitions
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* References:
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*
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* TMS570LS04x/03x 16/32-Bit RISC Flash Microcontroller, Technical Reference Manual, Texas
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* Instruments, Literature Number: SPNU517A, September 2013
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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#ifndef __ARCH_ARM_SRC_TMS570_CHIP_TMS570_VIM_H
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#define __ARCH_ARM_SRC_TMS570_CHIP_TMS570_VIM_H
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/****************************************************************************************************
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* Included Files
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****************************************************************************************************/
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#include <nuttx/config.h>
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#include "chip/tms570_memorymap.h"
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/****************************************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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/* Register Offsets *********************************************************************************/
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/* Register Offsets relative to the VIM Parity Frame */
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#define TMS570_VIM_PARFLG_OFFSET 0x00ec /* Interrupt Vector Table Parity Flag Register */
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#define TMS570_VIM_PARCTL_OFFSET 0x00f0 /* Interrupt Vector Table Parity Control Register */
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#define TMS570_VIM_ADDERR_OFFSET 0x00f4 /* Address Parity Error Register */
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#define TMS570_VIM_FBPARERR_OFFSET 0x00f8 /* Fall-Back Address Parity Error Register */
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/* Register Offsets relative to the VIM Frame */
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#define TMS570_VIM_IRQINDEX_OFFSET 0x0000 /* IRQ Index Offset Vector Register */
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#define TMS570_VIM_FIQINDEX_OFFSET 0x0004 /* FIQ Index Offset Vector Register */
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#define TMS570_VIM_FIRQPR0_OFFSET 0x0010 /* FIQ/IRQ Program Control Register 0 */
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#define TMS570_VIM_FIRQPR1_OFFSET 0x0014 /* FIQ/IRQ Program Control Register 1 */
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#define TMS570_VIM_FIRQPR2_OFFSET 0x0018 /* FIQ/IRQ Program Control Register 2 */
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#define TMS570_VIM_INTREQ0_OFFSET 0x0020 /* Pending Interrupt Read Location Register 0 */
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#define TMS570_VIM_INTREQ1_OFFSET 0x0024 /* Pending Interrupt Read Location Register 1 */
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#define TMS570_VIM_INTREQ2_OFFSET 0x0028 /* Pending Interrupt Read Location Register 2 */
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#define TMS570_VIM_REQENASET0_OFFSET 0x0030 /* Interrupt Enable Set Register 0 */
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#define TMS570_VIM_REQENASET1_OFFSET 0x0034 /* Interrupt Enable Set Register 1 */
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#define TMS570_VIM_REQENASET2_OFFSET 0x0038 /* Interrupt Enable Set Register 2 */
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#define TMS570_VIM_REQENACLR0_OFFSET 0x0040 /* Interrupt Enable Clear Register 0 */
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#define TMS570_VIM_REQENACLR1_OFFSET 0x0044 /* Interrupt Enable Clear Register 1 */
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#define TMS570_VIM_REQENACLR2_OFFSET 0x0048 /* Interrupt Enable Clear Register 2 */
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#define TMS570_VIM_WAKEENASET0_OFFSET 0x0050 /* Wake-up Enable Set Register 0 */
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#define TMS570_VIM_WAKEENASET1_OFFSET 0x0054 /* Wake-up Enable Set Register 1 */
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#define TMS570_VIM_WAKEENASET2_OFFSET 0x0058 /* Wake-up Enable Set Register 2 */
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#define TMS570_VIM_WAKEENACLR0_OFFSET 0x0060 /* Wake-up Enable Clear Register 0 */
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#define TMS570_VIM_WAKEENACLR1_OFFSET 0x0064 /* Wake-up Enable Clear Register 1 */
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#define TMS570_VIM_WAKEENACLR2_OFFSET 0x0068 /* Wake-up Enable Clear Register 2 */
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#define TMS570_VIM_IRQVECREG_OFFSET 0x0070 /* IRQ Interrupt Vector Register */
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#define TMS570_VIM_FIQVECREG_OFFSET 0x0074 /* FIQ Interrupt Vector Register */
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#define TMS570_VIM_CAPEVT_OFFSET 0x0078 /* Capture Event Register */
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/* 0x0080-0x00dc VIM Interrupt Control Register */
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#define TMS570_VIM_CHANCTRL_INDEX(n) ((n) >> 2)
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#define TMS570_VIM_CHANCTRL_OFFSET(n) (0x0080 << (TMS570_VIM_CHANCTRL_INDEX(n) << 2))
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/* Register Addresses *******************************************************************************/
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/* VIM Parity Frame Registers */
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#define TMS570_VIM_PARFLG (TMS570_VIMPAR_BASE+TMS570_VIM_PARFLG_OFFSET)
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#define TMS570_VIM_PARCTL (TMS570_VIMPAR_BASE+TMS570_VIM_PARCTL_OFFSET)
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#define TMS570_VIM_ADDERR (TMS570_VIMPAR_BASE+TMS570_VIM_ADDERR_OFFSET)
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#define TMS570_VIM_FBPARERR (TMS570_VIMPAR_BASE+TMS570_VIM_FBPARERR_OFFSET)
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/* VIM Frame Registers */
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#define TMS570_VIM_IRQINDEX (TMS570_VIM_BASE+TMS570_VIM_IRQINDEX_OFFSET)
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#define TMS570_VIM_FIQINDEX (TMS570_VIM_BASE+TMS570_VIM_FIQINDEX_OFFSET)
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#define TMS570_VIM_FIRQPR0 (TMS570_VIM_BASE+TMS570_VIM_FIRQPR0_OFFSET)
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#define TMS570_VIM_FIRQPR1 (TMS570_VIM_BASE+TMS570_VIM_FIRQPR1_OFFSET)
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#define TMS570_VIM_FIRQPR2 (TMS570_VIM_BASE+TMS570_VIM_FIRQPR2_OFFSET)
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#define TMS570_VIM_INTREQ0 (TMS570_VIM_BASE+TMS570_VIM_INTREQ0_OFFSET)
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#define TMS570_VIM_INTREQ1 (TMS570_VIM_BASE+TMS570_VIM_INTREQ1_OFFSET)
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#define TMS570_VIM_INTREQ2 (TMS570_VIM_BASE+TMS570_VIM_INTREQ2_OFFSET)
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#define TMS570_VIM_REQENASET0 (TMS570_VIM_BASE+TMS570_VIM_REQENASET0_OFFSET)
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#define TMS570_VIM_REQENASET1 (TMS570_VIM_BASE+TMS570_VIM_REQENASET1_OFFSET)
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#define TMS570_VIM_REQENASET2 (TMS570_VIM_BASE+TMS570_VIM_REQENASET2_OFFSET)
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#define TMS570_VIM_REQENACLR0 (TMS570_VIM_BASE+TMS570_VIM_REQENACLR0_OFFSET)
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#define TMS570_VIM_REQENACLR1 (TMS570_VIM_BASE+TMS570_VIM_REQENACLR1_OFFSET)
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#define TMS570_VIM_REQENACLR2 (TMS570_VIM_BASE+TMS570_VIM_REQENACLR2_OFFSET)
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#define TMS570_VIM_WAKEENASET0 (TMS570_VIM_BASE+TMS570_VIM_WAKEENASET0_OFFSET)
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#define TMS570_VIM_WAKEENASET1 (TMS570_VIM_BASE+TMS570_VIM_WAKEENASET1_OFFSET)
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#define TMS570_VIM_WAKEENASET2 (TMS570_VIM_BASE+TMS570_VIM_WAKEENASET2_OFFSET)
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#define TMS570_VIM_WAKEENACLR0 (TMS570_VIM_BASE+TMS570_VIM_WAKEENACLR0_OFFSET)
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#define TMS570_VIM_WAKEENACLR1 (TMS570_VIM_BASE+TMS570_VIM_WAKEENACLR1_OFFSET)
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#define TMS570_VIM_WAKEENACLR2 (TMS570_VIM_BASE+TMS570_VIM_WAKEENACLR2_OFFSET)
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#define TMS570_VIM_IRQVECREG (TMS570_VIM_BASE+TMS570_VIM_IRQVECREG_OFFSET)
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#define TMS570_VIM_FIQVECREG (TMS570_VIM_BASE+TMS570_VIM_FIQVECREG_OFFSET)
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#define TMS570_VIM_CAPEVT (TMS570_VIM_BASE+TMS570_VIM_CAPEVT_OFFSET)
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/* 0x0080-0x00dc VIM Interrupt Control Register */
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#define TMS570_VIM_CHANCTRL(n) (TMS570_VIM_BASE+TMS570_VIM_CHANCTRL_OFFSET(n))
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/* Register Bit-Field Definitions *******************************************************************/
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/* Interrupt Vector Table Parity Flag Register */
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#define VIM_PARFLG_
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/* Interrupt Vector Table Parity Control Register */
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#define VIM_PARCTL_
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/* Address Parity Error Register */
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#define VIM_ADDERR_
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/* Fall-Back Address Parity Error Register */
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#define VIM_FBPARERR_
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/* IRQ Index Offset Vector Register */
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#define VIM_IRQINDEX_
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/* FIQ Index Offset Vector Register */
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#define VIM_FIQINDEX_
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/* FIQ/IRQ Program Control Register 0 */
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#define VIM_FIRQPR0_
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/* FIQ/IRQ Program Control Register 1 */
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#define VIM_FIRQPR1_
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/* FIQ/IRQ Program Control Register 2 */
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#define VIM_FIRQPR2_
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/* Pending Interrupt Read Location Register 0 */
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#define VIM_INTREQ0_
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/* Pending Interrupt Read Location Register 1 */
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#define VIM_INTREQ1_
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/* Pending Interrupt Read Location Register 2 */
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#define VIM_INTREQ2_
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/* Interrupt Enable Set Register 0 */
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#define VIM_REQENASET0_
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/* Interrupt Enable Set Register 1 */
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#define VIM_REQENASET1_
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/* Interrupt Enable Set Register 2 */
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#define VIM_REQENASET2_
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/* Interrupt Enable Clear Register 0 */
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#define VIM_REQENACLR0_
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/* Interrupt Enable Clear Register 1 */
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#define VIM_REQENACLR1_
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/* Interrupt Enable Clear Register 2 */
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#define VIM_REQENACLR2_
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/* Wake-up Enable Set Register 0 */
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#define VIM_WAKEENASET0_
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/* Wake-up Enable Set Register 1 */
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#define VIM_WAKEENASET1_
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/* Wake-up Enable Set Register 2 */
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#define VIM_WAKEENASET2_
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/* Wake-up Enable Clear Register 0 */
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#define VIM_WAKEENACLR0_
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/* Wake-up Enable Clear Register 1 */
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#define VIM_WAKEENACLR1_
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/* Wake-up Enable Clear Register 2 */
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#define VIM_WAKEENACLR2_
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/* IRQ Interrupt Vector Register */
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#define VIM_IRQVECREG_
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/* FIQ Interrupt Vector Register */
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#define VIM_FIQVECREG_
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/* Capture Event Register */
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#define VIM_CAPEVT_
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/* 0x0080-0x00dc VIM Interrupt Control Register */
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#define VIM_CHANCTRL_SHIFT(n) (((n) & 3) << 3)
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#define VIM_CHANCTRL_MASK(n) (0xff << VIM_CHANCTRL_SHIFT(n))
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# define VIM_CHANCTRL(n,v) ((uint32_t)(v) << VIM_CHANCTRL_SHIFT(n))
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#endif /* __ARCH_ARM_SRC_TMS570_CHIP_TMS570_VIM_H */
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@ -245,8 +245,6 @@ void arm_boot(void)
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#ifdef CONFIG_TMS570_SELFTEST
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/* Perform PBIST on all dual-port memories */
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tms570_memtest_start(PBIST_RINFOL_ESRAM1_RAM)
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tms570_memtest_start(PBIST_RINFOL_VIM_RAM
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#ifdef CONFIG_TMS570_DCAN1
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| PBIST_RINFOL_DCAN1_RAM
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