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armv7amr/v8m:Modify hardcodes to macro definitions and update commit.

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Signed-off-by: chenrun1 <chenrun1@xiaomi.com>
This commit is contained in:
chenrun1 2023-07-13 15:24:33 +08:00 committed by Xiang Xiao
parent 9c2bc0edbe
commit cafbbb1ded
4 changed files with 18 additions and 6 deletions
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8
arch/arm/src/armv7-a/cp15_cacheops.c
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@ -28,6 +28,12 @@
#include "cp15_cacheops.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define NVIC_CSSELR_IND (1 << 0)
/****************************************************************************
* Private Functions
****************************************************************************/
@ -52,7 +58,7 @@ static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways,
csselr = CP15_GET(CSSELR);
CP15_SET(CSSELR, (csselr & ~0x01) | (icache & 0x01));
CP15_SET(CSSELR, (csselr & ~NVIC_CSSELR_IND) | (icache & NVIC_CSSELR_IND));
ccsidr = CP15_GET(CCSIDR);

4
arch/arm/src/armv7-m/nvic.h
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@ -679,8 +679,8 @@
/* Cache Size Selection Register (Cortex-M7) */
#define NVIC_CSSELR_IND (1 << 0) /* Bit 0: Selects either instruction or data cache */
# define NVIC_CSSELR_IND_ICACHE (1 << 0) /* 0=Instruction Cache */
# define NVIC_CSSELR_IND_DCACHE (0 << 0) /* 1=Data Cache */
# define NVIC_CSSELR_IND_ICACHE (1 << 0) /* 1=Instruction Cache */
# define NVIC_CSSELR_IND_DCACHE (0 << 0) /* 0=Data Cache */
#define NVIC_CSSELR_LEVEL_SHIFT (1) /* Bit 1-3: Selects cache level */
#define NVIC_CSSELR_LEVEL_MASK (7 << NVIC_CSSELR_LEVEL_SHIFT)

8
arch/arm/src/armv7-r/cp15_cacheops.c
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@ -28,6 +28,12 @@
#include "cp15_cacheops.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define NVIC_CSSELR_IND (1 << 0)
/****************************************************************************
* Private Functions
****************************************************************************/
@ -52,7 +58,7 @@ static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways,
csselr = CP15_GET(CSSELR);
CP15_SET(CSSELR, (csselr & ~0x01) | (icache & 0x01));
CP15_SET(CSSELR, (csselr & ~NVIC_CSSELR_IND) | (icache & NVIC_CSSELR_IND));
ccsidr = CP15_GET(CCSIDR);

4
arch/arm/src/armv8-m/nvic.h
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@ -778,8 +778,8 @@
/* Cache Size Selection Register */
#define NVIC_CSSELR_IND (1 << 0) /* Bit 0: Selects either instruction or data cache */
# define NVIC_CSSELR_IND_ICACHE (1 << 0) /* 0=Instruction Cache */
# define NVIC_CSSELR_IND_DCACHE (0 << 0) /* 1=Data Cache */
# define NVIC_CSSELR_IND_ICACHE (1 << 0) /* 1=Instruction Cache */
# define NVIC_CSSELR_IND_DCACHE (0 << 0) /* 0=Data Cache */
#define NVIC_CSSELR_LEVEL_SHIFT (1) /* Bit 1-3: Selects cache level */
#define NVIC_CSSELR_LEVEL_MASK (7 << NVIC_CSSELR_LEVEL_SHIFT)