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arch/: Clean up some naming and spacing.

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This commit is contained in:
Gregory Nutt 2018-06-20 15:38:06 -06:00
parent 49ec86ddb1
commit cb374e6e62
54 changed files with 1519 additions and 1541 deletions
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16
arch/arm/include/bcm2708/irq.h
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@ -186,24 +186,24 @@
#define IPR2_IRQ_LAST BCM_IRQ_AVSPMON /* IRQ of last defined bit */
#define IPR2_BIT_LAST (31) /* Last defined bit */
/* Number of interrupts */
/* Number of hardware interrupt vectors */
#define NR_INTERRUPTS (IPR2_IRQ_LAST + 1)
#define BCM_IRQ_NVECTORS (IPR2_IRQ_LAST + 1)
/* Second level GPIO interrupts */
#ifdef CONFIG_BCM2708_GPIO_IRQ
# define BCM_IRQ_GPIO(n) (NR_INTERRUPTS + (n)) /* IRQ number of pin n */
# define BCM_IRQ_GPIO0_FIRST (NR_INTERRUPTS) /* IRQ number of first GPIO0 interrupt */
# define BCM_IRQ_GPIO1_FIRST (NR_INTERRUPTS + 32) /* IRQ number of first GPIO1 interrupt */
# define NR_GPIOINTS (54)
# define BCM_IRQ_GPIO(n) (BCM_IRQ_NVECTORS + (n)) /* IRQ number of pin n */
# define BCM_IRQ_GPIO0_FIRST (BCM_IRQ_NVECTORS) /* IRQ number of first GPIO0 interrupt */
# define BCM_IRQ_GPIO1_FIRST (BCM_IRQ_NVECTORS + 32) /* IRQ number of first GPIO1 interrupt */
# define BCM_IRQ_NGPIOINTS (54)
#else
# define NR_GPIOINTS (0)
# define BCM_IRQ_NGPIOINTS (0)
#endif
/* Number of supported IRQs */
#define NR_IRQS (NR_INTERRUPTS + NR_GPIOINTS)
#define NR_IRQS (BCM_IRQ_NVECTORS + BCM_IRQ_NGPIOINTS)
#else
# error Unrecognized BCM2708 chip

2
arch/arm/include/efm32/efm32g_irq.h
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@ -90,7 +90,7 @@
#define EFM32_IRQ_AES (EFM32_IRQ_INTERRUPTS + 29) /* 29 AES */
#define EFM32_PERIPH_INTS (30)
#define NR_VECTORS (EFM32_IRQ_INTERRUPTS + EFM32_PERIPH_INTS)
#define EFM32_IRQ_NVECTORS (EFM32_IRQ_INTERRUPTS + EFM32_PERIPH_INTS)
/****************************************************************************
* Public Types

2
arch/arm/include/efm32/efm32gg_irq.h
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@ -99,7 +99,7 @@
#define EFM32_IRQ_EMI (EFM32_IRQ_INTERRUPTS + 38)
#define EFM32_PERIPH_INTS (39)
#define NR_VECTORS (EFM32_IRQ_INTERRUPTS + EFM32_PERIPH_INTS)
#define EFM32_IRQ_NVECTORS (EFM32_IRQ_INTERRUPTS + EFM32_PERIPH_INTS)
/****************************************************************************
* Public Types

2
arch/arm/include/efm32/efm32tg_irq.h
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@ -83,7 +83,7 @@
#define EFM32_IRQ_AES (EFM32_IRQ_INTERRUPTS + 22)
#define EFM32_PERIPH_INTS (23)
#define NR_VECTORS (EFM32_IRQ_INTERRUPTS + EFM32_PERIPH_INTS)
#define EFM32_IRQ_NVECTORS (EFM32_IRQ_INTERRUPTS + EFM32_PERIPH_INTS)
/****************************************************************************
* Public Types

36
arch/arm/include/efm32/irq.h
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@ -95,26 +95,26 @@
* 16-additional interrupts generated from a second level of decoding.
*/
# define EFM32_IRQ_EXTI0 (NR_VECTORS + 0) /* Port[n], pin0 external interrupt */
# define EFM32_IRQ_EXTI1 (NR_VECTORS + 1) /* Port[n], pin1 external interrupt */
# define EFM32_IRQ_EXTI2 (NR_VECTORS + 2) /* Port[n], pin2 external interrupt */
# define EFM32_IRQ_EXTI3 (NR_VECTORS + 3) /* Port[n], pin3 external interrupt */
# define EFM32_IRQ_EXTI4 (NR_VECTORS + 4) /* Port[n], pin4 external interrupt */
# define EFM32_IRQ_EXTI5 (NR_VECTORS + 5) /* Port[n], pin5 external interrupt */
# define EFM32_IRQ_EXTI6 (NR_VECTORS + 6) /* Port[n], pin6 external interrupt */
# define EFM32_IRQ_EXTI7 (NR_VECTORS + 7) /* Port[n], pin7 external interrupt */
# define EFM32_IRQ_EXTI8 (NR_VECTORS + 8) /* Port[n], pin8 external interrupt */
# define EFM32_IRQ_EXTI9 (NR_VECTORS + 9) /* Port[n], pin9 external interrupt */
# define EFM32_IRQ_EXTI10 (NR_VECTORS + 10) /* Port[n], pin10 external interrupt */
# define EFM32_IRQ_EXTI11 (NR_VECTORS + 11) /* Port[n], pin11 external interrupt */
# define EFM32_IRQ_EXTI12 (NR_VECTORS + 12) /* Port[n], pin12 external interrupt */
# define EFM32_IRQ_EXTI13 (NR_VECTORS + 13) /* Port[n], pin13 external interrupt */
# define EFM32_IRQ_EXTI14 (NR_VECTORS + 14) /* Port[n], pin14 external interrupt */
# define EFM32_IRQ_EXTI15 (NR_VECTORS + 15) /* Port[n], pin15 external interrupt */
# define EFM32_IRQ_EXTI0 (EFM32_IRQ_NVECTORS + 0) /* Port[n], pin0 external interrupt */
# define EFM32_IRQ_EXTI1 (EFM32_IRQ_NVECTORS + 1) /* Port[n], pin1 external interrupt */
# define EFM32_IRQ_EXTI2 (EFM32_IRQ_NVECTORS + 2) /* Port[n], pin2 external interrupt */
# define EFM32_IRQ_EXTI3 (EFM32_IRQ_NVECTORS + 3) /* Port[n], pin3 external interrupt */
# define EFM32_IRQ_EXTI4 (EFM32_IRQ_NVECTORS + 4) /* Port[n], pin4 external interrupt */
# define EFM32_IRQ_EXTI5 (EFM32_IRQ_NVECTORS + 5) /* Port[n], pin5 external interrupt */
# define EFM32_IRQ_EXTI6 (EFM32_IRQ_NVECTORS + 6) /* Port[n], pin6 external interrupt */
# define EFM32_IRQ_EXTI7 (EFM32_IRQ_NVECTORS + 7) /* Port[n], pin7 external interrupt */
# define EFM32_IRQ_EXTI8 (EFM32_IRQ_NVECTORS + 8) /* Port[n], pin8 external interrupt */
# define EFM32_IRQ_EXTI9 (EFM32_IRQ_NVECTORS + 9) /* Port[n], pin9 external interrupt */
# define EFM32_IRQ_EXTI10 (EFM32_IRQ_NVECTORS + 10) /* Port[n], pin10 external interrupt */
# define EFM32_IRQ_EXTI11 (EFM32_IRQ_NVECTORS + 11) /* Port[n], pin11 external interrupt */
# define EFM32_IRQ_EXTI12 (EFM32_IRQ_NVECTORS + 12) /* Port[n], pin12 external interrupt */
# define EFM32_IRQ_EXTI13 (EFM32_IRQ_NVECTORS + 13) /* Port[n], pin13 external interrupt */
# define EFM32_IRQ_EXTI14 (EFM32_IRQ_NVECTORS + 14) /* Port[n], pin14 external interrupt */
# define EFM32_IRQ_EXTI15 (EFM32_IRQ_NVECTORS + 15) /* Port[n], pin15 external interrupt */
# define NR_IRQS (NR_VECTORS + 16) /* Total number of interrupts */
# define NR_IRQS (EFM32_IRQ_NVECTORS + 16) /* Total number of interrupts */
#else
# define NR_IRQS NR_VECTORS /* Total number of interrupts */
# define NR_IRQS EFM32_IRQ_NVECTORS /* Total number of interrupts */
#endif
/************************************************************************************

1
arch/arm/include/imxrt/imxrt105x_irq.h
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@ -482,7 +482,6 @@
/* Total number of IRQ numbers **********************************************************/
#define NR_VECTORS IMXRT_IRQ_NIRQS
#define NR_IRQS (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT + IMXRT_GPIO_NIRQS)
/****************************************************************************************

224
arch/arm/include/kinetis/kinetis_k20irq.h
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@ -1,4 +1,4 @@
/*****************************************************************************
/**************************************************************************************
* arch/arm/include/kinetis/kinetis_k20irq.h
*
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
@ -32,7 +32,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
*************************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
@ -41,15 +41,15 @@
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_K20IRQ_H
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_K20IRQ_H
/*****************************************************************************
/**************************************************************************************
* Included Files
****************************************************************************/
*************************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
/**************************************************************************************
* Pre-processor Definitions
****************************************************************************/
*************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
@ -60,123 +60,123 @@
*
* External interrupts (vectors >= 16)
*
* K20 Family ****************************************************************
* K20 Family *************************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale
* document K20P64M72SF1RM
*/
#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0 transfer complete */
#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1 transfer complete */
#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2 transfer complete */
#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3 transfer complete */
#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4 transfer complete */
#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5 transfer complete */
#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6 transfer complete */
#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7 transfer complete */
#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8 transfer complete */
#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9 transfer complete */
#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10 transfer complete */
#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11 transfer complete */
#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12 transfer complete */
#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13 transfer complete */
#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14 transfer complete */
#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15 transfer complete */
#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-15 */
#define KINETIS_IRQ_RESVD17 (KINETIS_IRQ_FIRST+17) /* 17: Reserved */
#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */
#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */
#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage
* detect, low-voltage warning */
#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */
#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog */
#define KINETIS_IRQ_RESVD23 (KINETIS_IRQ_FIRST+23) /* 23: Reserved */
#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */
#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */
#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */
#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */
#define KINETIS_IRQ_RESVD28 (KINETIS_IRQ_FIRST+28) /* 28: Reserved */
#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+29) /* 29: CAN0 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+30) /* 30: CAN0 Bus Off */
#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+31) /* 31: CAN0 Error */
#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+32) /* 32: CAN0 Transmit Warning */
#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+33) /* 33: CAN0 Receive Warning */
#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+34) /* 34: CAN0 Wake UP */
#define KINETIS_IRQ_I2S0TX (KINETIS_IRQ_FIRST+35) /* 35: I2S0 Transmit */
#define KINETIS_IRQ_I2S0TX (KINETIS_IRQ_FIRST+36) /* 36: I2S0 Receive */
#define KINETIS_IRQ_RESVD37 (KINETIS_IRQ_FIRST+37) /* 37: Reserved */
#define KINETIS_IRQ_RESVD38 (KINETIS_IRQ_FIRST+38) /* 38: Reserved */
#define KINETIS_IRQ_RESVD39 (KINETIS_IRQ_FIRST+39) /* 39: Reserved */
#define KINETIS_IRQ_RESVD40 (KINETIS_IRQ_FIRST+40) /* 40: Reserved */
#define KINETIS_IRQ_RESVD41 (KINETIS_IRQ_FIRST+41) /* 41: Reserved */
#define KINETIS_IRQ_RESVD42 (KINETIS_IRQ_FIRST+42) /* 42: Reserved */
#define KINETIS_IRQ_RESVD43 (KINETIS_IRQ_FIRST+43) /* 43: Reserved */
#define KINETIS_IRQ_UART0L (KINETIS_IRQ_FIRST+44) /* 44: UART0 LON */
#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+45) /* 45: UART0 status */
#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+46) /* 46: UART0 error */
#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+47) /* 47: UART1 status */
#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+48) /* 48: UART1 error */
#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+49) /* 49: UART2 status */
#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+50) /* 50: UART2 error */
#define KINETIS_IRQ_RESVD51 (KINETIS_IRQ_FIRST+51) /* 51: Reserved */
#define KINETIS_IRQ_RESVD52 (KINETIS_IRQ_FIRST+52) /* 52: Reserved */
#define KINETIS_IRQ_RESVD53 (KINETIS_IRQ_FIRST+53) /* 53: Reserved */
#define KINETIS_IRQ_RESVD54 (KINETIS_IRQ_FIRST+54) /* 54: Reserved */
#define KINETIS_IRQ_RESVD55 (KINETIS_IRQ_FIRST+55) /* 55: Reserved */
#define KINETIS_IRQ_RESVD56 (KINETIS_IRQ_FIRST+56) /* 56: Reserved */
#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+57) /* 57: ADC0 */
#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+58) /* 58: ADC1 */
#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+59) /* 59: CMP0 */
#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+60) /* 60: CMP1 */
#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+61) /* 61: CMP2 */
#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+62) /* 62: FTM0 all sources */
#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+63) /* 63: FTM1 all sources */
#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+64) /* 64: FTM2 all sources */
#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+65) /* 65: CMT */
#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+66) /* 66: RTC alarm interrupt */
#define KINETIS_IRQ_RTCS (KINETIS_IRQ_FIRST+67) /* 67: RTC Seconds interrupt */
#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+68) /* 68: PIT channel 0 */
#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+69) /* 69: PIT channel 1 */
#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+70) /* 70: PIT channel 2 */
#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+71) /* 71: PIT channel 3 */
#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+72) /* 72: PDB */
#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+73) /* 73: USB OTG */
#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+74) /* 74: USB charger detect */
#define KINETIS_IRQ_RESVD75 (KINETIS_IRQ_FIRST+75) /* 75: Reserved */
#define KINETIS_IRQ_RESVD76 (KINETIS_IRQ_FIRST+76) /* 76: Reserved */
#define KINETIS_IRQ_RESVD77 (KINETIS_IRQ_FIRST+77) /* 77: Reserved */
#define KINETIS_IRQ_RESVD78 (KINETIS_IRQ_FIRST+78) /* 78: Reserved */
#define KINETIS_IRQ_RESVD79 (KINETIS_IRQ_FIRST+79) /* 79: Reserved */
#define KINETIS_IRQ_RESVD80 (KINETIS_IRQ_FIRST+80) /* 80: Reserved */
#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+81) /* 81: DAC0 */
#define KINETIS_IRQ_RESVD82 (KINETIS_IRQ_FIRST+82) /* 82: Reserved */
#define KINETIS_IRQ_TSI (KINETIS_IRQ_FIRST+83) /* 83: TSI all sources */
#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+84) /* 84: MCG */
#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+85) /* 85: Low power timer */
#define KINETIS_IRQ_RESVD86 (KINETIS_IRQ_FIRST+86) /* 86: Reserved */
#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+87) /* 87: Pin detect port A */
#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+88) /* 88: Pin detect port B */
#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+89) /* 89: Pin detect port C */
#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+90) /* 90: Pin detect port D */
#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+91) /* 91: Pin detect port E */
#define KINETIS_IRQ_RESVD92 (KINETIS_IRQ_FIRST+92) /* 92: Reserved */
#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST+93) /* 93: Reserved */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+94) /* 94: Software interrupt */
#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST + 0) /* 0: DMA channel 0 transfer complete */
#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST + 1) /* 1: DMA channel 1 transfer complete */
#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST + 2) /* 2: DMA channel 2 transfer complete */
#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST + 3) /* 3: DMA channel 3 transfer complete */
#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST + 4) /* 4: DMA channel 4 transfer complete */
#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST + 5) /* 5: DMA channel 5 transfer complete */
#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST + 6) /* 6: DMA channel 6 transfer complete */
#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST + 7) /* 7: DMA channel 7 transfer complete */
#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST + 8) /* 8: DMA channel 8 transfer complete */
#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST + 9) /* 9: DMA channel 9 transfer complete */
#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST + 10) /* 10: DMA channel 10 transfer complete */
#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST + 11) /* 11: DMA channel 11 transfer complete */
#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST + 12) /* 12: DMA channel 12 transfer complete */
#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST + 13) /* 13: DMA channel 13 transfer complete */
#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST + 14) /* 14: DMA channel 14 transfer complete */
#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST + 15) /* 15: DMA channel 15 transfer complete */
#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST + 16) /* 16: DMA error interrupt channels 0-15 */
#define KINETIS_IRQ_RESVD17 (KINETIS_IRQ_FIRST + 17) /* 17: Reserved */
#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST + 18) /* 18: Flash memory command complete */
#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST + 19) /* 19: Flash memory read collision */
#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST + 20) /* 20: Mode Controller low-voltage
* detect, low-voltage warning */
#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST + 21) /* 21: LLWU Normal Low Leakage Wakeup */
#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST + 22) /* 22: Watchdog */
#define KINETIS_IRQ_RESVD23 (KINETIS_IRQ_FIRST + 23) /* 23: Reserved */
#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST + 24) /* 24: I2C0 */
#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST + 25) /* 25: I2C1 */
#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST + 26) /* 26: SPI0 all sources */
#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST + 27) /* 27: SPI1 all sources */
#define KINETIS_IRQ_RESVD28 (KINETIS_IRQ_FIRST + 28) /* 28: Reserved */
#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST + 29) /* 29: CAN0 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST + 30) /* 30: CAN0 Bus Off */
#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST + 31) /* 31: CAN0 Error */
#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST + 32) /* 32: CAN0 Transmit Warning */
#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST + 33) /* 33: CAN0 Receive Warning */
#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST + 34) /* 34: CAN0 Wake UP */
#define KINETIS_IRQ_I2S0TX (KINETIS_IRQ_FIRST + 35) /* 35: I2S0 Transmit */
#define KINETIS_IRQ_I2S0TX (KINETIS_IRQ_FIRST + 36) /* 36: I2S0 Receive */
#define KINETIS_IRQ_RESVD37 (KINETIS_IRQ_FIRST + 37) /* 37: Reserved */
#define KINETIS_IRQ_RESVD38 (KINETIS_IRQ_FIRST + 38) /* 38: Reserved */
#define KINETIS_IRQ_RESVD39 (KINETIS_IRQ_FIRST + 39) /* 39: Reserved */
#define KINETIS_IRQ_RESVD40 (KINETIS_IRQ_FIRST + 40) /* 40: Reserved */
#define KINETIS_IRQ_RESVD41 (KINETIS_IRQ_FIRST + 41) /* 41: Reserved */
#define KINETIS_IRQ_RESVD42 (KINETIS_IRQ_FIRST + 42) /* 42: Reserved */
#define KINETIS_IRQ_RESVD43 (KINETIS_IRQ_FIRST + 43) /* 43: Reserved */
#define KINETIS_IRQ_UART0L (KINETIS_IRQ_FIRST + 44) /* 44: UART0 LON */
#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST + 45) /* 45: UART0 status */
#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST + 46) /* 46: UART0 error */
#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST + 47) /* 47: UART1 status */
#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST + 48) /* 48: UART1 error */
#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST + 49) /* 49: UART2 status */
#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST + 50) /* 50: UART2 error */
#define KINETIS_IRQ_RESVD51 (KINETIS_IRQ_FIRST + 51) /* 51: Reserved */
#define KINETIS_IRQ_RESVD52 (KINETIS_IRQ_FIRST + 52) /* 52: Reserved */
#define KINETIS_IRQ_RESVD53 (KINETIS_IRQ_FIRST + 53) /* 53: Reserved */
#define KINETIS_IRQ_RESVD54 (KINETIS_IRQ_FIRST + 54) /* 54: Reserved */
#define KINETIS_IRQ_RESVD55 (KINETIS_IRQ_FIRST + 55) /* 55: Reserved */
#define KINETIS_IRQ_RESVD56 (KINETIS_IRQ_FIRST + 56) /* 56: Reserved */
#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST + 57) /* 57: ADC0 */
#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST + 58) /* 58: ADC1 */
#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST + 59) /* 59: CMP0 */
#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST + 60) /* 60: CMP1 */
#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST + 61) /* 61: CMP2 */
#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST + 62) /* 62: FTM0 all sources */
#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST + 63) /* 63: FTM1 all sources */
#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST + 64) /* 64: FTM2 all sources */
#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST + 65) /* 65: CMT */
#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST + 66) /* 66: RTC alarm interrupt */
#define KINETIS_IRQ_RTCS (KINETIS_IRQ_FIRST + 67) /* 67: RTC Seconds interrupt */
#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST + 68) /* 68: PIT channel 0 */
#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST + 69) /* 69: PIT channel 1 */
#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST + 70) /* 70: PIT channel 2 */
#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST + 71) /* 71: PIT channel 3 */
#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST + 72) /* 72: PDB */
#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST + 73) /* 73: USB OTG */
#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST + 74) /* 74: USB charger detect */
#define KINETIS_IRQ_RESVD75 (KINETIS_IRQ_FIRST + 75) /* 75: Reserved */
#define KINETIS_IRQ_RESVD76 (KINETIS_IRQ_FIRST + 76) /* 76: Reserved */
#define KINETIS_IRQ_RESVD77 (KINETIS_IRQ_FIRST + 77) /* 77: Reserved */
#define KINETIS_IRQ_RESVD78 (KINETIS_IRQ_FIRST + 78) /* 78: Reserved */
#define KINETIS_IRQ_RESVD79 (KINETIS_IRQ_FIRST + 79) /* 79: Reserved */
#define KINETIS_IRQ_RESVD80 (KINETIS_IRQ_FIRST + 80) /* 80: Reserved */
#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST + 81) /* 81: DAC0 */
#define KINETIS_IRQ_RESVD82 (KINETIS_IRQ_FIRST + 82) /* 82: Reserved */
#define KINETIS_IRQ_TSI (KINETIS_IRQ_FIRST + 83) /* 83: TSI all sources */
#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST + 84) /* 84: MCG */
#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST + 85) /* 85: Low power timer */
#define KINETIS_IRQ_RESVD86 (KINETIS_IRQ_FIRST + 86) /* 86: Reserved */
#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST + 87) /* 87: Pin detect port A */
#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST + 88) /* 88: Pin detect port B */
#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST + 89) /* 89: Pin detect port C */
#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST + 90) /* 90: Pin detect port D */
#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST + 91) /* 91: Pin detect port E */
#define KINETIS_IRQ_RESVD92 (KINETIS_IRQ_FIRST + 92) /* 92: Reserved */
#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST + 93) /* 93: Reserved */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST + 94) /* 94: Software interrupt */
#define NR_INTERRUPTS 95 /* 95 Non core IRQs*/
#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 111 vectors */
#define KINETIS_IRQ_NEXTINTS 95 /* 95 Non core IRQs */
#define KINETIS_IRQ_NVECTORS (KINETIS_IRQ_FIRST + KINETIS_IRQ_NEXTINTS) /* 111 vectors */
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS KINETIS_IRQ_NVECTORS
/*****************************************************************************
/**************************************************************************************
* Public Types
****************************************************************************/
*************************************************************************************/
/*****************************************************************************
/**************************************************************************************
* Public Data
****************************************************************************/
*************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@ -187,9 +187,9 @@ extern "C"
#define EXTERN extern
#endif
/*****************************************************************************
/**************************************************************************************
* Public Functions
****************************************************************************/
*************************************************************************************/
#undef EXTERN
#ifdef __cplusplus

224
arch/arm/include/kinetis/kinetis_k28irq.h
View File

@ -65,132 +65,132 @@
* document K28P210M150SF5RM
*/
#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0, 16 transfer complete */
#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1, 17 transfer complete */
#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2, 18 transfer complete */
#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3, 19 transfer complete */
#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4, 20 transfer complete */
#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5, 21 transfer complete */
#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6, 11 transfer complete */
#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7, 23 transfer complete */
#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8, 24 transfer complete */
#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9, 25 transfer complete */
#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST + 0) /* 0: DMA channel 0, 16 transfer complete */
#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST + 1) /* 1: DMA channel 1, 17 transfer complete */
#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST + 2) /* 2: DMA channel 2, 18 transfer complete */
#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST + 3) /* 3: DMA channel 3, 19 transfer complete */
#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST + 4) /* 4: DMA channel 4, 20 transfer complete */
#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST + 5) /* 5: DMA channel 5, 21 transfer complete */
#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST + 6) /* 6: DMA channel 6, 11 transfer complete */
#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST + 7) /* 7: DMA channel 7, 23 transfer complete */
#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST + 8) /* 8: DMA channel 8, 24 transfer complete */
#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST + 9) /* 9: DMA channel 9, 25 transfer complete */
#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10, 26 transfer complete */
#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11, 27 transfer complete */
#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12, 28 transfer complete */
#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13, 29 transfer complete */
#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14, 30 transfer complete */
#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15, 31 transfer complete */
#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-31 */
#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST+17) /* 17: MCM or RDC interrupt */
#define KINETIS_IRQ_RDC (KINETIS_IRQ_FIRST+17) /* 17: MCM or RDC interrupt */
#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */
#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */
#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST + 10) /* 10: DMA channel 10, 26 transfer complete */
#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST + 11) /* 11: DMA channel 11, 27 transfer complete */
#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST + 12) /* 12: DMA channel 12, 28 transfer complete */
#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST + 13) /* 13: DMA channel 13, 29 transfer complete */
#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST + 14) /* 14: DMA channel 14, 30 transfer complete */
#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST + 15) /* 15: DMA channel 15, 31 transfer complete */
#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST + 16) /* 16: DMA error interrupt channels 0-31 */
#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST + 17) /* 17: MCM or RDC interrupt */
#define KINETIS_IRQ_RDC (KINETIS_IRQ_FIRST + 17) /* 17: MCM or RDC interrupt */
#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST + 18) /* 18: Flash memory command complete */
#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST + 19) /* 19: Flash memory read collision */
#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage
* detect, low-voltage warning */
#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */
#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog or EWM */
#define KINETIS_IRQ_RNGB (KINETIS_IRQ_FIRST+23) /* 23: True random number generator (TRNG) */
#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */
#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */
#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */
#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */
#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST+28) /* 28: 12S0 Transmit */
#define KINETIS_IRQ_I2S1 (KINETIS_IRQ_FIRST+29) /* 29: 12S0 Receive */
#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST + 20) /* 20: Mode Controller low-voltage
* detect, low-voltage warning */
#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST + 21) /* 21: LLWU Normal Low Leakage Wakeup */
#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST + 22) /* 22: Watchdog or EWM */
#define KINETIS_IRQ_RNGB (KINETIS_IRQ_FIRST + 23) /* 23: True random number generator (TRNG) */
#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST + 24) /* 24: I2C0 */
#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST + 25) /* 25: I2C1 */
#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST + 26) /* 26: SPI0 all sources */
#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST + 27) /* 27: SPI1 all sources */
#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST + 28) /* 28: 12S0 Transmit */
#define KINETIS_IRQ_I2S1 (KINETIS_IRQ_FIRST + 29) /* 29: 12S0 Receive */
#define KINETIS_IRQ_LPUART0 (KINETIS_IRQ_FIRST+30) /* 30: LPUART0 Status and error */
#define KINETIS_IRQ_LPUART1 (KINETIS_IRQ_FIRST+31) /* 31: LPUART1 Status and error */
#define KINETIS_IRQ_LPUART2 (KINETIS_IRQ_FIRST+32) /* 32: LPUART2 Status and error */
#define KINETIS_IRQ_LPUART3 (KINETIS_IRQ_FIRST+33) /* 33: LPUART3 Status and error */
#define KINETIS_IRQ_LPUART4 (KINETIS_IRQ_FIRST+34) /* 34: LPUART4 Status and error */
#define KINETIS_IRQ_RESVD35 (KINETIS_IRQ_FIRST+35) /* 35: Reserved */
#define KINETIS_IRQ_RESVD36 (KINETIS_IRQ_FIRST+36) /* 36: Reserved */
#define KINETIS_IRQ_RESVD37 (KINETIS_IRQ_FIRST+37) /* 37: Reserved */
#define KINETIS_IRQ_RESVD38 (KINETIS_IRQ_FIRST+38) /* 38: Reserved */
#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+39) /* 39: ADC0 */
#define KINETIS_IRQ_LPUART0 (KINETIS_IRQ_FIRST + 30) /* 30: LPUART0 Status and error */
#define KINETIS_IRQ_LPUART1 (KINETIS_IRQ_FIRST + 31) /* 31: LPUART1 Status and error */
#define KINETIS_IRQ_LPUART2 (KINETIS_IRQ_FIRST + 32) /* 32: LPUART2 Status and error */
#define KINETIS_IRQ_LPUART3 (KINETIS_IRQ_FIRST + 33) /* 33: LPUART3 Status and error */
#define KINETIS_IRQ_LPUART4 (KINETIS_IRQ_FIRST + 34) /* 34: LPUART4 Status and error */
#define KINETIS_IRQ_RESVD35 (KINETIS_IRQ_FIRST + 35) /* 35: Reserved */
#define KINETIS_IRQ_RESVD36 (KINETIS_IRQ_FIRST + 36) /* 36: Reserved */
#define KINETIS_IRQ_RESVD37 (KINETIS_IRQ_FIRST + 37) /* 37: Reserved */
#define KINETIS_IRQ_RESVD38 (KINETIS_IRQ_FIRST + 38) /* 38: Reserved */
#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST + 39) /* 39: ADC0 */
#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+40) /* 40: CMP0 */
#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+41) /* 41: CMP1 */
#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+42) /* 42: FTM0 all sources */
#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+43) /* 43: FTM1 all sources */
#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+44) /* 44: FTM2 all sources */
#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+45) /* 45: CMT */
#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+46) /* 46: RTC alarm interrupt */
#define KINETIS_IRQ_RTCS (KINETIS_IRQ_FIRST+47) /* 47: RTC seconds interrupt */
#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+48) /* 48: PIT channel 0 */
#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+49) /* 49: PIT channel 1 */
#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST + 40) /* 40: CMP0 */
#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST + 41) /* 41: CMP1 */
#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST + 42) /* 42: FTM0 all sources */
#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST + 43) /* 43: FTM1 all sources */
#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST + 44) /* 44: FTM2 all sources */
#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST + 45) /* 45: CMT */
#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST + 46) /* 46: RTC alarm interrupt */
#define KINETIS_IRQ_RTCS (KINETIS_IRQ_FIRST + 47) /* 47: RTC seconds interrupt */
#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST + 48) /* 48: PIT channel 0 */
#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST + 49) /* 49: PIT channel 1 */
#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+50) /* 50: PIT channel 2 */
#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+51) /* 51: PIT channel 3 */
#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+52) /* 52: PDB */
#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+53) /* 53: USB OTG */
#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+54) /* 54: USB charger detect */
#define KINETIS_IRQ_RESVD55 (KINETIS_IRQ_FIRST+55) /* 55: Reserved */
#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+56) /* 56: DAC0 */
#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+57) /* 57: MCG */
#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+58) /* 58: Low power timer LPTMR0 and LPTMR1 */
#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+59) /* 59: Pin detect port A */
#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST + 50) /* 50: PIT channel 2 */
#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST + 51) /* 51: PIT channel 3 */
#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST + 52) /* 52: PDB */
#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST + 53) /* 53: USB OTG */
#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST + 54) /* 54: USB charger detect */
#define KINETIS_IRQ_RESVD55 (KINETIS_IRQ_FIRST + 55) /* 55: Reserved */
#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST + 56) /* 56: DAC0 */
#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST + 57) /* 57: MCG */
#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST + 58) /* 58: Low power timer LPTMR0 and LPTMR1 */
#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST + 59) /* 59: Pin detect port A */
#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+60) /* 60: Pin detect port B */
#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+61) /* 61: Pin detect port C */
#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+62) /* 62: Pin detect port D */
#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+63) /* 63: Pin detect port E */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+64) /* 64: Software interrupt */
#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST+65) /* 65: SPI2 all sources */
#define KINETIS_IRQ_SPI3 (KINETIS_IRQ_FIRST+66) /* 66: SPI3 all sources */
#define KINETIS_IRQ_RESVD67 (KINETIS_IRQ_FIRST+67) /* 67: Reserved */
#define KINETIS_IRQ_I2S1TX (KINETIS_IRQ_FIRST+68) /* 68: I2S1 Transmit */
#define KINETIS_IRQ_I2S1RX (KINETIS_IRQ_FIRST+69) /* 69: I2S1 Receive */
#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST + 60) /* 60: Pin detect port B */
#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST + 61) /* 61: Pin detect port C */
#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST + 62) /* 62: Pin detect port D */
#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST + 63) /* 63: Pin detect port E */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST + 64) /* 64: Software interrupt */
#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST + 65) /* 65: SPI2 all sources */
#define KINETIS_IRQ_SPI3 (KINETIS_IRQ_FIRST + 66) /* 66: SPI3 all sources */
#define KINETIS_IRQ_RESVD67 (KINETIS_IRQ_FIRST + 67) /* 67: Reserved */
#define KINETIS_IRQ_I2S1TX (KINETIS_IRQ_FIRST + 68) /* 68: I2S1 Transmit */
#define KINETIS_IRQ_I2S1RX (KINETIS_IRQ_FIRST + 69) /* 69: I2S1 Receive */
#define KINETIS_IRQ_FLEXIO (KINETIS_IRQ_FIRST+70) /* 70: FlexIO */
#define KINETIS_IRQ_FTM3 (KINETIS_IRQ_FIRST+71) /* 71: FTM3 all sources */
#define KINETIS_IRQ_RESVD72 (KINETIS_IRQ_FIRST+72) /* 72: Reserved */
#define KINETIS_IRQ_RESVD73 (KINETIS_IRQ_FIRST+73) /* 73: Reserved */
#define KINETIS_IRQ_I2C2 (KINETIS_IRQ_FIRST+74) /* 74: I2C2 */
#define KINETIS_IRQ_RESVD75 (KINETIS_IRQ_FIRST+75) /* 75: Reserved */
#define KINETIS_IRQ_RESVD76 (KINETIS_IRQ_FIRST+76) /* 76: Reserved */
#define KINETIS_IRQ_RESVD77 (KINETIS_IRQ_FIRST+77) /* 77: Reserved */
#define KINETIS_IRQ_RESVD78 (KINETIS_IRQ_FIRST+78) /* 78: Reserved */
#define KINETIS_IRQ_RESVD79 (KINETIS_IRQ_FIRST+79) /* 79: Reserved */
#define KINETIS_IRQ_FLEXIO (KINETIS_IRQ_FIRST + 70) /* 70: FlexIO */
#define KINETIS_IRQ_FTM3 (KINETIS_IRQ_FIRST + 71) /* 71: FTM3 all sources */
#define KINETIS_IRQ_RESVD72 (KINETIS_IRQ_FIRST + 72) /* 72: Reserved */
#define KINETIS_IRQ_RESVD73 (KINETIS_IRQ_FIRST + 73) /* 73: Reserved */
#define KINETIS_IRQ_I2C2 (KINETIS_IRQ_FIRST + 74) /* 74: I2C2 */
#define KINETIS_IRQ_RESVD75 (KINETIS_IRQ_FIRST + 75) /* 75: Reserved */
#define KINETIS_IRQ_RESVD76 (KINETIS_IRQ_FIRST + 76) /* 76: Reserved */
#define KINETIS_IRQ_RESVD77 (KINETIS_IRQ_FIRST + 77) /* 77: Reserved */
#define KINETIS_IRQ_RESVD78 (KINETIS_IRQ_FIRST + 78) /* 78: Reserved */
#define KINETIS_IRQ_RESVD79 (KINETIS_IRQ_FIRST + 79) /* 79: Reserved */
#define KINETIS_IRQ_RESVD80 (KINETIS_IRQ_FIRST+80) /* 80: Reserved */
#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST+81) /* 81: SDHC */
#define KINETIS_IRQ_RESVD82 (KINETIS_IRQ_FIRST+82) /* 82: Reserved */
#define KINETIS_IRQ_RESVD83 (KINETIS_IRQ_FIRST+83) /* 83: Reserved */
#define KINETIS_IRQ_RESVD84 (KINETIS_IRQ_FIRST+84) /* 84: Reserved */
#define KINETIS_IRQ_RESVD85 (KINETIS_IRQ_FIRST+85) /* 85: Reserved */
#define KINETIS_IRQ_RESVD86 (KINETIS_IRQ_FIRST+86) /* 86: Reserved */
#define KINETIS_IRQ_RESVD87 (KINETIS_IRQ_FIRST+87) /* 87: Reserved */
#define KINETIS_IRQ_TPM1 (KINETIS_IRQ_FIRST+88) /* 88: TPM1 */
#define KINETIS_IRQ_TPM2 (KINETIS_IRQ_FIRST+89) /* 89: TPM2 */
#define KINETIS_IRQ_RESVD80 (KINETIS_IRQ_FIRST + 80) /* 80: Reserved */
#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST + 81) /* 81: SDHC */
#define KINETIS_IRQ_RESVD82 (KINETIS_IRQ_FIRST + 82) /* 82: Reserved */
#define KINETIS_IRQ_RESVD83 (KINETIS_IRQ_FIRST + 83) /* 83: Reserved */
#define KINETIS_IRQ_RESVD84 (KINETIS_IRQ_FIRST + 84) /* 84: Reserved */
#define KINETIS_IRQ_RESVD85 (KINETIS_IRQ_FIRST + 85) /* 85: Reserved */
#define KINETIS_IRQ_RESVD86 (KINETIS_IRQ_FIRST + 86) /* 86: Reserved */
#define KINETIS_IRQ_RESVD87 (KINETIS_IRQ_FIRST + 87) /* 87: Reserved */
#define KINETIS_IRQ_TPM1 (KINETIS_IRQ_FIRST + 88) /* 88: TPM1 */
#define KINETIS_IRQ_TPM2 (KINETIS_IRQ_FIRST + 89) /* 89: TPM2 */
#define KINETIS_IRQ_USBHSDCD (KINETIS_IRQ_FIRST+90) /* 90: USBHS DCD or USBHS Phy modules */
#define KINETIS_IRQ_I2C3 (KINETIS_IRQ_FIRST+91) /* 91: I2C3 */
#define KINETIS_IRQ_RESVD92 (KINETIS_IRQ_FIRST+92) /* 92: Reserved */
#define KINETIS_IRQ_USB1OTG (KINETIS_IRQ_FIRST+93) /* 93: USB1 OTG*/
#define KINETIS_IRQ_RESVD94 (KINETIS_IRQ_FIRST+94) /* 94: Reserved */
#define KINETIS_IRQ_RESVD95 (KINETIS_IRQ_FIRST+95) /* 95: Reserved */
#define KINETIS_IRQ_RESVD96 (KINETIS_IRQ_FIRST+96) /* 96: Reserved */
#define KINETIS_IRQ_RESVD97 (KINETIS_IRQ_FIRST+97) /* 97: Reserved */
#define KINETIS_IRQ_RESVD98 (KINETIS_IRQ_FIRST+98) /* 98: Reserved */
#define KINETIS_IRQ_RESVD99 (KINETIS_IRQ_FIRST+99) /* 99: Reserved */
#define KINETIS_IRQ_USBHSDCD (KINETIS_IRQ_FIRST + 90) /* 90: USBHS DCD or USBHS Phy modules */
#define KINETIS_IRQ_I2C3 (KINETIS_IRQ_FIRST + 91) /* 91: I2C3 */
#define KINETIS_IRQ_RESVD92 (KINETIS_IRQ_FIRST + 92) /* 92: Reserved */
#define KINETIS_IRQ_USB1OTG (KINETIS_IRQ_FIRST + 93) /* 93: USB1 OTG*/
#define KINETIS_IRQ_RESVD94 (KINETIS_IRQ_FIRST + 94) /* 94: Reserved */
#define KINETIS_IRQ_RESVD95 (KINETIS_IRQ_FIRST + 95) /* 95: Reserved */
#define KINETIS_IRQ_RESVD96 (KINETIS_IRQ_FIRST + 96) /* 96: Reserved */
#define KINETIS_IRQ_RESVD97 (KINETIS_IRQ_FIRST + 97) /* 97: Reserved */
#define KINETIS_IRQ_RESVD98 (KINETIS_IRQ_FIRST + 98) /* 98: Reserved */
#define KINETIS_IRQ_RESVD99 (KINETIS_IRQ_FIRST + 99) /* 99: Reserved */
#define KINETIS_QSPI0 (KINETIS_IRQ_FIRST+100) /* 100: QSPI0 all sources */
#define KINETIS_IRQ_RESVD101 (KINETIS_IRQ_FIRST+101) /* 101: Reserved */
#define KINETIS_IRQ_RESVD102 (KINETIS_IRQ_FIRST+102) /* 102: Reserved */
#define KINETIS_IRQ_RESVD103 (KINETIS_IRQ_FIRST+103) /* 103: Reserved */
#define KINETIS_IRQ_RESVD104 (KINETIS_IRQ_FIRST+104) /* 104: Reserved */
#define KINETIS_IRQ_RESVD105 (KINETIS_IRQ_FIRST+105) /* 105: Reserved */
#define KINETIS_IRQ_RESVD106 (KINETIS_IRQ_FIRST+106) /* 106: Reserved */
#define KINETIS_QSPI0 (KINETIS_IRQ_FIRST + 100) /* 100: QSPI0 all sources */
#define KINETIS_IRQ_RESVD101 (KINETIS_IRQ_FIRST + 101) /* 101: Reserved */
#define KINETIS_IRQ_RESVD102 (KINETIS_IRQ_FIRST + 102) /* 102: Reserved */
#define KINETIS_IRQ_RESVD103 (KINETIS_IRQ_FIRST + 103) /* 103: Reserved */
#define KINETIS_IRQ_RESVD104 (KINETIS_IRQ_FIRST + 104) /* 104: Reserved */
#define KINETIS_IRQ_RESVD105 (KINETIS_IRQ_FIRST + 105) /* 105: Reserved */
#define KINETIS_IRQ_RESVD106 (KINETIS_IRQ_FIRST + 106) /* 106: Reserved */
#define NR_INTERRUPTS 107 /* 107 Non core IRQs*/
#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 123 vectors */
#define KINETIS_IRQ_NEXTINTS 107 /* 107 Non core IRQs */
#define KINETIS_IRQ_NVECTORS (KINETIS_IRQ_FIRST + KINETIS_IRQ_NEXTINTS) /* 123 vectors */
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS KINETIS_IRQ_NVECTORS
/*********************************************************************************************
* Public Types

224
arch/arm/include/kinetis/kinetis_k40irq.h
View File

@ -1,4 +1,4 @@
/*****************************************************************************
/*************************************************************************************
* arch/arm/include/kinetis/kinetis_k40irq.h
*
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
@ -32,7 +32,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
************************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
@ -41,15 +41,15 @@
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_40KIRQ_H
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_40KIRQ_H
/*****************************************************************************
/*************************************************************************************
* Included Files
****************************************************************************/
************************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
/*************************************************************************************
* Pre-processor Definitions
****************************************************************************/
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
@ -60,123 +60,123 @@
*
* External interrupts (vectors >= 16)
*
* K40 Family ****************************************************************
* K40 Family ************************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale
* document K40P144M100SF2RM
*/
#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0 transfer complete */
#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1 transfer complete */
#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2 transfer complete */
#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3 transfer complete */
#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4 transfer complete */
#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5 transfer complete */
#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6 transfer complete */
#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7 transfer complete */
#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8 transfer complete */
#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9 transfer complete */
#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10 transfer complete */
#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11 transfer complete */
#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12 transfer complete */
#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13 transfer complete */
#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14 transfer complete */
#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15 transfer complete */
#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-15 */
#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST+17) /* 17: MCM Normal interrupt */
#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */
#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */
#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage
* detect, low-voltage warning */
#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */
#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog */
#define KINETIS_IRQ_RESVD23 (KINETIS_IRQ_FIRST+23) /* 23: Reserved */
#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */
#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */
#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */
#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */
#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST+28) /* 28: SPI2 all sources */
#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+29) /* 29: CAN0 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+30) /* 30: CAN0 Bus Off */
#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+31) /* 31: CAN0 Error */
#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+32) /* 32: CAN0 Transmit Warning */
#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+33) /* 33: CAN0 Receive Warning */
#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+34) /* 34: CAN0 Wake UP */
#define KINETIS_IRQ_RESVD35 (KINETIS_IRQ_FIRST+35) /* 35: Reserved */
#define KINETIS_IRQ_RESVD36 (KINETIS_IRQ_FIRST+36) /* 36: Reserved */
#define KINETIS_IRQ_CAN1MB (KINETIS_IRQ_FIRST+37) /* 37: CAN1 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN1BO (KINETIS_IRQ_FIRST+38) /* 38: CAN1 Bus Off */
#define KINETIS_IRQ_CAN1ERR (KINETIS_IRQ_FIRST+39) /* 39: CAN1 Error */
#define KINETIS_IRQ_CAN1TW (KINETIS_IRQ_FIRST+40) /* 40: CAN1 Transmit Warning */
#define KINETIS_IRQ_CAN1RW (KINETIS_IRQ_FIRST+41) /* 41: CAN1 Receive Warning */
#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST+42) /* 42: CAN1 Wake UP */
#define KINETIS_IRQ_RESVD43 (KINETIS_IRQ_FIRST+43) /* 43: Reserved */
#define KINETIS_IRQ_RESVD44 (KINETIS_IRQ_FIRST+44) /* 44: Reserved */
#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+45) /* 45: UART0 status */
#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+46) /* 46: UART0 error */
#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+47) /* 47: UART1 status */
#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+48) /* 48: UART1 error */
#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+49) /* 49: UART2 status */
#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+50) /* 50: UART2 error */
#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST+51) /* 51: UART3 status */
#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST+52) /* 52: UART3 error */
#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST+53) /* 53: UART4 status */
#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST+54) /* 54: UART4 error */
#define KINETIS_IRQ_UART5S (KINETIS_IRQ_FIRST+55) /* 55: UART5 status */
#define KINETIS_IRQ_UART5E (KINETIS_IRQ_FIRST+56) /* 56: UART5 error */
#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+57) /* 57: ADC0 */
#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+58) /* 58: ADC1 */
#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+59) /* 59: CMP0 */
#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+60) /* 60: CMP1 */
#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+61) /* 61: CMP2 */
#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+62) /* 62: FTM0 all sources */
#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+63) /* 63: FTM1 all sources */
#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+64) /* 64: FTM2 all sources */
#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+65) /* 65: CMT */
#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+66) /* 66: RTC alarm interrupt */
#define KINETIS_IRQ_RESVD67 (KINETIS_IRQ_FIRST+67) /* 67: Reserved */
#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+68) /* 68: PIT channel 0 */
#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+69) /* 69: PIT channel 1 */
#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+70) /* 70: PIT channel 2 */
#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+71) /* 71: PIT channel 3 */
#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+72) /* 72: PDB */
#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+73) /* 73: USB OTG */
#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+74) /* 74: USB charger detect */
#define KINETIS_IRQ_RESVD75 (KINETIS_IRQ_FIRST+75) /* 75: Reserved */
#define KINETIS_IRQ_RESVD76 (KINETIS_IRQ_FIRST+76) /* 76: Reserved */
#define KINETIS_IRQ_RESVD77 (KINETIS_IRQ_FIRST+77) /* 77: Reserved */
#define KINETIS_IRQ_RESVD78 (KINETIS_IRQ_FIRST+78) /* 78: Reserved */
#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST+79) /* 79: I2S0 */
#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST+80) /* 80: SDHC */
#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+81) /* 81: DAC0 */
#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST+82) /* 82: DAC1 */
#define KINETIS_IRQ_TSI (KINETIS_IRQ_FIRST+83) /* 83: TSI all sources */
#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+84) /* 84: MCG */
#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+85) /* 85: Low power timer */
#define KINETIS_IRQ_SLCD (KINETIS_IRQ_FIRST+86) /* 86: Segment LCD all sources */
#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+87) /* 87: Pin detect port A */
#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+88) /* 88: Pin detect port B */
#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+89) /* 89: Pin detect port C */
#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+90) /* 90: Pin detect port D */
#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+91) /* 91: Pin detect port E */
#define KINETIS_IRQ_RESVD92 (KINETIS_IRQ_FIRST+92) /* 92: Reserved */
#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST+93) /* 93: Reserved */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+94) /* 94: Software interrupt */
#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST + 0) /* 0: DMA channel 0 transfer complete */
#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST + 1) /* 1: DMA channel 1 transfer complete */
#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST + 2) /* 2: DMA channel 2 transfer complete */
#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST + 3) /* 3: DMA channel 3 transfer complete */
#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST + 4) /* 4: DMA channel 4 transfer complete */
#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST + 5) /* 5: DMA channel 5 transfer complete */
#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST + 6) /* 6: DMA channel 6 transfer complete */
#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST + 7) /* 7: DMA channel 7 transfer complete */
#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST + 8) /* 8: DMA channel 8 transfer complete */
#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST + 9) /* 9: DMA channel 9 transfer complete */
#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST + 10) /* 10: DMA channel 10 transfer complete */
#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST + 11) /* 11: DMA channel 11 transfer complete */
#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST + 12) /* 12: DMA channel 12 transfer complete */
#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST + 13) /* 13: DMA channel 13 transfer complete */
#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST + 14) /* 14: DMA channel 14 transfer complete */
#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST + 15) /* 15: DMA channel 15 transfer complete */
#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST + 16) /* 16: DMA error interrupt channels 0-15 */
#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST + 17) /* 17: MCM Normal interrupt */
#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST + 18) /* 18: Flash memory command complete */
#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST + 19) /* 19: Flash memory read collision */
#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST + 20) /* 20: Mode Controller low-voltage
* detect, low-voltage warning */
#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST + 21) /* 21: LLWU Normal Low Leakage Wakeup */
#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST + 22) /* 22: Watchdog */
#define KINETIS_IRQ_RESVD23 (KINETIS_IRQ_FIRST + 23) /* 23: Reserved */
#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST + 24) /* 24: I2C0 */
#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST + 25) /* 25: I2C1 */
#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST + 26) /* 26: SPI0 all sources */
#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST + 27) /* 27: SPI1 all sources */
#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST + 28) /* 28: SPI2 all sources */
#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST + 29) /* 29: CAN0 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST + 30) /* 30: CAN0 Bus Off */
#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST + 31) /* 31: CAN0 Error */
#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST + 32) /* 32: CAN0 Transmit Warning */
#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST + 33) /* 33: CAN0 Receive Warning */
#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST + 34) /* 34: CAN0 Wake UP */
#define KINETIS_IRQ_RESVD35 (KINETIS_IRQ_FIRST + 35) /* 35: Reserved */
#define KINETIS_IRQ_RESVD36 (KINETIS_IRQ_FIRST + 36) /* 36: Reserved */
#define KINETIS_IRQ_CAN1MB (KINETIS_IRQ_FIRST + 37) /* 37: CAN1 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN1BO (KINETIS_IRQ_FIRST + 38) /* 38: CAN1 Bus Off */
#define KINETIS_IRQ_CAN1ERR (KINETIS_IRQ_FIRST + 39) /* 39: CAN1 Error */
#define KINETIS_IRQ_CAN1TW (KINETIS_IRQ_FIRST + 40) /* 40: CAN1 Transmit Warning */
#define KINETIS_IRQ_CAN1RW (KINETIS_IRQ_FIRST + 41) /* 41: CAN1 Receive Warning */
#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST + 42) /* 42: CAN1 Wake UP */
#define KINETIS_IRQ_RESVD43 (KINETIS_IRQ_FIRST + 43) /* 43: Reserved */
#define KINETIS_IRQ_RESVD44 (KINETIS_IRQ_FIRST + 44) /* 44: Reserved */
#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST + 45) /* 45: UART0 status */
#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST + 46) /* 46: UART0 error */
#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST + 47) /* 47: UART1 status */
#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST + 48) /* 48: UART1 error */
#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST + 49) /* 49: UART2 status */
#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST + 50) /* 50: UART2 error */
#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST + 51) /* 51: UART3 status */
#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST + 52) /* 52: UART3 error */
#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST + 53) /* 53: UART4 status */
#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST + 54) /* 54: UART4 error */
#define KINETIS_IRQ_UART5S (KINETIS_IRQ_FIRST + 55) /* 55: UART5 status */
#define KINETIS_IRQ_UART5E (KINETIS_IRQ_FIRST + 56) /* 56: UART5 error */
#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST + 57) /* 57: ADC0 */
#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST + 58) /* 58: ADC1 */
#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST + 59) /* 59: CMP0 */
#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST + 60) /* 60: CMP1 */
#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST + 61) /* 61: CMP2 */
#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST + 62) /* 62: FTM0 all sources */
#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST + 63) /* 63: FTM1 all sources */
#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST + 64) /* 64: FTM2 all sources */
#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST + 65) /* 65: CMT */
#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST + 66) /* 66: RTC alarm interrupt */
#define KINETIS_IRQ_RESVD67 (KINETIS_IRQ_FIRST + 67) /* 67: Reserved */
#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST + 68) /* 68: PIT channel 0 */
#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST + 69) /* 69: PIT channel 1 */
#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST + 70) /* 70: PIT channel 2 */
#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST + 71) /* 71: PIT channel 3 */
#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST + 72) /* 72: PDB */
#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST + 73) /* 73: USB OTG */
#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST + 74) /* 74: USB charger detect */
#define KINETIS_IRQ_RESVD75 (KINETIS_IRQ_FIRST + 75) /* 75: Reserved */
#define KINETIS_IRQ_RESVD76 (KINETIS_IRQ_FIRST + 76) /* 76: Reserved */
#define KINETIS_IRQ_RESVD77 (KINETIS_IRQ_FIRST + 77) /* 77: Reserved */
#define KINETIS_IRQ_RESVD78 (KINETIS_IRQ_FIRST + 78) /* 78: Reserved */
#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST + 79) /* 79: I2S0 */
#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST + 80) /* 80: SDHC */
#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST + 81) /* 81: DAC0 */
#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST + 82) /* 82: DAC1 */
#define KINETIS_IRQ_TSI (KINETIS_IRQ_FIRST + 83) /* 83: TSI all sources */
#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST + 84) /* 84: MCG */
#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST + 85) /* 85: Low power timer */
#define KINETIS_IRQ_SLCD (KINETIS_IRQ_FIRST + 86) /* 86: Segment LCD all sources */
#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST + 87) /* 87: Pin detect port A */
#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST + 88) /* 88: Pin detect port B */
#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST + 89) /* 89: Pin detect port C */
#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST + 90) /* 90: Pin detect port D */
#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST + 91) /* 91: Pin detect port E */
#define KINETIS_IRQ_RESVD92 (KINETIS_IRQ_FIRST + 92) /* 92: Reserved */
#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST + 93) /* 93: Reserved */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST + 94) /* 94: Software interrupt */
#define NR_INTERRUPTS 95 /* 95 Non core IRQs*/
#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 111 vectors */
#define KINETIS_IRQ_NEXTINTS 95 /* 95 Non core IRQs */
#define KINETIS_IRQ_NVECTORS (KINETIS_IRQ_FIRST + KINETIS_IRQ_NEXTINTS) /* 111 vectors */
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS KINETIS_IRQ_NVECTORS
/*****************************************************************************
/*************************************************************************************
* Public Types
****************************************************************************/
************************************************************************************/
/*****************************************************************************
/*************************************************************************************
* Public Data
****************************************************************************/
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@ -187,9 +187,9 @@ extern "C"
#define EXTERN extern
#endif
/*****************************************************************************
/*************************************************************************************
* Public Functions
****************************************************************************/
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus

224
arch/arm/include/kinetis/kinetis_k60irq.h
View File

@ -1,4 +1,4 @@
/*****************************************************************************
/************************************************************************************
* arch/arm/include/kinetis/kinetis_k60irq.h
*
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
@ -32,7 +32,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
************************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
@ -41,15 +41,15 @@
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_60KIRQ_H
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_60KIRQ_H
/*****************************************************************************
/************************************************************************************
* Included Files
****************************************************************************/
************************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
/************************************************************************************
* Pre-processor Definitions
****************************************************************************/
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
@ -60,123 +60,123 @@
*
* External interrupts (vectors >= 16)
*
* K60 Family ****************************************************************
* K60 Family ************************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale
* document K60P144M100SF2RM
*/
#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0 transfer complete */
#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1 transfer complete */
#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2 transfer complete */
#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3 transfer complete */
#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4 transfer complete */
#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5 transfer complete */
#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6 transfer complete */
#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7 transfer complete */
#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8 transfer complete */
#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9 transfer complete */
#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10 transfer complete */
#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11 transfer complete */
#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12 transfer complete */
#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13 transfer complete */
#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14 transfer complete */
#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15 transfer complete */
#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-15 */
#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST+17) /* 17: MCM Normal interrupt */
#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */
#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */
#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage
* detect, low-voltage warning */
#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */
#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog */
#define KINETIS_IRQ_RNGB (KINETIS_IRQ_FIRST+23) /* 23: Random number generator */
#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */
#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */
#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */
#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */
#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST+28) /* 28: SPI2 all sources */
#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+29) /* 29: CAN0 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+30) /* 30: CAN0 Bus Off */
#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+31) /* 31: CAN0 Error */
#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+32) /* 32: CAN0 Transmit Warning */
#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+33) /* 33: CAN0 Receive Warning */
#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+34) /* 34: CAN0 Wake UP */
#define KINETIS_IRQ_RESVD35 (KINETIS_IRQ_FIRST+35) /* 35: Reserved */
#define KINETIS_IRQ_RESVD36 (KINETIS_IRQ_FIRST+36) /* 36: Reserved */
#define KINETIS_IRQ_CAN1MB (KINETIS_IRQ_FIRST+37) /* 37: CAN1 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN1BO (KINETIS_IRQ_FIRST+38) /* 38: CAN1 Bus Off */
#define KINETIS_IRQ_CAN1ERR (KINETIS_IRQ_FIRST+39) /* 39: CAN1 Error */
#define KINETIS_IRQ_CAN1TW (KINETIS_IRQ_FIRST+40) /* 40: CAN1 Transmit Warning */
#define KINETIS_IRQ_CAN1RW (KINETIS_IRQ_FIRST+41) /* 41: CAN1 Receive Warning */
#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST+42) /* 42: CAN1 Wake UP */
#define KINETIS_IRQ_RESVD43 (KINETIS_IRQ_FIRST+43) /* 43: Reserved */
#define KINETIS_IRQ_RESVD44 (KINETIS_IRQ_FIRST+44) /* 44: Reserved */
#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+45) /* 45: UART0 status */
#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+46) /* 46: UART0 error */
#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+47) /* 47: UART1 status */
#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+48) /* 48: UART1 error */
#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+49) /* 49: UART2 status */
#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+50) /* 50: UART2 error */
#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST+51) /* 51: UART3 status */
#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST+52) /* 52: UART3 error */
#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST+53) /* 53: UART4 status */
#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST+54) /* 54: UART4 error */
#define KINETIS_IRQ_UART5S (KINETIS_IRQ_FIRST+55) /* 55: UART5 status */
#define KINETIS_IRQ_UART5E (KINETIS_IRQ_FIRST+56) /* 56: UART5 error */
#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+57) /* 57: ADC0 */
#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+58) /* 58: ADC1 */
#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+59) /* 59: CMP0 */
#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+60) /* 60: CMP1 */
#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+61) /* 61: CMP2 */
#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+62) /* 62: FTM0 all sources */
#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+63) /* 63: FTM1 all sources */
#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+64) /* 64: FTM2 all sources */
#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+65) /* 65: CMT */
#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+66) /* 66: RTC alarm interrupt */
#define KINETIS_IRQ_RESVD67 (KINETIS_IRQ_FIRST+67) /* 67: Reserved */
#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+68) /* 68: PIT channel 0 */
#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+69) /* 69: PIT channel 1 */
#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+70) /* 70: PIT channel 2 */
#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+71) /* 71: PIT channel 3 */
#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+72) /* 72: PDB */
#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+73) /* 73: USB OTG */
#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+74) /* 74: USB charger detect */
#define KINETIS_IRQ_EMACTMR (KINETIS_IRQ_FIRST+75) /* 75: Ethernet MAC IEEE 1588 timer interrupt */
#define KINETIS_IRQ_EMACTX (KINETIS_IRQ_FIRST+76) /* 76: Ethernet MAC transmit interrupt */
#define KINETIS_IRQ_EMACRX (KINETIS_IRQ_FIRST+77) /* 77: Ethernet MAC receive interrupt */
#define KINETIS_IRQ_EMACMISC (KINETIS_IRQ_FIRST+78) /* 78: Ethernet MAC error and misc interrupt */
#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST+79) /* 79: I2S0 */
#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST+80) /* 80: SDHC */
#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+81) /* 81: DAC0 */
#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST+82) /* 82: DAC1 */
#define KINETIS_IRQ_TSI (KINETIS_IRQ_FIRST+83) /* 83: TSI all sources */
#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+84) /* 84: MCG */
#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+85) /* 85: Low power timer */
#define KINETIS_IRQ_RESVD86 (KINETIS_IRQ_FIRST+86) /* 86: Reserved */
#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+87) /* 87: Pin detect port A */
#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+88) /* 88: Pin detect port B */
#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+89) /* 89: Pin detect port C */
#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+90) /* 90: Pin detect port D */
#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+91) /* 91: Pin detect port E */
#define KINETIS_IRQ_RESVD92 (KINETIS_IRQ_FIRST+92) /* 92: Reserved */
#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST+93) /* 93: Reserved */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+94) /* 94: Software interrupt */
#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST + 0) /* 0: DMA channel 0 transfer complete */
#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST + 1) /* 1: DMA channel 1 transfer complete */
#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST + 2) /* 2: DMA channel 2 transfer complete */
#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST + 3) /* 3: DMA channel 3 transfer complete */
#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST + 4) /* 4: DMA channel 4 transfer complete */
#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST + 5) /* 5: DMA channel 5 transfer complete */
#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST + 6) /* 6: DMA channel 6 transfer complete */
#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST + 7) /* 7: DMA channel 7 transfer complete */
#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST + 8) /* 8: DMA channel 8 transfer complete */
#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST + 9) /* 9: DMA channel 9 transfer complete */
#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST + 10) /* 10: DMA channel 10 transfer complete */
#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST + 11) /* 11: DMA channel 11 transfer complete */
#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST + 12) /* 12: DMA channel 12 transfer complete */
#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST + 13) /* 13: DMA channel 13 transfer complete */
#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST + 14) /* 14: DMA channel 14 transfer complete */
#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST + 15) /* 15: DMA channel 15 transfer complete */
#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST + 16) /* 16: DMA error interrupt channels 0-15 */
#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST + 17) /* 17: MCM Normal interrupt */
#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST + 18) /* 18: Flash memory command complete */
#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST + 19) /* 19: Flash memory read collision */
#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST + 20) /* 20: Mode Controller low-voltage
* detect, low-voltage warning */
#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST + 21) /* 21: LLWU Normal Low Leakage Wakeup */
#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST + 22) /* 22: Watchdog */
#define KINETIS_IRQ_RNGB (KINETIS_IRQ_FIRST + 23) /* 23: Random number generator */
#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST + 24) /* 24: I2C0 */
#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST + 25) /* 25: I2C1 */
#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST + 26) /* 26: SPI0 all sources */
#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST + 27) /* 27: SPI1 all sources */
#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST + 28) /* 28: SPI2 all sources */
#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST + 29) /* 29: CAN0 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST + 30) /* 30: CAN0 Bus Off */
#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST + 31) /* 31: CAN0 Error */
#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST + 32) /* 32: CAN0 Transmit Warning */
#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST + 33) /* 33: CAN0 Receive Warning */
#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST + 34) /* 34: CAN0 Wake UP */
#define KINETIS_IRQ_RESVD35 (KINETIS_IRQ_FIRST + 35) /* 35: Reserved */
#define KINETIS_IRQ_RESVD36 (KINETIS_IRQ_FIRST + 36) /* 36: Reserved */
#define KINETIS_IRQ_CAN1MB (KINETIS_IRQ_FIRST + 37) /* 37: CAN1 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN1BO (KINETIS_IRQ_FIRST + 38) /* 38: CAN1 Bus Off */
#define KINETIS_IRQ_CAN1ERR (KINETIS_IRQ_FIRST + 39) /* 39: CAN1 Error */
#define KINETIS_IRQ_CAN1TW (KINETIS_IRQ_FIRST + 40) /* 40: CAN1 Transmit Warning */
#define KINETIS_IRQ_CAN1RW (KINETIS_IRQ_FIRST + 41) /* 41: CAN1 Receive Warning */
#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST + 42) /* 42: CAN1 Wake UP */
#define KINETIS_IRQ_RESVD43 (KINETIS_IRQ_FIRST + 43) /* 43: Reserved */
#define KINETIS_IRQ_RESVD44 (KINETIS_IRQ_FIRST + 44) /* 44: Reserved */
#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST + 45) /* 45: UART0 status */
#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST + 46) /* 46: UART0 error */
#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST + 47) /* 47: UART1 status */
#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST + 48) /* 48: UART1 error */
#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST + 49) /* 49: UART2 status */
#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST + 50) /* 50: UART2 error */
#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST + 51) /* 51: UART3 status */
#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST + 52) /* 52: UART3 error */
#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST + 53) /* 53: UART4 status */
#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST + 54) /* 54: UART4 error */
#define KINETIS_IRQ_UART5S (KINETIS_IRQ_FIRST + 55) /* 55: UART5 status */
#define KINETIS_IRQ_UART5E (KINETIS_IRQ_FIRST + 56) /* 56: UART5 error */
#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST + 57) /* 57: ADC0 */
#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST + 58) /* 58: ADC1 */
#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST + 59) /* 59: CMP0 */
#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST + 60) /* 60: CMP1 */
#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST + 61) /* 61: CMP2 */
#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST + 62) /* 62: FTM0 all sources */
#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST + 63) /* 63: FTM1 all sources */
#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST + 64) /* 64: FTM2 all sources */
#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST + 65) /* 65: CMT */
#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST + 66) /* 66: RTC alarm interrupt */
#define KINETIS_IRQ_RESVD67 (KINETIS_IRQ_FIRST + 67) /* 67: Reserved */
#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST + 68) /* 68: PIT channel 0 */
#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST + 69) /* 69: PIT channel 1 */
#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST + 70) /* 70: PIT channel 2 */
#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST + 71) /* 71: PIT channel 3 */
#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST + 72) /* 72: PDB */
#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST + 73) /* 73: USB OTG */
#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST + 74) /* 74: USB charger detect */
#define KINETIS_IRQ_EMACTMR (KINETIS_IRQ_FIRST + 75) /* 75: Ethernet MAC IEEE 1588 timer interrupt */
#define KINETIS_IRQ_EMACTX (KINETIS_IRQ_FIRST + 76) /* 76: Ethernet MAC transmit interrupt */
#define KINETIS_IRQ_EMACRX (KINETIS_IRQ_FIRST + 77) /* 77: Ethernet MAC receive interrupt */
#define KINETIS_IRQ_EMACMISC (KINETIS_IRQ_FIRST + 78) /* 78: Ethernet MAC error and misc interrupt */
#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST + 79) /* 79: I2S0 */
#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST + 80) /* 80: SDHC */
#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST + 81) /* 81: DAC0 */
#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST + 82) /* 82: DAC1 */
#define KINETIS_IRQ_TSI (KINETIS_IRQ_FIRST + 83) /* 83: TSI all sources */
#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST + 84) /* 84: MCG */
#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST + 85) /* 85: Low power timer */
#define KINETIS_IRQ_RESVD86 (KINETIS_IRQ_FIRST + 86) /* 86: Reserved */
#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST + 87) /* 87: Pin detect port A */
#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST + 88) /* 88: Pin detect port B */
#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST + 89) /* 89: Pin detect port C */
#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST + 90) /* 90: Pin detect port D */
#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST + 91) /* 91: Pin detect port E */
#define KINETIS_IRQ_RESVD92 (KINETIS_IRQ_FIRST + 92) /* 92: Reserved */
#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST + 93) /* 93: Reserved */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST + 94) /* 94: Software interrupt */
#define NR_INTERRUPTS 95 /* 95 Non core IRQs*/
#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 111 vectors */
#define KINETIS_IRQ_NEXTINTS 95 /* 95 Non core IRQs */
#define KINETIS_IRQ_NVECTORS (KINETIS_IRQ_FIRST + KINETIS_IRQ_NEXTINTS) /* 111 vectors */
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS KINETIS_IRQ_NVECTORS
/*****************************************************************************
/************************************************************************************
* Public Types
****************************************************************************/
************************************************************************************/
/*****************************************************************************
/************************************************************************************
* Public Data
****************************************************************************/
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@ -187,9 +187,9 @@ extern "C"
#define EXTERN extern
#endif
/*****************************************************************************
/************************************************************************************
* Public Functions
****************************************************************************/
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus

206
arch/arm/include/kinetis/kinetis_k64irq.h
View File

@ -1,4 +1,4 @@
/*****************************************************************************
/************************************************************************************
* arch/arm/include/kinetis/kinetis_k64irq.h
*
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
@ -32,7 +32,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
************************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
@ -41,15 +41,15 @@
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_64KIRQ_H
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_64KIRQ_H
/*****************************************************************************
/************************************************************************************
* Included Files
****************************************************************************/
************************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
/************************************************************************************
* Pre-processor Definitions
****************************************************************************/
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
@ -60,113 +60,113 @@
*
* External interrupts (vectors >= 16)
*
* K60 Family ****************************************************************
* K60 Family ************************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale
* document K64P144M120SF5RM.pdf
*/
#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0 transfer complete */
#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1 transfer complete */
#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2 transfer complete */
#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3 transfer complete */
#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4 transfer complete */
#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5 transfer complete */
#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6 transfer complete */
#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7 transfer complete */
#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8 transfer complete */
#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9 transfer complete */
#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10 transfer complete */
#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11 transfer complete */
#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12 transfer complete */
#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13 transfer complete */
#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14 transfer complete */
#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15 transfer complete */
#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-15 */
#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST+17) /* 17: MCM Normal interrupt */
#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */
#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */
#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage
* detect, low-voltage warning */
#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */
#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog or EWM */
#define KINETIS_IRQ_RNGB (KINETIS_IRQ_FIRST+23) /* 23: Random number generator */
#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */
#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */
#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */
#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */
#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST+28) /* 28: 12S0 Transmit */
#define KINETIS_IRQ_I2S1 (KINETIS_IRQ_FIRST+29) /* 29: 12S0 Receive */
#define KINETIS_IRQ_RESVD30 (KINETIS_IRQ_FIRST+30) /* 30: Reserved */
#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+31) /* 31: UART0 status */
#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+32) /* 32: UART0 error */
#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+33) /* 33: UART1 status */
#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+34) /* 34: UART1 error */
#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+35) /* 35: UART2 status */
#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+36) /* 36: UART2 error */
#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST+37) /* 37: UART3 status */
#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST+38) /* 38: UART3 error */
#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+39) /* 39: ADC0 */
#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+40) /* 40: CMP0 */
#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+41) /* 41: CMP1 */
#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+42) /* 42: FTM0 all sources */
#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+43) /* 43: FTM1 all sources */
#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+44) /* 44: FTM2 all sources */
#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+45) /* 45: CMT */
#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+46) /* 46: RTC alarm interrupt */
#define KINETIS_IRQ_RTCS (KINETIS_IRQ_FIRST+47) /* 47: RTC seconds interrupt */
#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+48) /* 48: PIT channel 0 */
#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+49) /* 49: PIT channel 1 */
#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+50) /* 50: PIT channel 2 */
#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+51) /* 51: PIT channel 3 */
#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+52) /* 52: PDB */
#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+53) /* 53: USB OTG */
#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+54) /* 54: USB charger detect */
#define KINETIS_IRQ_RESVD55 (KINETIS_IRQ_FIRST+55) /* 55: Reserved */
#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+56) /* 56: DAC0 */
#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+57) /* 57: MCG */
#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+58) /* 58: Low power timer */
#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+59) /* 59: Pin detect port A */
#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+60) /* 60: Pin detect port B */
#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+61) /* 61: Pin detect port C */
#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+62) /* 62: Pin detect port D */
#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+63) /* 63: Pin detect port E */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+64) /* 64: Software interrupt */
#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST+65) /* 65: SPI2 all sources */
#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST+66) /* 66: UART4 status */
#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST+67) /* 67: UART4 error */
#define KINETIS_IRQ_UART5S (KINETIS_IRQ_FIRST+68) /* 68: UART5 status */
#define KINETIS_IRQ_UART5E (KINETIS_IRQ_FIRST+69) /* 69: UART5 error */
#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+70) /* 70: CMP2 */
#define KINETIS_IRQ_FTM3 (KINETIS_IRQ_FIRST+71) /* 71: FTM3 all sources */
#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST+72) /* 72: DAC1 */
#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+73) /* 73: ADC1 */
#define KINETIS_IRQ_I2C2 (KINETIS_IRQ_FIRST+74) /* 74: I2C2 */
#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+75) /* 75: CAN0 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+76) /* 76: CAN0 Bus Off */
#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+77) /* 77: CAN0 Error */
#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+78) /* 78: CAN0 Transmit Warning */
#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+79) /* 79: CAN0 Receive Warning */
#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+80) /* 80: CAN0 Wake UP */
#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST+81) /* 81: SDHC */
#define KINETIS_IRQ_EMACTMR (KINETIS_IRQ_FIRST+82) /* 82: Ethernet MAC IEEE 1588 timer interrupt */
#define KINETIS_IRQ_EMACTX (KINETIS_IRQ_FIRST+83) /* 83: Ethernet MAC transmit interrupt */
#define KINETIS_IRQ_EMACRX (KINETIS_IRQ_FIRST+84) /* 84: Ethernet MAC receive interrupt */
#define KINETIS_IRQ_EMACMISC (KINETIS_IRQ_FIRST+85) /* 85: Ethernet MAC error and misc interrupt */
#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST + 0) /* 0: DMA channel 0 transfer complete */
#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST + 1) /* 1: DMA channel 1 transfer complete */
#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST + 2) /* 2: DMA channel 2 transfer complete */
#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST + 3) /* 3: DMA channel 3 transfer complete */
#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST + 4) /* 4: DMA channel 4 transfer complete */
#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST + 5) /* 5: DMA channel 5 transfer complete */
#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST + 6) /* 6: DMA channel 6 transfer complete */
#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST + 7) /* 7: DMA channel 7 transfer complete */
#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST + 8) /* 8: DMA channel 8 transfer complete */
#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST + 9) /* 9: DMA channel 9 transfer complete */
#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST + 10) /* 10: DMA channel 10 transfer complete */
#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST + 11) /* 11: DMA channel 11 transfer complete */
#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST + 12) /* 12: DMA channel 12 transfer complete */
#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST + 13) /* 13: DMA channel 13 transfer complete */
#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST + 14) /* 14: DMA channel 14 transfer complete */
#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST + 15) /* 15: DMA channel 15 transfer complete */
#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST + 16) /* 16: DMA error interrupt channels 0-15 */
#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST + 17) /* 17: MCM Normal interrupt */
#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST + 18) /* 18: Flash memory command complete */
#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST + 19) /* 19: Flash memory read collision */
#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST + 20) /* 20: Mode Controller low-voltage
* detect, low-voltage warning */
#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST + 21) /* 21: LLWU Normal Low Leakage Wakeup */
#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST + 22) /* 22: Watchdog or EWM */
#define KINETIS_IRQ_RNGB (KINETIS_IRQ_FIRST + 23) /* 23: Random number generator */
#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST + 24) /* 24: I2C0 */
#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST + 25) /* 25: I2C1 */
#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST + 26) /* 26: SPI0 all sources */
#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST + 27) /* 27: SPI1 all sources */
#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST + 28) /* 28: 12S0 Transmit */
#define KINETIS_IRQ_I2S1 (KINETIS_IRQ_FIRST + 29) /* 29: 12S0 Receive */
#define KINETIS_IRQ_RESVD30 (KINETIS_IRQ_FIRST + 30) /* 30: Reserved */
#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST + 31) /* 31: UART0 status */
#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST + 32) /* 32: UART0 error */
#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST + 33) /* 33: UART1 status */
#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST + 34) /* 34: UART1 error */
#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST + 35) /* 35: UART2 status */
#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST + 36) /* 36: UART2 error */
#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST + 37) /* 37: UART3 status */
#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST + 38) /* 38: UART3 error */
#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST + 39) /* 39: ADC0 */
#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST + 40) /* 40: CMP0 */
#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST + 41) /* 41: CMP1 */
#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST + 42) /* 42: FTM0 all sources */
#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST + 43) /* 43: FTM1 all sources */
#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST + 44) /* 44: FTM2 all sources */
#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST + 45) /* 45: CMT */
#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST + 46) /* 46: RTC alarm interrupt */
#define KINETIS_IRQ_RTCS (KINETIS_IRQ_FIRST + 47) /* 47: RTC seconds interrupt */
#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST + 48) /* 48: PIT channel 0 */
#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST + 49) /* 49: PIT channel 1 */
#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST + 50) /* 50: PIT channel 2 */
#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST + 51) /* 51: PIT channel 3 */
#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST + 52) /* 52: PDB */
#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST + 53) /* 53: USB OTG */
#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST + 54) /* 54: USB charger detect */
#define KINETIS_IRQ_RESVD55 (KINETIS_IRQ_FIRST + 55) /* 55: Reserved */
#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST + 56) /* 56: DAC0 */
#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST + 57) /* 57: MCG */
#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST + 58) /* 58: Low power timer */
#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST + 59) /* 59: Pin detect port A */
#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST + 60) /* 60: Pin detect port B */
#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST + 61) /* 61: Pin detect port C */
#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST + 62) /* 62: Pin detect port D */
#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST + 63) /* 63: Pin detect port E */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST + 64) /* 64: Software interrupt */
#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST + 65) /* 65: SPI2 all sources */
#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST + 66) /* 66: UART4 status */
#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST + 67) /* 67: UART4 error */
#define KINETIS_IRQ_UART5S (KINETIS_IRQ_FIRST + 68) /* 68: UART5 status */
#define KINETIS_IRQ_UART5E (KINETIS_IRQ_FIRST + 69) /* 69: UART5 error */
#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST + 70) /* 70: CMP2 */
#define KINETIS_IRQ_FTM3 (KINETIS_IRQ_FIRST + 71) /* 71: FTM3 all sources */
#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST + 72) /* 72: DAC1 */
#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST + 73) /* 73: ADC1 */
#define KINETIS_IRQ_I2C2 (KINETIS_IRQ_FIRST + 74) /* 74: I2C2 */
#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST + 75) /* 75: CAN0 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST + 76) /* 76: CAN0 Bus Off */
#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST + 77) /* 77: CAN0 Error */
#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST + 78) /* 78: CAN0 Transmit Warning */
#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST + 79) /* 79: CAN0 Receive Warning */
#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST + 80) /* 80: CAN0 Wake UP */
#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST + 81) /* 81: SDHC */
#define KINETIS_IRQ_EMACTMR (KINETIS_IRQ_FIRST + 82) /* 82: Ethernet MAC IEEE 1588 timer interrupt */
#define KINETIS_IRQ_EMACTX (KINETIS_IRQ_FIRST + 83) /* 83: Ethernet MAC transmit interrupt */
#define KINETIS_IRQ_EMACRX (KINETIS_IRQ_FIRST + 84) /* 84: Ethernet MAC receive interrupt */
#define KINETIS_IRQ_EMACMISC (KINETIS_IRQ_FIRST + 85) /* 85: Ethernet MAC error and misc interrupt */
#define NR_INTERRUPTS 86 /* 86 Non core IRQs*/
#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 102 vectors */
#define KINETIS_IRQ_NEXTINTS 86 /* 86 Non core IRQs */
#define KINETIS_IRQ_NVECTORS (KINETIS_IRQ_FIRST + KINETIS_IRQ_NEXTINTS) /* 102 vectors */
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS KINETIS_IRQ_NVECTORS
/*****************************************************************************
/************************************************************************************
* Public Types
****************************************************************************/
************************************************************************************/
/*****************************************************************************
/************************************************************************************
* Public Data
****************************************************************************/
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@ -177,9 +177,9 @@ extern "C"
#define EXTERN extern
#endif
/*****************************************************************************
/************************************************************************************
* Public Functions
****************************************************************************/
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus

234
arch/arm/include/kinetis/kinetis_k66irq.h
View File

@ -1,4 +1,4 @@
/*****************************************************************************
/************************************************************************************
* arch/arm/include/kinetis/kinetis_k66irq.h
*
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
@ -32,7 +32,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
************************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
@ -41,15 +41,15 @@
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_K66IRQ_H
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_K66IRQ_H
/*****************************************************************************
/************************************************************************************
* Included Files
****************************************************************************/
************************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
/************************************************************************************
* Pre-processor Definitions
****************************************************************************/
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
@ -60,129 +60,129 @@
*
* External interrupts (vectors >= 16)
*
* K66 Family ****************************************************************
* K66 Family ************************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale
* document K66P144M180SF5RMV2
*/
#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0, 16 transfer complete */
#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1, 17 transfer complete */
#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2, 18 transfer complete */
#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3, 19 transfer complete */
#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4, 20 transfer complete */
#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5, 21 transfer complete */
#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6, 11 transfer complete */
#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7, 23 transfer complete */
#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8, 24 transfer complete */
#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9, 25 transfer complete */
#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10, 26 transfer complete */
#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11, 27 transfer complete */
#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12, 28 transfer complete */
#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13, 29 transfer complete */
#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14, 30 transfer complete */
#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15, 31 transfer complete */
#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-31 */
#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST+17) /* 17: MCM Normal interrupt */
#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */
#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */
#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage
* detect, low-voltage warning */
#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */
#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog or EWM */
#define KINETIS_IRQ_RNGB (KINETIS_IRQ_FIRST+23) /* 23: Random number generator */
#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */
#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */
#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */
#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */
#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST+28) /* 28: 12S0 Transmit */
#define KINETIS_IRQ_I2S1 (KINETIS_IRQ_FIRST+29) /* 29: 12S0 Receive */
#define KINETIS_IRQ_RESVD30 (KINETIS_IRQ_FIRST+30) /* 30: Reserved */
#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+31) /* 31: UART0 status */
#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+32) /* 32: UART0 error */
#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+33) /* 33: UART1 status */
#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+34) /* 34: UART1 error */
#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+35) /* 35: UART2 status */
#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+36) /* 36: UART2 error */
#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST+37) /* 37: UART3 status */
#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST+38) /* 38: UART3 error */
#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+39) /* 39: ADC0 */
#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+40) /* 40: CMP0 */
#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+41) /* 41: CMP1 */
#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+42) /* 42: FTM0 all sources */
#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+43) /* 43: FTM1 all sources */
#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+44) /* 44: FTM2 all sources */
#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+45) /* 45: CMT */
#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+46) /* 46: RTC alarm interrupt */
#define KINETIS_IRQ_RTCS (KINETIS_IRQ_FIRST+47) /* 47: RTC seconds interrupt */
#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+48) /* 48: PIT channel 0 */
#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+49) /* 49: PIT channel 1 */
#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+50) /* 50: PIT channel 2 */
#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+51) /* 51: PIT channel 3 */
#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+52) /* 52: PDB */
#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+53) /* 53: USB OTG */
#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+54) /* 54: USB charger detect */
#define KINETIS_IRQ_RESVD55 (KINETIS_IRQ_FIRST+55) /* 55: Reserved */
#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+56) /* 56: DAC0 */
#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+57) /* 57: MCG */
#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+58) /* 58: Low power timer */
#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+59) /* 59: Pin detect port A */
#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+60) /* 60: Pin detect port B */
#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+61) /* 61: Pin detect port C */
#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+62) /* 62: Pin detect port D */
#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+63) /* 63: Pin detect port E */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+64) /* 64: Software interrupt */
#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST+65) /* 65: SPI2 all sources */
#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST+66) /* 66: UART4 status */
#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST+67) /* 67: UART4 error */
#define KINETIS_IRQ_RESVD68 (KINETIS_IRQ_FIRST+68) /* 68: Reserved */
#define KINETIS_IRQ_RESVD69 (KINETIS_IRQ_FIRST+69) /* 69: Reserved */
#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+70) /* 70: CMP2 */
#define KINETIS_IRQ_FTM3 (KINETIS_IRQ_FIRST+71) /* 71: FTM3 all sources */
#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST+72) /* 72: DAC1 */
#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+73) /* 73: ADC1 */
#define KINETIS_IRQ_I2C2 (KINETIS_IRQ_FIRST+74) /* 74: I2C2 */
#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+75) /* 75: CAN0 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+76) /* 76: CAN0 Bus Off */
#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+77) /* 77: CAN0 Error */
#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+78) /* 78: CAN0 Transmit Warning */
#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+79) /* 79: CAN0 Receive Warning */
#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+80) /* 80: CAN0 Wake UP */
#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST+81) /* 81: SDHC */
#define KINETIS_IRQ_EMACTMR (KINETIS_IRQ_FIRST+82) /* 82: Ethernet MAC IEEE 1588 timer interrupt */
#define KINETIS_IRQ_EMACTX (KINETIS_IRQ_FIRST+83) /* 83: Ethernet MAC transmit interrupt */
#define KINETIS_IRQ_EMACRX (KINETIS_IRQ_FIRST+84) /* 84: Ethernet MAC receive interrupt */
#define KINETIS_IRQ_EMACMISC (KINETIS_IRQ_FIRST+85) /* 85: Ethernet MAC error and misc interrupt */
#define KINETIS_IRQ_LPUART0 (KINETIS_IRQ_FIRST+86) /* 86: LPUART0 Status and error */
#define KINETIS_IRQ_TSI0 (KINETIS_IRQ_FIRST+87) /* 87: TSI0 */
#define KINETIS_IRQ_TPM1 (KINETIS_IRQ_FIRST+88) /* 88: TPM1 */
#define KINETIS_IRQ_TPM2 (KINETIS_IRQ_FIRST+89) /* 89: TPM2 */
#define KINETIS_IRQ_USBHSDCD (KINETIS_IRQ_FIRST+90) /* 90: shared by USBHS DCD & USBHS Phy modules */
#define KINETIS_IRQ_I2C3 (KINETIS_IRQ_FIRST+91) /* 91: I2C3 */
#define KINETIS_IRQ_CMP3 (KINETIS_IRQ_FIRST+92) /* 92: CMP3 */
#define KINETIS_IRQ_USBHSOTG (KINETIS_IRQ_FIRST+93) /* 93: USBHS OTG*/
#define KINETIS_IRQ_CAN1MB (KINETIS_IRQ_FIRST+94) /* 94: CAN1 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN1BO (KINETIS_IRQ_FIRST+95) /* 95: CAN1 Bus Off */
#define KINETIS_IRQ_CAN1ERR (KINETIS_IRQ_FIRST+96) /* 96: CAN1 Error */
#define KINETIS_IRQ_CAN1TW (KINETIS_IRQ_FIRST+97) /* 97: CAN1 Transmit Warning */
#define KINETIS_IRQ_CAN1RW (KINETIS_IRQ_FIRST+98) /* 98: CAN1 Receive Warning */
#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST+99) /* 99: CAN1 Wake UP */
#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST + 0) /* 0: DMA channel 0, 16 transfer complete */
#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST + 1) /* 1: DMA channel 1, 17 transfer complete */
#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST + 2) /* 2: DMA channel 2, 18 transfer complete */
#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST + 3) /* 3: DMA channel 3, 19 transfer complete */
#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST + 4) /* 4: DMA channel 4, 20 transfer complete */
#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST + 5) /* 5: DMA channel 5, 21 transfer complete */
#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST + 6) /* 6: DMA channel 6, 11 transfer complete */
#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST + 7) /* 7: DMA channel 7, 23 transfer complete */
#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST + 8) /* 8: DMA channel 8, 24 transfer complete */
#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST + 9) /* 9: DMA channel 9, 25 transfer complete */
#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST + 10) /* 10: DMA channel 10, 26 transfer complete */
#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST + 11) /* 11: DMA channel 11, 27 transfer complete */
#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST + 12) /* 12: DMA channel 12, 28 transfer complete */
#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST + 13) /* 13: DMA channel 13, 29 transfer complete */
#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST + 14) /* 14: DMA channel 14, 30 transfer complete */
#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST + 15) /* 15: DMA channel 15, 31 transfer complete */
#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST + 16) /* 16: DMA error interrupt channels 0-31 */
#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST + 17) /* 17: MCM Normal interrupt */
#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST + 18) /* 18: Flash memory command complete */
#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST + 19) /* 19: Flash memory read collision */
#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST + 20) /* 20: Mode Controller low-voltage
* detect, low-voltage warning */
#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST + 21) /* 21: LLWU Normal Low Leakage Wakeup */
#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST + 22) /* 22: Watchdog or EWM */
#define KINETIS_IRQ_RNGB (KINETIS_IRQ_FIRST + 23) /* 23: Random number generator */
#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST + 24) /* 24: I2C0 */
#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST + 25) /* 25: I2C1 */
#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST + 26) /* 26: SPI0 all sources */
#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST + 27) /* 27: SPI1 all sources */
#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST + 28) /* 28: 12S0 Transmit */
#define KINETIS_IRQ_I2S1 (KINETIS_IRQ_FIRST + 29) /* 29: 12S0 Receive */
#define KINETIS_IRQ_RESVD30 (KINETIS_IRQ_FIRST + 30) /* 30: Reserved */
#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST + 31) /* 31: UART0 status */
#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST + 32) /* 32: UART0 error */
#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST + 33) /* 33: UART1 status */
#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST + 34) /* 34: UART1 error */
#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST + 35) /* 35: UART2 status */
#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST + 36) /* 36: UART2 error */
#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST + 37) /* 37: UART3 status */
#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST + 38) /* 38: UART3 error */
#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST + 39) /* 39: ADC0 */
#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST + 40) /* 40: CMP0 */
#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST + 41) /* 41: CMP1 */
#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST + 42) /* 42: FTM0 all sources */
#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST + 43) /* 43: FTM1 all sources */
#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST + 44) /* 44: FTM2 all sources */
#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST + 45) /* 45: CMT */
#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST + 46) /* 46: RTC alarm interrupt */
#define KINETIS_IRQ_RTCS (KINETIS_IRQ_FIRST + 47) /* 47: RTC seconds interrupt */
#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST + 48) /* 48: PIT channel 0 */
#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST + 49) /* 49: PIT channel 1 */
#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST + 50) /* 50: PIT channel 2 */
#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST + 51) /* 51: PIT channel 3 */
#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST + 52) /* 52: PDB */
#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST + 53) /* 53: USB OTG */
#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST + 54) /* 54: USB charger detect */
#define KINETIS_IRQ_RESVD55 (KINETIS_IRQ_FIRST + 55) /* 55: Reserved */
#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST + 56) /* 56: DAC0 */
#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST + 57) /* 57: MCG */
#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST + 58) /* 58: Low power timer */
#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST + 59) /* 59: Pin detect port A */
#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST + 60) /* 60: Pin detect port B */
#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST + 61) /* 61: Pin detect port C */
#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST + 62) /* 62: Pin detect port D */
#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST + 63) /* 63: Pin detect port E */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST + 64) /* 64: Software interrupt */
#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST + 65) /* 65: SPI2 all sources */
#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST + 66) /* 66: UART4 status */
#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST + 67) /* 67: UART4 error */
#define KINETIS_IRQ_RESVD68 (KINETIS_IRQ_FIRST + 68) /* 68: Reserved */
#define KINETIS_IRQ_RESVD69 (KINETIS_IRQ_FIRST + 69) /* 69: Reserved */
#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST + 70) /* 70: CMP2 */
#define KINETIS_IRQ_FTM3 (KINETIS_IRQ_FIRST + 71) /* 71: FTM3 all sources */
#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST + 72) /* 72: DAC1 */
#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST + 73) /* 73: ADC1 */
#define KINETIS_IRQ_I2C2 (KINETIS_IRQ_FIRST + 74) /* 74: I2C2 */
#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST + 75) /* 75: CAN0 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST + 76) /* 76: CAN0 Bus Off */
#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST + 77) /* 77: CAN0 Error */
#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST + 78) /* 78: CAN0 Transmit Warning */
#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST + 79) /* 79: CAN0 Receive Warning */
#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST + 80) /* 80: CAN0 Wake UP */
#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST + 81) /* 81: SDHC */
#define KINETIS_IRQ_EMACTMR (KINETIS_IRQ_FIRST + 82) /* 82: Ethernet MAC IEEE 1588 timer interrupt */
#define KINETIS_IRQ_EMACTX (KINETIS_IRQ_FIRST + 83) /* 83: Ethernet MAC transmit interrupt */
#define KINETIS_IRQ_EMACRX (KINETIS_IRQ_FIRST + 84) /* 84: Ethernet MAC receive interrupt */
#define KINETIS_IRQ_EMACMISC (KINETIS_IRQ_FIRST + 85) /* 85: Ethernet MAC error and misc interrupt */
#define KINETIS_IRQ_LPUART0 (KINETIS_IRQ_FIRST + 86) /* 86: LPUART0 Status and error */
#define KINETIS_IRQ_TSI0 (KINETIS_IRQ_FIRST + 87) /* 87: TSI0 */
#define KINETIS_IRQ_TPM1 (KINETIS_IRQ_FIRST + 88) /* 88: TPM1 */
#define KINETIS_IRQ_TPM2 (KINETIS_IRQ_FIRST + 89) /* 89: TPM2 */
#define KINETIS_IRQ_USBHSDCD (KINETIS_IRQ_FIRST + 90) /* 90: shared by USBHS DCD & USBHS Phy modules */
#define KINETIS_IRQ_I2C3 (KINETIS_IRQ_FIRST + 91) /* 91: I2C3 */
#define KINETIS_IRQ_CMP3 (KINETIS_IRQ_FIRST + 92) /* 92: CMP3 */
#define KINETIS_IRQ_USBHSOTG (KINETIS_IRQ_FIRST + 93) /* 93: USBHS OTG*/
#define KINETIS_IRQ_CAN1MB (KINETIS_IRQ_FIRST + 94) /* 94: CAN1 OR'ed Message buffer (0-15) */
#define KINETIS_IRQ_CAN1BO (KINETIS_IRQ_FIRST + 95) /* 95: CAN1 Bus Off */
#define KINETIS_IRQ_CAN1ERR (KINETIS_IRQ_FIRST + 96) /* 96: CAN1 Error */
#define KINETIS_IRQ_CAN1TW (KINETIS_IRQ_FIRST + 97) /* 97: CAN1 Transmit Warning */
#define KINETIS_IRQ_CAN1RW (KINETIS_IRQ_FIRST + 98) /* 98: CAN1 Receive Warning */
#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST + 99) /* 99: CAN1 Wake UP */
#define NR_INTERRUPTS 100 /* 100 Non core IRQs*/
#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 116 vectors */
#define KINETIS_IRQ_NEXTINTS 100 /* 100 Non core IRQs*/
#define KINETIS_IRQ_NVECTORS (KINETIS_IRQ_FIRST + KINETIS_IRQ_NEXTINTS) /* 116 vectors */
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS KINETIS_IRQ_NVECTORS
/*****************************************************************************
/************************************************************************************
* Public Types
****************************************************************************/
************************************************************************************/
/*****************************************************************************
/************************************************************************************
* Public Data
****************************************************************************/
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@ -193,9 +193,9 @@ extern "C"
#define EXTERN extern
#endif
/*****************************************************************************
/************************************************************************************
* Public Functions
****************************************************************************/
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus

2
arch/arm/include/kl/irq.h
View File

@ -122,7 +122,6 @@
* now) seems to justify the waste.
*/
# define NR_VECTORS (64) /* 64 vectors */
# define NR_IRQS (48) /* 64 interrupts but 48 IRQ numbers */
#elif defined(CONFIG_ARCH_CHIP_MKL26Z128)
@ -168,7 +167,6 @@
* now) seems to justify the waste.
*/
# define NR_VECTORS (64) /* 64 vectors */
# define NR_IRQS (48) /* 64 interrupts but 48 IRQ numbers */
#else

1
arch/arm/include/lc823450/irq.h
View File

@ -258,7 +258,6 @@
#define LC823450_IRQ_NVIRTUALIRQS (0)
#endif /* CONFIG_LC823450_VIRQ */
#define NR_VECTORS (LC823450_IRQ_NIRQS)
#define NR_IRQS (LC823450_IRQ_NIRQS + LC823450_IRQ_NGPIOIRQS + \
LC823450_IRQ_NVIRTUALIRQS)

1
arch/arm/include/lpc11xx/irq.h
View File

@ -109,7 +109,6 @@
#define LPC11_IRQ_PIO0 (47) /* Vector 47: PIO0 */
#endif
#define NR_VECTORS (48) /* 48 vectors */
#define NR_IRQS (48) /* 32 interrupts plus 16 exceptions */
/****************************************************************************

1
arch/arm/include/lpc17xx/lpc176x_irq.h
View File

@ -223,7 +223,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS LPC17_IRQ_NIRQS
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
/****************************************************************************

1
arch/arm/include/lpc17xx/lpc178x_irq.h
View File

@ -269,7 +269,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS LPC17_IRQ_NIRQS
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
/****************************************************************************

2
arch/arm/include/lpc43xx/irq.h
View File

@ -133,7 +133,6 @@
* supported)
*/
#define NR_VECTORS LPC43M4_IRQ_NIRQS
#define NR_IRQS LPC43M4_IRQ_NIRQS
/* Cortex-M0 External interrupts (vectors >= 16) */
@ -184,7 +183,6 @@
*/
#if 0
#define NR_VECTORS LPC43M0_IRQ_NIRQS
#define NR_IRQS LPC43M0_IRQ_NIRQS
#endif

1
arch/arm/include/lpc54xx/lpc546x_irq.h
View File

@ -109,7 +109,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS LPC54_IRQ_NIRQS
#define NR_IRQS LPC54_IRQ_NIRQS
#endif /* __ARCH_ARM_INCLUDE_LPC54XX_LPC543X_IRQ_H */

1
arch/arm/include/nrf52/nrf52832_irq.h
View File

@ -91,7 +91,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS NRF52_IRQ_NIRQS
#define NR_IRQS NRF52_IRQ_NIRQS
#endif /* __ARCH_ARM_INCLUDE_NRF52_NRF52_IRQ_H */

1
arch/arm/include/sam34/sam3u_irq.h
View File

@ -238,7 +238,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)

1
arch/arm/include/sam34/sam3x_irq.h
View File

@ -392,7 +392,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \
SAM_NGPIODIRQS + SAM_NGPIOEIRQS + SAM_NGPIOFIRQS)

1
arch/arm/include/sam34/sam4cm_irq.h
View File

@ -267,7 +267,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)

1
arch/arm/include/sam34/sam4e_irq.h
View File

@ -300,7 +300,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \
SAM_NGPIODIRQS + SAM_NGPIOEIRQS)

1
arch/arm/include/sam34/sam4l_irq.h
View File

@ -299,7 +299,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)

1
arch/arm/include/sam34/sam4s_irq.h
View File

@ -249,7 +249,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)

1
arch/arm/include/samdl/samd20_irq.h
View File

@ -105,7 +105,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_INTERRUPT + SAM_IRQ_NINTS + SAM_IRQ_NEXTINTS)
/****************************************************************************************

1
arch/arm/include/samdl/samd21_irq.h
View File

@ -112,7 +112,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_INTERRUPT + SAM_IRQ_NINTS + SAM_IRQ_NEXTINTS)
/****************************************************************************************

103
arch/arm/include/samdl/saml21_irq.h
View File

@ -50,62 +50,62 @@
/* External interrupts */
#define SAM_IRQ_PM (SAM_IRQ_INTERRUPT+0) /* Power Manager */
#define SAM_IRQ_MCLK (SAM_IRQ_INTERRUPT+0) /* Main Clock */
#define SAM_IRQ_OSCCTRL (SAM_IRQ_INTERRUPT+0) /* Oscillators Controller */
#define SAM_IRQ_OSC32KCTRL (SAM_IRQ_INTERRUPT+0) /* 32KHz scillators Controller */
#define SAM_IRQ_SUPC (SAM_IRQ_INTERRUPT+0) /* Supply Controller */
#define SAM_IRQ_PACC (SAM_IRQ_INTERRUPT+0) /* Protection Access Controller */
#define SAM_IRQ_WDT (SAM_IRQ_INTERRUPT+1) /* Watchdog Timer */
#define SAM_IRQ_RTC (SAM_IRQ_INTERRUPT+2) /* Real Time Counter */
#define SAM_IRQ_EIC (SAM_IRQ_INTERRUPT+3) /* External Interrupt Controller */
#define SAM_IRQ_NVMCTRL (SAM_IRQ_INTERRUPT+4) /* Non-Volatile Memory Controller */
#define SAM_IRQ_DMAC (SAM_IRQ_INTERRUPT+5) /* Direct Memory Access Controller */
#define SAM_IRQ_USB (SAM_IRQ_INTERRUPT+6) /* Universal Serial Bus */
#define SAM_IRQ_EVSYS (SAM_IRQ_INTERRUPT+7) /* Event System */
#define SAM_IRQ_SERCOM0 (SAM_IRQ_INTERRUPT+8) /* Serial Communication Interface 0 */
#define SAM_IRQ_SERCOM1 (SAM_IRQ_INTERRUPT+9) /* Serial Communication Interface 1 */
#define SAM_IRQ_SERCOM2 (SAM_IRQ_INTERRUPT+10) /* Serial Communication Interface 2 */
#define SAM_IRQ_SERCOM3 (SAM_IRQ_INTERRUPT+11) /* Serial Communication Interface 3 */
#define SAM_IRQ_SERCOM4 (SAM_IRQ_INTERRUPT+12) /* Serial Communication Interface 4 */
#define SAM_IRQ_SERCOM5 (SAM_IRQ_INTERRUPT+13) /* Serial Communication Interface 5 */
#define SAM_IRQ_TCC0 (SAM_IRQ_INTERRUPT+14) /* Timer/Counter for Control 0 */
#define SAM_IRQ_TCC1 (SAM_IRQ_INTERRUPT+15) /* Timer/Counter for Control 1 */
#define SAM_IRQ_TCC2 (SAM_IRQ_INTERRUPT+16) /* Timer/Counter for Control 2 */
#define SAM_IRQ_TC0 (SAM_IRQ_INTERRUPT+17) /* Timer/Counter 0 */
#define SAM_IRQ_TC1 (SAM_IRQ_INTERRUPT+18) /* Timer/Counter 1 */
#define SAM_IRQ_TC2 (SAM_IRQ_INTERRUPT+19) /* Timer/Counter 2 */
#define SAM_IRQ_TC3 (SAM_IRQ_INTERRUPT+20) /* Timer/Counter 3 */
#define SAM_IRQ_TC4 (SAM_IRQ_INTERRUPT+21) /* Timer/Counter 4 */
#define SAM_IRQ_ADC (SAM_IRQ_INTERRUPT+22) /* Analog-to-Digital Converter */
#define SAM_IRQ_AC (SAM_IRQ_INTERRUPT+23) /* Analog Comparator */
#define SAM_IRQ_DAC (SAM_IRQ_INTERRUPT+24) /* Digital-to-Analog Converter */
#define SAM_IRQ_PTC (SAM_IRQ_INTERRUPT+25) /* Peripheral Touch Controller */
#define SAM_IRQ_AES (SAM_IRQ_INTERRUPT+26) /* Advanced Encryption Standard Module */
#define SAM_IRQ_TRNG (SAM_IRQ_INTERRUPT+27) /* True Random Number Generator */
#define SAM_IRQ_PM (SAM_IRQ_INTERRUPT + 0) /* Power Manager */
#define SAM_IRQ_MCLK (SAM_IRQ_INTERRUPT + 0) /* Main Clock */
#define SAM_IRQ_OSCCTRL (SAM_IRQ_INTERRUPT + 0) /* Oscillators Controller */
#define SAM_IRQ_OSC32KCTRL (SAM_IRQ_INTERRUPT + 0) /* 32KHz scillators Controller */
#define SAM_IRQ_SUPC (SAM_IRQ_INTERRUPT + 0) /* Supply Controller */
#define SAM_IRQ_PACC (SAM_IRQ_INTERRUPT + 0) /* Protection Access Controller */
#define SAM_IRQ_WDT (SAM_IRQ_INTERRUPT + 1) /* Watchdog Timer */
#define SAM_IRQ_RTC (SAM_IRQ_INTERRUPT + 2) /* Real Time Counter */
#define SAM_IRQ_EIC (SAM_IRQ_INTERRUPT + 3) /* External Interrupt Controller */
#define SAM_IRQ_NVMCTRL (SAM_IRQ_INTERRUPT + 4) /* Non-Volatile Memory Controller */
#define SAM_IRQ_DMAC (SAM_IRQ_INTERRUPT + 5) /* Direct Memory Access Controller */
#define SAM_IRQ_USB (SAM_IRQ_INTERRUPT + 6) /* Universal Serial Bus */
#define SAM_IRQ_EVSYS (SAM_IRQ_INTERRUPT + 7) /* Event System */
#define SAM_IRQ_SERCOM0 (SAM_IRQ_INTERRUPT + 8) /* Serial Communication Interface 0 */
#define SAM_IRQ_SERCOM1 (SAM_IRQ_INTERRUPT + 9) /* Serial Communication Interface 1 */
#define SAM_IRQ_SERCOM2 (SAM_IRQ_INTERRUPT + 10) /* Serial Communication Interface 2 */
#define SAM_IRQ_SERCOM3 (SAM_IRQ_INTERRUPT + 11) /* Serial Communication Interface 3 */
#define SAM_IRQ_SERCOM4 (SAM_IRQ_INTERRUPT + 12) /* Serial Communication Interface 4 */
#define SAM_IRQ_SERCOM5 (SAM_IRQ_INTERRUPT + 13) /* Serial Communication Interface 5 */
#define SAM_IRQ_TCC0 (SAM_IRQ_INTERRUPT + 14) /* Timer/Counter for Control 0 */
#define SAM_IRQ_TCC1 (SAM_IRQ_INTERRUPT + 15) /* Timer/Counter for Control 1 */
#define SAM_IRQ_TCC2 (SAM_IRQ_INTERRUPT + 16) /* Timer/Counter for Control 2 */
#define SAM_IRQ_TC0 (SAM_IRQ_INTERRUPT + 17) /* Timer/Counter 0 */
#define SAM_IRQ_TC1 (SAM_IRQ_INTERRUPT + 18) /* Timer/Counter 1 */
#define SAM_IRQ_TC2 (SAM_IRQ_INTERRUPT + 19) /* Timer/Counter 2 */
#define SAM_IRQ_TC3 (SAM_IRQ_INTERRUPT + 20) /* Timer/Counter 3 */
#define SAM_IRQ_TC4 (SAM_IRQ_INTERRUPT + 21) /* Timer/Counter 4 */
#define SAM_IRQ_ADC (SAM_IRQ_INTERRUPT + 22) /* Analog-to-Digital Converter */
#define SAM_IRQ_AC (SAM_IRQ_INTERRUPT + 23) /* Analog Comparator */
#define SAM_IRQ_DAC (SAM_IRQ_INTERRUPT + 24) /* Digital-to-Analog Converter */
#define SAM_IRQ_PTC (SAM_IRQ_INTERRUPT + 25) /* Peripheral Touch Controller */
#define SAM_IRQ_AES (SAM_IRQ_INTERRUPT + 26) /* Advanced Encryption Standard Module */
#define SAM_IRQ_TRNG (SAM_IRQ_INTERRUPT + 27) /* True Random Number Generator */
#define SAM_IRQ_NINTS (28) /* Total number of interrupts */
#define SAM_IRQ_NIRQS (SAM_IRQ_INTERRUPT+28) /* The number of real interrupts */
#define SAM_IRQ_NINTS (28) /* Total number of interrupts */
#define SAM_IRQ_NIRQS (SAM_IRQ_INTERRUPT + 28) /* The number of real interrupts */
/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
#ifdef CONFIG_SAMDL_GPIOIRQ
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
# define SAM_IRQ_EXTINT3 (SAM_IRQ_NIRQS+3) /* External interrupt 3 */
# define SAM_IRQ_EXTINT4 (SAM_IRQ_NIRQS+4) /* External interrupt 4 */
# define SAM_IRQ_EXTINT5 (SAM_IRQ_NIRQS+5) /* External interrupt 5 */
# define SAM_IRQ_EXTINT6 (SAM_IRQ_NIRQS+6) /* External interrupt 6 */
# define SAM_IRQ_EXTINT7 (SAM_IRQ_NIRQS+7) /* External interrupt 7 */
# define SAM_IRQ_EXTINT8 (SAM_IRQ_NIRQS+8) /* External interrupt 8 */
# define SAM_IRQ_EXTINT9 (SAM_IRQ_NIRQS+9) /* External interrupt 9 */
# define SAM_IRQ_EXTINT10 (SAM_IRQ_NIRQS+10) /* External interrupt 10 */
# define SAM_IRQ_EXTINT11 (SAM_IRQ_NIRQS+11) /* External interrupt 11 */
# define SAM_IRQ_EXTINT12 (SAM_IRQ_NIRQS+12) /* External interrupt 12 */
# define SAM_IRQ_EXTINT13 (SAM_IRQ_NIRQS+13) /* External interrupt 13 */
# define SAM_IRQ_EXTINT14 (SAM_IRQ_NIRQS+14) /* External interrupt 14 */
# define SAM_IRQ_EXTINT15 (SAM_IRQ_NIRQS+15) /* External interrupt 15 */
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS + 0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS + 1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS + 2) /* External interrupt 2 */
# define SAM_IRQ_EXTINT3 (SAM_IRQ_NIRQS + 3) /* External interrupt 3 */
# define SAM_IRQ_EXTINT4 (SAM_IRQ_NIRQS + 4) /* External interrupt 4 */
# define SAM_IRQ_EXTINT5 (SAM_IRQ_NIRQS + 5) /* External interrupt 5 */
# define SAM_IRQ_EXTINT6 (SAM_IRQ_NIRQS + 6) /* External interrupt 6 */
# define SAM_IRQ_EXTINT7 (SAM_IRQ_NIRQS + 7) /* External interrupt 7 */
# define SAM_IRQ_EXTINT8 (SAM_IRQ_NIRQS + 8) /* External interrupt 8 */
# define SAM_IRQ_EXTINT9 (SAM_IRQ_NIRQS + 9) /* External interrupt 9 */
# define SAM_IRQ_EXTINT10 (SAM_IRQ_NIRQS + 10) /* External interrupt 10 */
# define SAM_IRQ_EXTINT11 (SAM_IRQ_NIRQS + 11) /* External interrupt 11 */
# define SAM_IRQ_EXTINT12 (SAM_IRQ_NIRQS + 12) /* External interrupt 12 */
# define SAM_IRQ_EXTINT13 (SAM_IRQ_NIRQS + 13) /* External interrupt 13 */
# define SAM_IRQ_EXTINT14 (SAM_IRQ_NIRQS + 14) /* External interrupt 14 */
# define SAM_IRQ_EXTINT15 (SAM_IRQ_NIRQS + 15) /* External interrupt 15 */
# define SAM_IRQ_NEXTINTS 16
#else
# define SAM_IRQ_NEXTINTS 0
@ -113,7 +113,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_INTERRUPT + SAM_IRQ_NINTS + SAM_IRQ_NEXTINTS)
/****************************************************************************************

1
arch/arm/include/samv7/same70_irq.h
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@ -399,7 +399,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \
SAM_NGPIODIRQS + SAM_NGPIOEIRQS)

1
arch/arm/include/samv7/samv71_irq.h
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@ -399,7 +399,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \
SAM_NGPIODIRQS + SAM_NGPIOEIRQS)

1
arch/arm/include/stm32f0/irq.h
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@ -108,7 +108,6 @@
#define STM32F0_IRQ_CEC_CAN (46) /* Vector 46: HDMI CEC and CAN */
#define STM32F0_IRQ_USB (47) /* Vector 47: USB */
#define NR_VECTORS (48) /* 48 vectors */
#define NR_IRQS (48) /* 32 interrupts plus 16 exceptions */
/****************************************************************************

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arch/arm/include/stm32f7/stm32f72xx73xx_irq.h
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@ -62,110 +62,109 @@
* External interrupts (vectors >= 16)
*/
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
#define STM32_IRQ_FMC (STM32_IRQ_FIRST+48) /* 48: FMC global interrupt */
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Stream 0 global interrupt */
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Stream 1 global interrupt */
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Stream 2 global interrupt */
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Stream 3 global interrupt */
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Stream 4 global interrupt */
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Stream 5 global interrupt */
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Stream 6 global interrupt */
#define STM32_IRQ_ADC (STM32_IRQ_FIRST + 18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 24) /* 24: TIM9 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 25) /* 25: TIM10 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 26) /* 26: TIM11 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST + 42) /* 42: USB On-The-Go FS Wakeup through EXTI */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 43) /* 43: TIM12 global interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 44) /* 44: TIM13 global interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 45) /* 45: TIM14 global interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST + 47) /* 47: DMA1 Stream 7 global interrupt */
#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 48) /* 48: FMC global interrupt */
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Stream 0 global interrupt */
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Stream 1 global interrupt */
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Stream 2 global interrupt */
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Stream 3 global interrupt */
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Stream 4 global interrupt */
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Stream 5 global interrupt */
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Stream 6 global interrupt */
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST + 70) /* 70: DMA2 Stream 7 global interrupt */
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 71) /* 71: USART6 global interrupt */
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST + 74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST + 75) /* 75: USB On The Go HS End Point 1 In global interrupt */
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST + 76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST + 77) /* 77: USB On The Go HS global interrupt */
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */
#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST + 79) /* 79: CRYP crypto global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
#define STM32_IRQ_UART7 (STM32_IRQ_FIRST + 82) /* 82: UART7 global interrupt */
#define STM32_IRQ_UART8 (STM32_IRQ_FIRST + 83) /* 83: UART8 global interrupt */
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 84) /* 84: SPI4 global interrupt */
#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST + 85) /* 85: SPI5 global interrupt */
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 87) /* 87: SAI1 global interrupt */
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */
#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 92) /* 92: QuadSPI global interrupt */
#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST + 93) /* 93: LP Timer1 global interrupt */
#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST+103) /* 103: SDMMC2 global interrupt */
#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST + 103) /* 103: SDMMC2 global interrupt */
#define NR_INTERRUPTS 103
#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
#define STM32_IRQ_NEXTINTS 104
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************************************
* Public Types

219
arch/arm/include/stm32f7/stm32f74xx75xx_irq.h
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@ -57,120 +57,119 @@
* External interrupts (vectors >= 16)
*/
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
#define STM32_IRQ_FMC (STM32_IRQ_FIRST+48) /* 48: FMC global interrupt */
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */
#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */
#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 global interrupt */
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */
#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LCD-TFT global interrupt */
#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LCD-TFT global Error interrupt */
#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D global interrupt */
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */
#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */
#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+94) /* 94: HDMI-CEC global interrupt */
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+95) /* 95: I2C4 event interrupt */
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+96) /* 96: I2C4 Error interrupt */
#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+97) /* 97: SPDIFRX global interrupt */
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Stream 0 global interrupt */
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Stream 1 global interrupt */
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Stream 2 global interrupt */
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Stream 3 global interrupt */
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Stream 4 global interrupt */
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Stream 5 global interrupt */
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Stream 6 global interrupt */
#define STM32_IRQ_ADC (STM32_IRQ_FIRST + 18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 24) /* 24: TIM9 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 25) /* 25: TIM10 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 26) /* 26: TIM11 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST + 42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 43) /* 43: TIM12 global interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 44) /* 44: TIM13 global interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 45) /* 45: TIM14 global interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST + 47) /* 47: DMA1 Stream 7 global interrupt */
#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 48) /* 48: FMC global interrupt */
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Stream 0 global interrupt */
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Stream 1 global interrupt */
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Stream 2 global interrupt */
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Stream 3 global interrupt */
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Stream 4 global interrupt */
#define STM32_IRQ_ETH (STM32_IRQ_FIRST + 61) /* 61: Ethernet global interrupt */
#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST + 62) /* 62: Ethernet Wakeup through EXTI line interrupt */
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST + 63) /* 63: CAN2 TX interrupts */
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST + 64) /* 64: CAN2 RX0 interrupts */
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST + 65) /* 65: CAN2 RX1 interrupt */
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 66) /* 66: CAN2 SCE interrupt */
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Stream 5 global interrupt */
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Stream 6 global interrupt */
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST + 70) /* 70: DMA2 Stream 7 global interrupt */
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 71) /* 71: USART6 global interrupt */
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST + 74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST + 75) /* 75: USB On The Go HS End Point 1 In global interrupt */
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST + 76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST + 77) /* 77: USB On The Go HS global interrupt */
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 78) /* 78: DCMI global interrupt */
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST + 79) /* 79: CRYP crypto global interrupt */
#define STM32_IRQ_HASH (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
#define STM32_IRQ_UART7 (STM32_IRQ_FIRST + 82) /* 82: UART7 global interrupt */
#define STM32_IRQ_UART8 (STM32_IRQ_FIRST + 83) /* 83: UART8 global interrupt */
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 84) /* 84: SPI4 global interrupt */
#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST + 85) /* 85: SPI5 global interrupt */
#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST + 86) /* 86: SPI6 global interrupt */
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 87) /* 87: SAI1 global interrupt */
#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST + 88) /* 88: LCD-TFT global interrupt */
#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST + 89) /* 89: LCD-TFT global Error interrupt */
#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 92) /* 92: QuadSPI global interrupt */
#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST + 93) /* 93: LP Timer1 global interrupt */
#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST + 94) /* 94: HDMI-CEC global interrupt */
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 95) /* 95: I2C4 event interrupt */
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 96) /* 96: I2C4 Error interrupt */
#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST + 97) /* 97: SPDIFRX global interrupt */
#define NR_INTERRUPTS 98
#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
#define STM32_IRQ_NEXTINTS 98
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************************************
* Public Types

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arch/arm/include/stm32f7/stm32f76xx77xx_irq.h
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@ -58,132 +58,131 @@
* External interrupts (vectors >= 16)
*/
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
#define STM32_IRQ_FMC (STM32_IRQ_FIRST+48) /* 48: FMC global interrupt */
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */
#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */
#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 global interrupt */
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */
#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LCD-TFT global interrupt */
#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LCD-TFT global Error interrupt */
#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D global interrupt */
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */
#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */
#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+94) /* 94: HDMI-CEC global interrupt */
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+95) /* 95: I2C4 event interrupt */
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+96) /* 96: I2C4 Error interrupt */
#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+97) /* 97: SPDIFRX global interrupt */
#define STM32_IRQ_DSIHOST (STM32_IRQ_FIRST+98) /* 98: DSI host global interrupt */
#define STM32_IRQ_DFSDM1FLT0 (STM32_IRQ_FIRST+99) /* 99: DFSDM1 Filter 0 global interrupt */
#define STM32_IRQ_DFSDM1FLT1 (STM32_IRQ_FIRST+100) /* 100: DFSDM1 Filter 1 global interrupt */
#define STM32_IRQ_DFSDM1FLT2 (STM32_IRQ_FIRST+101) /* 101: DFSDM1 Filter 2 global interrupt */
#define STM32_IRQ_DFSDM1FLT3 (STM32_IRQ_FIRST+102) /* 102: DFSDM1 Filter 3 global interrupt */
#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST+103) /* 103: SDMMC2 global interrupt */
#define STM32_IRQ_CAN3TX (STM32_IRQ_FIRST+104) /* 104: CAN3 TX interrupt */
#define STM32_IRQ_CAN3RX0 (STM32_IRQ_FIRST+105) /* 105: CAN3 RX0 interrupt */
#define STM32_IRQ_CAN3RX1 (STM32_IRQ_FIRST+106) /* 106: CAN3 RX1 interrupt */
#define STM32_IRQ_CAN3SCE (STM32_IRQ_FIRST+107) /* 107: CAN3 SCE interrupt */
#define STM32_IRQ_JPEG (STM32_IRQ_FIRST+108) /* 108: JPEG global interrupt */
#define STM32_IRQ_MDIOS (STM32_IRQ_FIRST+109) /* 109: MDIO slave global interrupt */
#define STM32_IRQ_WWDG (STM32_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
#define STM32_IRQ_PVD (STM32_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST + 3) /* 3: RTC global interrupt */
#define STM32_IRQ_FLASH (STM32_IRQ_FIRST + 4) /* 4: Flash global interrupt */
#define STM32_IRQ_RCC (STM32_IRQ_FIRST + 5) /* 5: RCC global interrupt */
#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST + 11) /* 11: DMA1 Stream 0 global interrupt */
#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST + 12) /* 12: DMA1 Stream 1 global interrupt */
#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST + 13) /* 13: DMA1 Stream 2 global interrupt */
#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST + 14) /* 14: DMA1 Stream 3 global interrupt */
#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST + 15) /* 15: DMA1 Stream 4 global interrupt */
#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST + 16) /* 16: DMA1 Stream 5 global interrupt */
#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST + 17) /* 17: DMA1 Stream 6 global interrupt */
#define STM32_IRQ_ADC (STM32_IRQ_FIRST + 18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST + 24) /* 24: TIM9 global interrupt */
#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST + 25) /* 25: TIM10 global interrupt */
#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST + 26) /* 26: TIM11 global interrupt */
#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
#define STM32_IRQ_USART1 (STM32_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
#define STM32_IRQ_USART2 (STM32_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
#define STM32_IRQ_USART3 (STM32_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST + 42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST + 43) /* 43: TIM12 global interrupt */
#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST + 44) /* 44: TIM13 global interrupt */
#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST + 45) /* 45: TIM14 global interrupt */
#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST + 47) /* 47: DMA1 Stream 7 global interrupt */
#define STM32_IRQ_FMC (STM32_IRQ_FIRST + 48) /* 48: FMC global interrupt */
#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
#define STM32_IRQ_UART4 (STM32_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
#define STM32_IRQ_UART5 (STM32_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
#define STM32_IRQ_DAC (STM32_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST + 56) /* 56: DMA2 Stream 0 global interrupt */
#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST + 57) /* 57: DMA2 Stream 1 global interrupt */
#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST + 58) /* 58: DMA2 Stream 2 global interrupt */
#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST + 59) /* 59: DMA2 Stream 3 global interrupt */
#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST + 60) /* 60: DMA2 Stream 4 global interrupt */
#define STM32_IRQ_ETH (STM32_IRQ_FIRST + 61) /* 61: Ethernet global interrupt */
#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST + 62) /* 62: Ethernet Wakeup through EXTI line interrupt */
#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST + 63) /* 63: CAN2 TX interrupts */
#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST + 64) /* 64: CAN2 RX0 interrupts */
#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST + 65) /* 65: CAN2 RX1 interrupt */
#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST + 66) /* 66: CAN2 SCE interrupt */
#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST + 68) /* 68: DMA2 Stream 5 global interrupt */
#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST + 69) /* 69: DMA2 Stream 6 global interrupt */
#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST + 70) /* 70: DMA2 Stream 7 global interrupt */
#define STM32_IRQ_USART6 (STM32_IRQ_FIRST + 71) /* 71: USART6 global interrupt */
#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST + 74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST + 75) /* 75: USB On The Go HS End Point 1 In global interrupt */
#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST + 76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST + 77) /* 77: USB On The Go HS global interrupt */
#define STM32_IRQ_DCMI (STM32_IRQ_FIRST + 78) /* 78: DCMI global interrupt */
#define STM32_IRQ_CRYP (STM32_IRQ_FIRST + 79) /* 79: CRYP crypto global interrupt */
#define STM32_IRQ_HASH (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
#define STM32_IRQ_UART7 (STM32_IRQ_FIRST + 82) /* 82: UART7 global interrupt */
#define STM32_IRQ_UART8 (STM32_IRQ_FIRST + 83) /* 83: UART8 global interrupt */
#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST + 84) /* 84: SPI4 global interrupt */
#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST + 85) /* 85: SPI5 global interrupt */
#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST + 86) /* 86: SPI6 global interrupt */
#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST + 87) /* 87: SAI1 global interrupt */
#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST + 88) /* 88: LCD-TFT global interrupt */
#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST + 89) /* 89: LCD-TFT global Error interrupt */
#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST + 91) /* 91: SAI2 global interrupt */
#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST + 92) /* 92: QuadSPI global interrupt */
#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST + 93) /* 93: LP Timer1 global interrupt */
#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST + 94) /* 94: HDMI-CEC global interrupt */
#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST + 95) /* 95: I2C4 event interrupt */
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 96) /* 96: I2C4 Error interrupt */
#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST + 97) /* 97: SPDIFRX global interrupt */
#define STM32_IRQ_DSIHOST (STM32_IRQ_FIRST + 98) /* 98: DSI host global interrupt */
#define STM32_IRQ_DFSDM1FLT0 (STM32_IRQ_FIRST + 99) /* 99: DFSDM1 Filter 0 global interrupt */
#define STM32_IRQ_DFSDM1FLT1 (STM32_IRQ_FIRST + 100) /* 100: DFSDM1 Filter 1 global interrupt */
#define STM32_IRQ_DFSDM1FLT2 (STM32_IRQ_FIRST + 101) /* 101: DFSDM1 Filter 2 global interrupt */
#define STM32_IRQ_DFSDM1FLT3 (STM32_IRQ_FIRST + 102) /* 102: DFSDM1 Filter 3 global interrupt */
#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST + 103) /* 103: SDMMC2 global interrupt */
#define STM32_IRQ_CAN3TX (STM32_IRQ_FIRST + 104) /* 104: CAN3 TX interrupt */
#define STM32_IRQ_CAN3RX0 (STM32_IRQ_FIRST + 105) /* 105: CAN3 RX0 interrupt */
#define STM32_IRQ_CAN3RX1 (STM32_IRQ_FIRST + 106) /* 106: CAN3 RX1 interrupt */
#define STM32_IRQ_CAN3SCE (STM32_IRQ_FIRST + 107) /* 107: CAN3 SCE interrupt */
#define STM32_IRQ_JPEG (STM32_IRQ_FIRST + 108) /* 108: JPEG global interrupt */
#define STM32_IRQ_MDIOS (STM32_IRQ_FIRST + 109) /* 109: MDIO slave global interrupt */
#define NR_INTERRUPTS 110
#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
#define STM32_IRQ_NEXTINTS 110
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************************************
* Public Types

5
arch/arm/include/stm32h7/stm32h7x3xx_irq.h
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@ -214,9 +214,8 @@
#define STM32_IRQ_RESERVED148 (STM32_IRQ_FIRST + 148) /* 148: Reserved */
#define STM32_IRQ_WKUP (STM32_IRQ_FIRST + 149) /* 149: WKUP1 to WKUP6 pins */
#define NR_INTERRUPTS 150
#define NR_VECTORS (STM32_IRQ_FIRST + NR_INTERRUPTS)
#define NR_IRQS NR_VECTORS
#define STM32_IRQ_NEXTINTS 150
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************************************
* Public Types

172
arch/arm/include/stm32l4/stm32l4x3xx_irq.h
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@ -59,101 +59,99 @@
* External interrupts (vectors >= 16)
*/
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST+11) /* 12: DMA1 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST+12) /* 13: DMA1 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST+13) /* 14: DMA1 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST+14) /* 15: DMA1 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST+15) /* 16: DMA1 Channel 5 global interrupt */
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST+16) /* 17: DMA1 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST+17) /* 17: DMA1 Channel 7 global interrupt */
#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST+18) /* 18: ADC1 global interrupt */
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST+24) /* 24: TIM15 global interrupt */
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST+25) /* 25: TIM16 global interrupt */
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
/* Reserved */ /* 30: TIM4 global interrupt */
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
/* Reserved */ /* 42-48: reserved */
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
/* Reserved */ /* 50: TIM5 global interrupt */
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 12: DMA1 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 13: DMA1 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 14: DMA1 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 15: DMA1 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 16: DMA1 Channel 5 global interrupt */
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 17: DMA1 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
#define STM32L4_IRQ_ADC1 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 global interrupt */
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
/* Reserved */ /* 30: TIM4 global interrupt */
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
/* Reserved */ /* 42-48: reserved */
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
/* Reserved */ /* 50: TIM5 global interrupt */
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
/* Reserved */ /* 53: UART5 global interrupt */
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST+54) /* 54: DAC1 underrun error interrupts */
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST+56) /* 56: DMA2 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST+57) /* 57: DMA2 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST+58) /* 58: DMA2 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST+59) /* 59: DMA2 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST+60) /* 60: DMA2 Channel 5 global interrupt */
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST+61) /* 61: DFSDM0 global interrupt */
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST+62) /* 62: DFSDM1 global interrupt*/
/* Reserved */ /* 63: DFSDM2 global interrupt */
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST+64) /* 64: COMP1/COMP2 interrupts */
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST+65) /* 65: LPTIM1 global interrupt */
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST+66) /* 66: LPTIM2 global interrupt */
#define STM32L4_IRQ_USB_FS (STM32L4_IRQ_FIRST+67) /* 67: USB event interrupt through EXTI line 17 */
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST+68) /* 68: DMA2 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST+69) /* 69: DMA2 Channel 7 global interrupt */
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST+70) /* 70: Low power UART 1 global interrupt */
#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST+71) /* 71: QUADSPI global interrupt */
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST+74) /* 74: SAI1 global interrupt */
/* Reserved */ /* 75: SAI2 global interrupt */
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST+76) /* 76: SWPMI1 global interrupt */
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST+77) /* 77: TSC global interrupt */
#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST+78) /* 78: LCD global interrupt */
#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST+79) /* 79: AES crypto global interrupt */
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST+80) /* 80: RNG global interrupt */
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define STM32L4_IRQ_CRS (STM32L4_IRQ_FIRST+82) /* 82: CRS global interrupt */
#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST+83) /* 83: I2C4 event interrupt */
#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST+84) /* 84: I2C4 error interrupt */
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 underrun error interrupts */
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
/* Reserved */ /* 63: DFSDM2 global interrupt */
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
#define STM32L4_IRQ_USB_FS (STM32L4_IRQ_FIRST + 67) /* 67: USB event interrupt through EXTI line 17 */
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
/* Reserved */ /* 75: SAI2 global interrupt */
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */
#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
#define STM32L4_IRQ_CRS (STM32L4_IRQ_FIRST + 82) /* 82: CRS global interrupt */
#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
#if defined(CONFIG_STM32L4_STM32L4X3)
# define NR_INTERRUPTS 85
# define STM32L4_IRQ_NEXTINTS 85
#else
# error "Unsupported STM32L4 chip"
#endif
#define NR_VECTORS (STM32L4_IRQ_FIRST+NR_INTERRUPTS)
/* (EXTI interrupts do not use IRQ numbers) */
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
/****************************************************************************************************
* Public Types

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arch/arm/include/stm32l4/stm32l4x5xx_irq.h
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@ -60,100 +60,99 @@
* External interrupts (vectors >= 16)
*/
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST+11) /* 11: DMA1 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST+12) /* 12: DMA1 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST+13) /* 13: DMA1 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST+14) /* 14: DMA1 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST+15) /* 15: DMA1 Channel 5 global interrupt */
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST+16) /* 16: DMA1 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST+17) /* 17: DMA1 Channel 7 global interrupt */
#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST+18) /* 18: ADC1 and ADC2 global interrupt */
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST+24) /* 24: TIM15 global interrupt */
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST+25) /* 25: TIM16 global interrupt */
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST+26) /* 26: TIM17 global interrupt */
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST+42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST+47) /* 47: ADC3 global interrupt */
#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST+48) /* 48: FSMC global interrupt */
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST+53) /* 53: UART5 global interrupt */
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST+56) /* 56: DMA2 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST+57) /* 57: DMA2 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST+58) /* 58: DMA2 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST+59) /* 59: DMA2 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST+60) /* 60: DMA2 Channel 5 global interrupt */
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST+61) /* 61: DFSDM0 global interrupt */
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST+62) /* 62: DFSDM1 global interrupt*/
#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST+63) /* 63: DFSDM2 global interrupt */
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST+64) /* 64: COMP1/COMP2 interrupts */
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST+65) /* 65: LPTIM1 global interrupt */
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST+66) /* 66: LPTIM2 global interrupt */
#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST+68) /* 68: DMA2 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST+69) /* 69: DMA2 Channel 7 global interrupt */
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST+70) /* 70: Low power UART 1 global interrupt */
#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST+71) /* 71: QUADSPI global interrupt */
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST+74) /* 74: SAI1 global interrupt */
#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST+75) /* 75: SAI2 global interrupt */
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST+76) /* 76: SWPMI1 global interrupt */
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST+77) /* 77: TSC global interrupt */
#define STM32_IRQ_RESERVED78 (STM32L4_IRQ_FIRST+78) /* 78: Reserved */
#define STM32_IRQ_RESERVED79 (STM32L4_IRQ_FIRST+79) /* 79: Reserved */
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST+80) /* 80: RNG global interrupt */
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */
#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
#define STM32L4_IRQ_RESERVED78 (STM32L4_IRQ_FIRST + 78) /* 78: Reserved */
#define STM32L4_IRQ_RESERVED79 (STM32L4_IRQ_FIRST + 79) /* 79: Reserved */
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
#define NR_INTERRUPTS 82
#define NR_VECTORS (STM32L4_IRQ_FIRST+NR_INTERRUPTS)
#define STM32L4_IRQ_NEXTINTS 82
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
/****************************************************************************************************
* Public Types

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arch/arm/include/stm32l4/stm32l4x6xx_irq.h
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@ -58,119 +58,117 @@
* External interrupts (vectors >= 16)
*/
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST+3) /* 3: RTC global interrupt */
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST+4) /* 4: Flash global interrupt */
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST+5) /* 5: RCC global interrupt */
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST+11) /* 11: DMA1 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST+12) /* 12: DMA1 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST+13) /* 13: DMA1 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST+14) /* 14: DMA1 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST+15) /* 15: DMA1 Channel 5 global interrupt */
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST+16) /* 16: DMA1 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST+17) /* 17: DMA1 Channel 7 global interrupt */
#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST+18) /* 18: ADC1 and ADC2 global interrupt */
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST+24) /* 24: TIM15 global interrupt */
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST+25) /* 25: TIM16 global interrupt */
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST+26) /* 26: TIM17 global interrupt */
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST+37) /* 37: USART1 global interrupt */
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST+38) /* 38: USART2 global interrupt */
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST+39) /* 39: USART3 global interrupt */
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST+42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST+47) /* 47: ADC3 global interrupt */
#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST+48) /* 48: FSMC global interrupt */
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST+52) /* 52: UART4 global interrupt */
#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST+53) /* 53: UART5 global interrupt */
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST+56) /* 56: DMA2 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST+57) /* 57: DMA2 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST+58) /* 58: DMA2 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST+59) /* 59: DMA2 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST+60) /* 60: DMA2 Channel 5 global interrupt */
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST+61) /* 61: DFSDM0 global interrupt */
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST+62) /* 62: DFSDM1 global interrupt*/
#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST+63) /* 63: DFSDM2 global interrupt */
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST+64) /* 64: COMP1/COMP2 interrupts */
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST+65) /* 65: LPTIM1 global interrupt */
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST+66) /* 66: LPTIM2 global interrupt */
#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST+68) /* 68: DMA2 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST+69) /* 69: DMA2 Channel 7 global interrupt */
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST+70) /* 70: Low power UART 1 global interrupt */
#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST+71) /* 71: QUADSPI global interrupt */
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST+74) /* 74: SAI1 global interrupt */
#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST+75) /* 75: SAI2 global interrupt */
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST+76) /* 76: SWPMI1 global interrupt */
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST+77) /* 77: TSC global interrupt */
#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST+78) /* 78: LCD global interrupt */
#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST+79) /* 79: AES crypto global interrupt */
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST+80) /* 80: RNG global interrupt */
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST+81) /* 81: FPU global interrupt */
#define STM32L4_IRQ_WWDG (STM32L4_IRQ_FIRST + 0) /* 0: Window Watchdog interrupt */
#define STM32L4_IRQ_PVD (STM32L4_IRQ_FIRST + 1) /* 1: PVD through EXTI Line detection interrupt */
#define STM32L4_IRQ_TAMPER (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_TIMESTAMP (STM32L4_IRQ_FIRST + 2) /* 2: Tamper and time stamp interrupts */
#define STM32L4_IRQ_RTC_WKUP (STM32L4_IRQ_FIRST + 3) /* 3: RTC global interrupt */
#define STM32L4_IRQ_FLASH (STM32L4_IRQ_FIRST + 4) /* 4: Flash global interrupt */
#define STM32L4_IRQ_RCC (STM32L4_IRQ_FIRST + 5) /* 5: RCC global interrupt */
#define STM32L4_IRQ_EXTI0 (STM32L4_IRQ_FIRST + 6) /* 6: EXTI Line 0 interrupt */
#define STM32L4_IRQ_EXTI1 (STM32L4_IRQ_FIRST + 7) /* 7: EXTI Line 1 interrupt */
#define STM32L4_IRQ_EXTI2 (STM32L4_IRQ_FIRST + 8) /* 8: EXTI Line 2 interrupt */
#define STM32L4_IRQ_EXTI3 (STM32L4_IRQ_FIRST + 9) /* 9: EXTI Line 3 interrupt */
#define STM32L4_IRQ_EXTI4 (STM32L4_IRQ_FIRST + 10) /* 10: EXTI Line 4 interrupt */
#define STM32L4_IRQ_DMA1CH1 (STM32L4_IRQ_FIRST + 11) /* 11: DMA1 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA1CH2 (STM32L4_IRQ_FIRST + 12) /* 12: DMA1 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA1CH3 (STM32L4_IRQ_FIRST + 13) /* 13: DMA1 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA1CH4 (STM32L4_IRQ_FIRST + 14) /* 14: DMA1 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA1CH5 (STM32L4_IRQ_FIRST + 15) /* 15: DMA1 Channel 5 global interrupt */
#define STM32L4_IRQ_DMA1CH6 (STM32L4_IRQ_FIRST + 16) /* 16: DMA1 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA1CH7 (STM32L4_IRQ_FIRST + 17) /* 17: DMA1 Channel 7 global interrupt */
#define STM32L4_IRQ_ADC12 (STM32L4_IRQ_FIRST + 18) /* 18: ADC1 and ADC2 global interrupt */
#define STM32L4_IRQ_CAN1TX (STM32L4_IRQ_FIRST + 19) /* 19: CAN1 TX interrupts */
#define STM32L4_IRQ_CAN1RX0 (STM32L4_IRQ_FIRST + 20) /* 20: CAN1 RX0 interrupts */
#define STM32L4_IRQ_CAN1RX1 (STM32L4_IRQ_FIRST + 21) /* 21: CAN1 RX1 interrupt */
#define STM32L4_IRQ_CAN1SCE (STM32L4_IRQ_FIRST + 22) /* 22: CAN1 SCE interrupt */
#define STM32L4_IRQ_EXTI95 (STM32L4_IRQ_FIRST + 23) /* 23: EXTI Line[9:5] interrupts */
#define STM32L4_IRQ_TIM1BRK (STM32L4_IRQ_FIRST + 24) /* 24: TIM1 Break interrupt */
#define STM32L4_IRQ_TIM15 (STM32L4_IRQ_FIRST + 24) /* 24: TIM15 global interrupt */
#define STM32L4_IRQ_TIM1UP (STM32L4_IRQ_FIRST + 25) /* 25: TIM1 Update interrupt */
#define STM32L4_IRQ_TIM16 (STM32L4_IRQ_FIRST + 25) /* 25: TIM16 global interrupt */
#define STM32L4_IRQ_TIM1TRGCOM (STM32L4_IRQ_FIRST + 26) /* 26: TIM1 Trigger and Commutation interrupts */
#define STM32L4_IRQ_TIM17 (STM32L4_IRQ_FIRST + 26) /* 26: TIM17 global interrupt */
#define STM32L4_IRQ_TIM1CC (STM32L4_IRQ_FIRST + 27) /* 27: TIM1 Capture Compare interrupt */
#define STM32L4_IRQ_TIM2 (STM32L4_IRQ_FIRST + 28) /* 28: TIM2 global interrupt */
#define STM32L4_IRQ_TIM3 (STM32L4_IRQ_FIRST + 29) /* 29: TIM3 global interrupt */
#define STM32L4_IRQ_TIM4 (STM32L4_IRQ_FIRST + 30) /* 30: TIM4 global interrupt */
#define STM32L4_IRQ_I2C1EV (STM32L4_IRQ_FIRST + 31) /* 31: I2C1 event interrupt */
#define STM32L4_IRQ_I2C1ER (STM32L4_IRQ_FIRST + 32) /* 32: I2C1 error interrupt */
#define STM32L4_IRQ_I2C2EV (STM32L4_IRQ_FIRST + 33) /* 33: I2C2 event interrupt */
#define STM32L4_IRQ_I2C2ER (STM32L4_IRQ_FIRST + 34) /* 34: I2C2 error interrupt */
#define STM32L4_IRQ_SPI1 (STM32L4_IRQ_FIRST + 35) /* 35: SPI1 global interrupt */
#define STM32L4_IRQ_SPI2 (STM32L4_IRQ_FIRST + 36) /* 36: SPI2 global interrupt */
#define STM32L4_IRQ_USART1 (STM32L4_IRQ_FIRST + 37) /* 37: USART1 global interrupt */
#define STM32L4_IRQ_USART2 (STM32L4_IRQ_FIRST + 38) /* 38: USART2 global interrupt */
#define STM32L4_IRQ_USART3 (STM32L4_IRQ_FIRST + 39) /* 39: USART3 global interrupt */
#define STM32L4_IRQ_EXTI1510 (STM32L4_IRQ_FIRST + 40) /* 40: EXTI Line[15:10] interrupts */
#define STM32L4_IRQ_RTCALRM (STM32L4_IRQ_FIRST + 41) /* 41: RTC alarm through EXTI line interrupt */
#define STM32L4_IRQ_DFSDM3 (STM32L4_IRQ_FIRST + 42) /* 42: Digital Filter / Sigma Delta Modulator interrupt */
#define STM32L4_IRQ_TIM8BRK (STM32L4_IRQ_FIRST + 43) /* 43: TIM8 Break interrupt */
#define STM32L4_IRQ_TIM8UP (STM32L4_IRQ_FIRST + 44) /* 44: TIM8 Update interrupt */
#define STM32L4_IRQ_TIM8TRGCOM (STM32L4_IRQ_FIRST + 45) /* 45: TIM8 Trigger and Commutation interrupts */
#define STM32L4_IRQ_TIM8CC (STM32L4_IRQ_FIRST + 46) /* 46: TIM8 Capture Compare interrupt */
#define STM32L4_IRQ_ADC3 (STM32L4_IRQ_FIRST + 47) /* 47: ADC3 global interrupt */
#define STM32L4_IRQ_FSMC (STM32L4_IRQ_FIRST + 48) /* 48: FSMC global interrupt */
#define STM32L4_IRQ_SDMMC1 (STM32L4_IRQ_FIRST + 49) /* 49: SDMMC1 global interrupt */
#define STM32L4_IRQ_TIM5 (STM32L4_IRQ_FIRST + 50) /* 50: TIM5 global interrupt */
#define STM32L4_IRQ_SPI3 (STM32L4_IRQ_FIRST + 51) /* 51: SPI3 global interrupt */
#define STM32L4_IRQ_UART4 (STM32L4_IRQ_FIRST + 52) /* 52: UART4 global interrupt */
#define STM32L4_IRQ_UART5 (STM32L4_IRQ_FIRST + 53) /* 53: UART5 global interrupt */
#define STM32L4_IRQ_TIM6 (STM32L4_IRQ_FIRST + 54) /* 54: TIM6 global interrupt */
#define STM32L4_IRQ_DAC (STM32L4_IRQ_FIRST + 54) /* 54: DAC1 and DAC2 underrun error interrupts */
#define STM32L4_IRQ_TIM7 (STM32L4_IRQ_FIRST + 55) /* 55: TIM7 global interrupt */
#define STM32L4_IRQ_DMA2CH1 (STM32L4_IRQ_FIRST + 56) /* 56: DMA2 Channel 1 global interrupt */
#define STM32L4_IRQ_DMA2CH2 (STM32L4_IRQ_FIRST + 57) /* 57: DMA2 Channel 2 global interrupt */
#define STM32L4_IRQ_DMA2CH3 (STM32L4_IRQ_FIRST + 58) /* 58: DMA2 Channel 3 global interrupt */
#define STM32L4_IRQ_DMA2CH4 (STM32L4_IRQ_FIRST + 59) /* 59: DMA2 Channel 4 global interrupt */
#define STM32L4_IRQ_DMA2CH5 (STM32L4_IRQ_FIRST + 60) /* 60: DMA2 Channel 5 global interrupt */
#define STM32L4_IRQ_DFSDM0 (STM32L4_IRQ_FIRST + 61) /* 61: DFSDM0 global interrupt */
#define STM32L4_IRQ_DFSDM1 (STM32L4_IRQ_FIRST + 62) /* 62: DFSDM1 global interrupt*/
#define STM32L4_IRQ_DFSDM2 (STM32L4_IRQ_FIRST + 63) /* 63: DFSDM2 global interrupt */
#define STM32L4_IRQ_COMP (STM32L4_IRQ_FIRST + 64) /* 64: COMP1/COMP2 interrupts */
#define STM32L4_IRQ_LPTIM1 (STM32L4_IRQ_FIRST + 65) /* 65: LPTIM1 global interrupt */
#define STM32L4_IRQ_LPTIM2 (STM32L4_IRQ_FIRST + 66) /* 66: LPTIM2 global interrupt */
#define STM32L4_IRQ_OTGFS (STM32L4_IRQ_FIRST + 67) /* 67: USB On The Go FS global interrupt */
#define STM32L4_IRQ_DMA2CH6 (STM32L4_IRQ_FIRST + 68) /* 68: DMA2 Channel 6 global interrupt */
#define STM32L4_IRQ_DMA2CH7 (STM32L4_IRQ_FIRST + 69) /* 69: DMA2 Channel 7 global interrupt */
#define STM32L4_IRQ_LPUART1 (STM32L4_IRQ_FIRST + 70) /* 70: Low power UART 1 global interrupt */
#define STM32L4_IRQ_QUADSPI (STM32L4_IRQ_FIRST + 71) /* 71: QUADSPI global interrupt */
#define STM32L4_IRQ_I2C3EV (STM32L4_IRQ_FIRST + 72) /* 72: I2C3 event interrupt */
#define STM32L4_IRQ_I2C3ER (STM32L4_IRQ_FIRST + 73) /* 73: I2C3 error interrupt */
#define STM32L4_IRQ_SAI1 (STM32L4_IRQ_FIRST + 74) /* 74: SAI1 global interrupt */
#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
#define STM32L4_IRQ_LCD (STM32L4_IRQ_FIRST + 78) /* 78: LCD global interrupt */
#define STM32L4_IRQ_AES (STM32L4_IRQ_FIRST + 79) /* 79: AES crypto global interrupt */
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
/* STM32L496xx/4A6xx only: */
#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST+82) /* 82: HASH and CRS global interrupt */
#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST+83) /* 83: I2C4 event interrupt */
#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST+84) /* 84: I2C4 error interrupt */
#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST+85) /* 85: DCMI global interrupt */
#define STM32L4_IRQ_CAN2TX (STM32L4_IRQ_FIRST+86) /* 86: CAN2 TX interrupts */
#define STM32L4_IRQ_CAN2RX0 (STM32L4_IRQ_FIRST+87) /* 87: CAN2 RX0 interrupts */
#define STM32L4_IRQ_CAN2RX1 (STM32L4_IRQ_FIRST+88) /* 88: CAN2 RX1 interrupt */
#define STM32L4_IRQ_CAN2SCE (STM32L4_IRQ_FIRST+89) /* 89: CAN2 SCE interrupt */
#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST+90) /* 90: DMA2D global interrupt */
#define STM32L4_IRQ_HASH_CRS (STM32L4_IRQ_FIRST + 82) /* 82: HASH and CRS global interrupt */
#define STM32L4_IRQ_I2C4EV (STM32L4_IRQ_FIRST + 83) /* 83: I2C4 event interrupt */
#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
#define STM32L4_IRQ_DCMI (STM32L4_IRQ_FIRST + 85) /* 85: DCMI global interrupt */
#define STM32L4_IRQ_CAN2TX (STM32L4_IRQ_FIRST + 86) /* 86: CAN2 TX interrupts */
#define STM32L4_IRQ_CAN2RX0 (STM32L4_IRQ_FIRST + 87) /* 87: CAN2 RX0 interrupts */
#define STM32L4_IRQ_CAN2RX1 (STM32L4_IRQ_FIRST + 88) /* 88: CAN2 RX1 interrupt */
#define STM32L4_IRQ_CAN2SCE (STM32L4_IRQ_FIRST + 89) /* 89: CAN2 SCE interrupt */
#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX)
# define NR_INTERRUPTS 82
# define STM32L4_IRQ_NEXTINTS 82
#elif defined(CONFIG_STM32L4_STM32L496XX)
# define NR_INTERRUPTS 91
# define STM32L4_IRQ_NEXTINTS 91
#else
# error "Unsupported STM32L4 chip"
#endif
#define NR_VECTORS (STM32L4_IRQ_FIRST+NR_INTERRUPTS)
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
/****************************************************************************************************
* Public Types

230
arch/arm/include/xmc4/xmc4500_irq.h
View File

@ -75,125 +75,125 @@
* USCI - Universal Serial Interface
*/
#define XMC4_IRQ_SCU (XMC4_IRQ_FIRST+0) /* 0: System Control */
#define XMC4_IRQ_ERU0_SR0 (XMC4_IRQ_FIRST+1) /* 1: ERU0, SR0 */
#define XMC4_IRQ_ERU0_SR1 (XMC4_IRQ_FIRST+2) /* 2: ERU0, SR1 */
#define XMC4_IRQ_ERU0_SR2 (XMC4_IRQ_FIRST+3) /* 3: ERU0, SR2 */
#define XMC4_IRQ_ERU0_SR3 (XMC4_IRQ_FIRST+4) /* 4: ERU0, SR3 */
#define XMC4_IRQ_ERU1_SR0 (XMC4_IRQ_FIRST+5) /* 5: ERU1, SR0 */
#define XMC4_IRQ_ERU1_SR1 (XMC4_IRQ_FIRST+6) /* 6: ERU1, SR1 */
#define XMC4_IRQ_ERU1_SR2 (XMC4_IRQ_FIRST+7) /* 7: ERU1, SR2 */
#define XMC4_IRQ_ERU1_SR3 (XMC4_IRQ_FIRST+8) /* 8: ERU1, SR3 */
#define XMC4_IRQ_RESVD009 (XMC4_IRQ_FIRST+9) /* 9: Reserved */
#define XMC4_IRQ_RESVD010 (XMC4_IRQ_FIRST+10) /* 10: Reserved */
#define XMC4_IRQ_RESVD011 (XMC4_IRQ_FIRST+11) /* 11: Reserved */
#define XMC4_IRQ_PMU1_SR0 (XMC4_IRQ_FIRST+12) /* 12: PMU, SR0 */
#define XMC4_IRQ_RESVD011 (XMC4_IRQ_FIRST+13) /* 13: Reserved */
#define XMC4_IRQ_VADC_COSR0 (XMC4_IRQ_FIRST+14) /* 14: ADC Common Block 0 */
#define XMC4_IRQ_VADC_COSR1 (XMC4_IRQ_FIRST+15) /* 15: ADC Common Block 1 */
#define XMC4_IRQ_VADC_COSR2 (XMC4_IRQ_FIRST+16) /* 16: ADC Common Block 2 */
#define XMC4_IRQ_VADC_COSR3 (XMC4_IRQ_FIRST+17) /* 17: ADC Common Block 3 */
#define XMC4_IRQ_VADC_GOSR0 (XMC4_IRQ_FIRST+18) /* 18: ADC Group 0, SR0 */
#define XMC4_IRQ_VADC_GOSR1 (XMC4_IRQ_FIRST+19) /* 19: ADC Group 0, SR1 */
#define XMC4_IRQ_VADC_GOSR2 (XMC4_IRQ_FIRST+20) /* 20: ADC Group 0, SR2 */
#define XMC4_IRQ_VADC_GOSR3 (XMC4_IRQ_FIRST+21) /* 21: ADC Group 0, SR3 */
#define XMC4_IRQ_VADC_G1SR0 (XMC4_IRQ_FIRST+22) /* 22: ADC Group 1, SR0 */
#define XMC4_IRQ_VADC_G1SR1 (XMC4_IRQ_FIRST+23) /* 23: ADC Group 1, SR1 */
#define XMC4_IRQ_VADC_G1SR2 (XMC4_IRQ_FIRST+24) /* 24: ADC Group 1, SR2 */
#define XMC4_IRQ_VADC_G1SR3 (XMC4_IRQ_FIRST+25) /* 25: ADC Group 1, SR3 */
#define XMC4_IRQ_VADC_G2SR0 (XMC4_IRQ_FIRST+26) /* 26: ADC Group 2, SR0 */
#define XMC4_IRQ_VADC_G2SR1 (XMC4_IRQ_FIRST+27) /* 27: ADC Group 2, SR1 */
#define XMC4_IRQ_VADC_G2SR2 (XMC4_IRQ_FIRST+28) /* 28: ADC Group 2, SR2 */
#define XMC4_IRQ_VADC_G2SR3 (XMC4_IRQ_FIRST+29) /* 29: ADC Group 2, SR3 */
#define XMC4_IRQ_VADC_G3SR0 (XMC4_IRQ_FIRST+30) /* 30: ADC Group 3, SR0 */
#define XMC4_IRQ_VADC_G3SR1 (XMC4_IRQ_FIRST+31) /* 31: ADC Group 3, SR1 */
#define XMC4_IRQ_VADC_G3SR2 (XMC4_IRQ_FIRST+32) /* 32: ADC Group 3, SR2 */
#define XMC4_IRQ_VADC_G3SR3 (XMC4_IRQ_FIRST+33) /* 33: ADC Group 3, SR3 */
#define XMC4_IRQ_DSD_SRM0 (XMC4_IRQ_FIRST+34) /* 34: DSD Main, SRM0 */
#define XMC4_IRQ_DSD_SRM1 (XMC4_IRQ_FIRST+35) /* 35: DSD Main, SRM1 */
#define XMC4_IRQ_DSD_SRM2 (XMC4_IRQ_FIRST+36) /* 36: DSD Main, SRM2 */
#define XMC4_IRQ_DSD_SRM3 (XMC4_IRQ_FIRST+37) /* 37: DSD Main, SRM3 */
#define XMC4_IRQ_DSD_SRA0 (XMC4_IRQ_FIRST+38) /* 38: DSD Auxiliary, SRA0 */
#define XMC4_IRQ_DSD_SRA1 (XMC4_IRQ_FIRST+39) /* 39: DSD Auxiliary, SRA1 */
#define XMC4_IRQ_DSD_SRA2 (XMC4_IRQ_FIRST+40) /* 40: DSD Auxiliary, SRA2 */
#define XMC4_IRQ_DSD_SRA3 (XMC4_IRQ_FIRST+41) /* 41: DSD Auxiliary, SRA3 */
#define XMC4_IRQ_DAC_SR0 (XMC4_IRQ_FIRST+42) /* 42: DAC, SR0 */
#define XMC4_IRQ_DAC_SR1 (XMC4_IRQ_FIRST+43) /* 43: DAC, SR1 */
#define XMC4_IRQ_CCU40_SR0 (XMC4_IRQ_FIRST+44) /* 44: CCU4 Module 0, SR0 */
#define XMC4_IRQ_CCU40_SR1 (XMC4_IRQ_FIRST+45) /* 45: CCU4 Module 0, SR1 */
#define XMC4_IRQ_CCU40_SR2 (XMC4_IRQ_FIRST+46) /* 46: CCU4 Module 0, SR2 */
#define XMC4_IRQ_CCU40_SR3 (XMC4_IRQ_FIRST+47) /* 47: CCU4 Module 0, SR3 */
#define XMC4_IRQ_CCU41_SR0 (XMC4_IRQ_FIRST+48) /* 48: CCU4 Module 1, SR0 */
#define XMC4_IRQ_CCU41_SR1 (XMC4_IRQ_FIRST+49) /* 49: CCU4 Module 1, SR1 */
#define XMC4_IRQ_CCU41_SR2 (XMC4_IRQ_FIRST+50) /* 50: CCU4 Module 1, SR2 */
#define XMC4_IRQ_CCU41_SR3 (XMC4_IRQ_FIRST+51) /* 51: CCU4 Module 1, SR3 */
#define XMC4_IRQ_CCU42_SR0 (XMC4_IRQ_FIRST+52) /* 52: CCU4 Module 2, SR0 */
#define XMC4_IRQ_CCU42_SR1 (XMC4_IRQ_FIRST+53) /* 53: CCU4 Module 2, SR1 */
#define XMC4_IRQ_CCU42_SR2 (XMC4_IRQ_FIRST+54) /* 54: CCU4 Module 2, SR2 */
#define XMC4_IRQ_CCU42_SR3 (XMC4_IRQ_FIRST+55) /* 55: CCU4 Module 2, SR3 */
#define XMC4_IRQ_CCU43_SR0 (XMC4_IRQ_FIRST+56) /* 56: CCU4 Module 3, SR0 */
#define XMC4_IRQ_CCU43_SR1 (XMC4_IRQ_FIRST+57) /* 57: CCU4 Module 3, SR1 */
#define XMC4_IRQ_CCU43_SR2 (XMC4_IRQ_FIRST+58) /* 58: CCU4 Module 3, SR2 */
#define XMC4_IRQ_CCU43_SR3 (XMC4_IRQ_FIRST+59) /* 59: CCU4 Module 3, SR3 */
#define XMC4_IRQ_CCU80_SR0 (XMC4_IRQ_FIRST+60) /* 60: CCU8 Module 0, SR0 */
#define XMC4_IRQ_CCU80_SR1 (XMC4_IRQ_FIRST+61) /* 61: CCU8 Module 0, SR1 */
#define XMC4_IRQ_CCU80_SR2 (XMC4_IRQ_FIRST+62) /* 62: CCU8 Module 0, SR2 */
#define XMC4_IRQ_CCU80_SR3 (XMC4_IRQ_FIRST+63) /* 63: CCU8 Module 0, SR3 */
#define XMC4_IRQ_CCU81_SR0 (XMC4_IRQ_FIRST+64) /* 64: CCU8 Module 1, SR0 */
#define XMC4_IRQ_CCU81_SR1 (XMC4_IRQ_FIRST+65) /* 65: CCU8 Module 1, SR1 */
#define XMC4_IRQ_CCU81_SR2 (XMC4_IRQ_FIRST+66) /* 66: CCU8 Module 1, SR2 */
#define XMC4_IRQ_CCU81_SR3 (XMC4_IRQ_FIRST+67) /* 67: CCU8 Module 1, SR3 */
#define XMC4_IRQ_POSIF0_SR0 (XMC4_IRQ_FIRST+68) /* 68: POSIF Module 0, SR0 */
#define XMC4_IRQ_POSIF0_SR1 (XMC4_IRQ_FIRST+69) /* 69: POSIF Module 0, SR1 */
#define XMC4_IRQ_POSIF1_SR0 (XMC4_IRQ_FIRST+70) /* 70: POSIF Module 1, SR0 */
#define XMC4_IRQ_POSIF1_SR1 (XMC4_IRQ_FIRST+71) /* 71: POSIF Module 1, SR1 */
#define XMC4_IRQ_RESVD072 (XMC4_IRQ_FIRST+72) /* 72: Reserved */
#define XMC4_IRQ_RESVD073 (XMC4_IRQ_FIRST+73) /* 73: Reserved */
#define XMC4_IRQ_RESVD074 (XMC4_IRQ_FIRST+74) /* 74: Reserved */
#define XMC4_IRQ_RESVD075 (XMC4_IRQ_FIRST+75) /* 75: Reserved */
#define XMC4_IRQ_CAN_SR0 (XMC4_IRQ_FIRST+76) /* 76: MultiCAN, SR0 */
#define XMC4_IRQ_CAN_SR1 (XMC4_IRQ_FIRST+77) /* 77: MultiCAN, SR1 */
#define XMC4_IRQ_CAN_SR2 (XMC4_IRQ_FIRST+78) /* 78: MultiCAN, SR2 */
#define XMC4_IRQ_CAN_SR3 (XMC4_IRQ_FIRST+79) /* 79: MultiCAN, SR3 */
#define XMC4_IRQ_CAN_SR4 (XMC4_IRQ_FIRST+80) /* 80: MultiCAN, SR4 */
#define XMC4_IRQ_CAN_SR5 (XMC4_IRQ_FIRST+81) /* 81: MultiCAN, SR5 */
#define XMC4_IRQ_CAN_SR6 (XMC4_IRQ_FIRST+82) /* 82: MultiCAN, SR6 */
#define XMC4_IRQ_CAN_SR7 (XMC4_IRQ_FIRST+83) /* 83: MultiCAN, SR7 */
#define XMC4_IRQ_USIC0_SR0 (XMC4_IRQ_FIRST+84) /* 84: USIC0 Channel, SR0 */
#define XMC4_IRQ_USIC0_SR1 (XMC4_IRQ_FIRST+85) /* 85: USIC0 Channel, SR1 */
#define XMC4_IRQ_USIC0_SR2 (XMC4_IRQ_FIRST+86) /* 86: USIC0 Channel, SR2 */
#define XMC4_IRQ_USIC0_SR3 (XMC4_IRQ_FIRST+87) /* 87: USIC0 Channel, SR3 */
#define XMC4_IRQ_USIC0_SR4 (XMC4_IRQ_FIRST+88) /* 88: USIC0 Channel, SR4 */
#define XMC4_IRQ_USIC0_SR5 (XMC4_IRQ_FIRST+89) /* 89: USIC0 Channel, SR5 */
#define XMC4_IRQ_USIC1_SR0 (XMC4_IRQ_FIRST+90) /* 90: USIC1 Channel, SR0 */
#define XMC4_IRQ_USIC1_SR1 (XMC4_IRQ_FIRST+91) /* 91: USIC1 Channel, SR1 */
#define XMC4_IRQ_USIC1_SR2 (XMC4_IRQ_FIRST+92) /* 92: USIC1 Channel, SR2 */
#define XMC4_IRQ_USIC1_SR3 (XMC4_IRQ_FIRST+93) /* 93: USIC1 Channel, SR3 */
#define XMC4_IRQ_USIC1_SR4 (XMC4_IRQ_FIRST+94) /* 94: USIC1 Channel, SR4 */
#define XMC4_IRQ_USIC1_SR5 (XMC4_IRQ_FIRST+95) /* 95: USIC1 Channel, SR5 */
#define XMC4_IRQ_USIC2_SR0 (XMC4_IRQ_FIRST+96) /* 96: USIC2 Channel, SR0 */
#define XMC4_IRQ_USIC2_SR1 (XMC4_IRQ_FIRST+97) /* 97: USIC2 Channel, SR1 */
#define XMC4_IRQ_USIC2_SR2 (XMC4_IRQ_FIRST+98) /* 98: USIC2 Channel, SR2 */
#define XMC4_IRQ_USIC2_SR3 (XMC4_IRQ_FIRST+99) /* 99: USIC2 Channel, SR3 */
#define XMC4_IRQ_USIC2_SR4 (XMC4_IRQ_FIRST+100) /* 100: USIC2 Channel, SR4 */
#define XMC4_IRQ_USIC2_SR5 (XMC4_IRQ_FIRST+101) /* 101: USIC2 Channel, SR5 */
#define XMC4_IRQ_LEDTS0_SR0 (XMC4_IRQ_FIRST+102) /* 102: LEDTS0, SR0 */
#define XMC4_IRQ_RESVD103 (XMC4_IRQ_FIRST+103) /* 103: Reserved */
#define XMC4_IRQ_FCR_SR0 (XMC4_IRQ_FIRST+104) /* 102: FCE, SR0 */
#define XMC4_IRQ_GPCMA0_SR0 (XMC4_IRQ_FIRST+105) /* 105: GPDMA0, SR0 */
#define XMC4_IRQ_SDMMC_SR0 (XMC4_IRQ_FIRST+106) /* 106: SDMMC, SR0 */
#define XMC4_IRQ_USB0_SR0 (XMC4_IRQ_FIRST+107) /* 107: USB, SR0 */
#define XMC4_IRQ_ETH0_SR0 (XMC4_IRQ_FIRST+108) /* 108: Ethernet, module 0, SR0 */
#define XMC4_IRQ_ECAT0_SR0 (XMC4_IRQ_FIRST+109) /* 109: EtherCAT, module 0, SR0 */
#define XMC4_IRQ_GPCMA1_SR0 (XMC4_IRQ_FIRST+110) /* 110: GPDMA1, SR0 */
#define XMC4_IRQ_RESVD111 (XMC4_IRQ_FIRST+111) /* 111: Reserved */
#define XMC4_IRQ_SCU (XMC4_IRQ_FIRST + 0) /* 0: System Control */
#define XMC4_IRQ_ERU0_SR0 (XMC4_IRQ_FIRST + 1) /* 1: ERU0, SR0 */
#define XMC4_IRQ_ERU0_SR1 (XMC4_IRQ_FIRST + 2) /* 2: ERU0, SR1 */
#define XMC4_IRQ_ERU0_SR2 (XMC4_IRQ_FIRST + 3) /* 3: ERU0, SR2 */
#define XMC4_IRQ_ERU0_SR3 (XMC4_IRQ_FIRST + 4) /* 4: ERU0, SR3 */
#define XMC4_IRQ_ERU1_SR0 (XMC4_IRQ_FIRST + 5) /* 5: ERU1, SR0 */
#define XMC4_IRQ_ERU1_SR1 (XMC4_IRQ_FIRST + 6) /* 6: ERU1, SR1 */
#define XMC4_IRQ_ERU1_SR2 (XMC4_IRQ_FIRST + 7) /* 7: ERU1, SR2 */
#define XMC4_IRQ_ERU1_SR3 (XMC4_IRQ_FIRST + 8) /* 8: ERU1, SR3 */
#define XMC4_IRQ_RESVD009 (XMC4_IRQ_FIRST + 9) /* 9: Reserved */
#define XMC4_IRQ_RESVD010 (XMC4_IRQ_FIRST + 10) /* 10: Reserved */
#define XMC4_IRQ_RESVD011 (XMC4_IRQ_FIRST + 11) /* 11: Reserved */
#define XMC4_IRQ_PMU1_SR0 (XMC4_IRQ_FIRST + 12) /* 12: PMU, SR0 */
#define XMC4_IRQ_RESVD011 (XMC4_IRQ_FIRST + 13) /* 13: Reserved */
#define XMC4_IRQ_VADC_COSR0 (XMC4_IRQ_FIRST + 14) /* 14: ADC Common Block 0 */
#define XMC4_IRQ_VADC_COSR1 (XMC4_IRQ_FIRST + 15) /* 15: ADC Common Block 1 */
#define XMC4_IRQ_VADC_COSR2 (XMC4_IRQ_FIRST + 16) /* 16: ADC Common Block 2 */
#define XMC4_IRQ_VADC_COSR3 (XMC4_IRQ_FIRST + 17) /* 17: ADC Common Block 3 */
#define XMC4_IRQ_VADC_GOSR0 (XMC4_IRQ_FIRST + 18) /* 18: ADC Group 0, SR0 */
#define XMC4_IRQ_VADC_GOSR1 (XMC4_IRQ_FIRST + 19) /* 19: ADC Group 0, SR1 */
#define XMC4_IRQ_VADC_GOSR2 (XMC4_IRQ_FIRST + 20) /* 20: ADC Group 0, SR2 */
#define XMC4_IRQ_VADC_GOSR3 (XMC4_IRQ_FIRST + 21) /* 21: ADC Group 0, SR3 */
#define XMC4_IRQ_VADC_G1SR0 (XMC4_IRQ_FIRST + 22) /* 22: ADC Group 1, SR0 */
#define XMC4_IRQ_VADC_G1SR1 (XMC4_IRQ_FIRST + 23) /* 23: ADC Group 1, SR1 */
#define XMC4_IRQ_VADC_G1SR2 (XMC4_IRQ_FIRST + 24) /* 24: ADC Group 1, SR2 */
#define XMC4_IRQ_VADC_G1SR3 (XMC4_IRQ_FIRST + 25) /* 25: ADC Group 1, SR3 */
#define XMC4_IRQ_VADC_G2SR0 (XMC4_IRQ_FIRST + 26) /* 26: ADC Group 2, SR0 */
#define XMC4_IRQ_VADC_G2SR1 (XMC4_IRQ_FIRST + 27) /* 27: ADC Group 2, SR1 */
#define XMC4_IRQ_VADC_G2SR2 (XMC4_IRQ_FIRST + 28) /* 28: ADC Group 2, SR2 */
#define XMC4_IRQ_VADC_G2SR3 (XMC4_IRQ_FIRST + 29) /* 29: ADC Group 2, SR3 */
#define XMC4_IRQ_VADC_G3SR0 (XMC4_IRQ_FIRST + 30) /* 30: ADC Group 3, SR0 */
#define XMC4_IRQ_VADC_G3SR1 (XMC4_IRQ_FIRST + 31) /* 31: ADC Group 3, SR1 */
#define XMC4_IRQ_VADC_G3SR2 (XMC4_IRQ_FIRST + 32) /* 32: ADC Group 3, SR2 */
#define XMC4_IRQ_VADC_G3SR3 (XMC4_IRQ_FIRST + 33) /* 33: ADC Group 3, SR3 */
#define XMC4_IRQ_DSD_SRM0 (XMC4_IRQ_FIRST + 34) /* 34: DSD Main, SRM0 */
#define XMC4_IRQ_DSD_SRM1 (XMC4_IRQ_FIRST + 35) /* 35: DSD Main, SRM1 */
#define XMC4_IRQ_DSD_SRM2 (XMC4_IRQ_FIRST + 36) /* 36: DSD Main, SRM2 */
#define XMC4_IRQ_DSD_SRM3 (XMC4_IRQ_FIRST + 37) /* 37: DSD Main, SRM3 */
#define XMC4_IRQ_DSD_SRA0 (XMC4_IRQ_FIRST + 38) /* 38: DSD Auxiliary, SRA0 */
#define XMC4_IRQ_DSD_SRA1 (XMC4_IRQ_FIRST + 39) /* 39: DSD Auxiliary, SRA1 */
#define XMC4_IRQ_DSD_SRA2 (XMC4_IRQ_FIRST + 40) /* 40: DSD Auxiliary, SRA2 */
#define XMC4_IRQ_DSD_SRA3 (XMC4_IRQ_FIRST + 41) /* 41: DSD Auxiliary, SRA3 */
#define XMC4_IRQ_DAC_SR0 (XMC4_IRQ_FIRST + 42) /* 42: DAC, SR0 */
#define XMC4_IRQ_DAC_SR1 (XMC4_IRQ_FIRST + 43) /* 43: DAC, SR1 */
#define XMC4_IRQ_CCU40_SR0 (XMC4_IRQ_FIRST + 44) /* 44: CCU4 Module 0, SR0 */
#define XMC4_IRQ_CCU40_SR1 (XMC4_IRQ_FIRST + 45) /* 45: CCU4 Module 0, SR1 */
#define XMC4_IRQ_CCU40_SR2 (XMC4_IRQ_FIRST + 46) /* 46: CCU4 Module 0, SR2 */
#define XMC4_IRQ_CCU40_SR3 (XMC4_IRQ_FIRST + 47) /* 47: CCU4 Module 0, SR3 */
#define XMC4_IRQ_CCU41_SR0 (XMC4_IRQ_FIRST + 48) /* 48: CCU4 Module 1, SR0 */
#define XMC4_IRQ_CCU41_SR1 (XMC4_IRQ_FIRST + 49) /* 49: CCU4 Module 1, SR1 */
#define XMC4_IRQ_CCU41_SR2 (XMC4_IRQ_FIRST + 50) /* 50: CCU4 Module 1, SR2 */
#define XMC4_IRQ_CCU41_SR3 (XMC4_IRQ_FIRST + 51) /* 51: CCU4 Module 1, SR3 */
#define XMC4_IRQ_CCU42_SR0 (XMC4_IRQ_FIRST + 52) /* 52: CCU4 Module 2, SR0 */
#define XMC4_IRQ_CCU42_SR1 (XMC4_IRQ_FIRST + 53) /* 53: CCU4 Module 2, SR1 */
#define XMC4_IRQ_CCU42_SR2 (XMC4_IRQ_FIRST + 54) /* 54: CCU4 Module 2, SR2 */
#define XMC4_IRQ_CCU42_SR3 (XMC4_IRQ_FIRST + 55) /* 55: CCU4 Module 2, SR3 */
#define XMC4_IRQ_CCU43_SR0 (XMC4_IRQ_FIRST + 56) /* 56: CCU4 Module 3, SR0 */
#define XMC4_IRQ_CCU43_SR1 (XMC4_IRQ_FIRST + 57) /* 57: CCU4 Module 3, SR1 */
#define XMC4_IRQ_CCU43_SR2 (XMC4_IRQ_FIRST + 58) /* 58: CCU4 Module 3, SR2 */
#define XMC4_IRQ_CCU43_SR3 (XMC4_IRQ_FIRST + 59) /* 59: CCU4 Module 3, SR3 */
#define XMC4_IRQ_CCU80_SR0 (XMC4_IRQ_FIRST + 60) /* 60: CCU8 Module 0, SR0 */
#define XMC4_IRQ_CCU80_SR1 (XMC4_IRQ_FIRST + 61) /* 61: CCU8 Module 0, SR1 */
#define XMC4_IRQ_CCU80_SR2 (XMC4_IRQ_FIRST + 62) /* 62: CCU8 Module 0, SR2 */
#define XMC4_IRQ_CCU80_SR3 (XMC4_IRQ_FIRST + 63) /* 63: CCU8 Module 0, SR3 */
#define XMC4_IRQ_CCU81_SR0 (XMC4_IRQ_FIRST + 64) /* 64: CCU8 Module 1, SR0 */
#define XMC4_IRQ_CCU81_SR1 (XMC4_IRQ_FIRST + 65) /* 65: CCU8 Module 1, SR1 */
#define XMC4_IRQ_CCU81_SR2 (XMC4_IRQ_FIRST + 66) /* 66: CCU8 Module 1, SR2 */
#define XMC4_IRQ_CCU81_SR3 (XMC4_IRQ_FIRST + 67) /* 67: CCU8 Module 1, SR3 */
#define XMC4_IRQ_POSIF0_SR0 (XMC4_IRQ_FIRST + 68) /* 68: POSIF Module 0, SR0 */
#define XMC4_IRQ_POSIF0_SR1 (XMC4_IRQ_FIRST + 69) /* 69: POSIF Module 0, SR1 */
#define XMC4_IRQ_POSIF1_SR0 (XMC4_IRQ_FIRST + 70) /* 70: POSIF Module 1, SR0 */
#define XMC4_IRQ_POSIF1_SR1 (XMC4_IRQ_FIRST + 71) /* 71: POSIF Module 1, SR1 */
#define XMC4_IRQ_RESVD072 (XMC4_IRQ_FIRST + 72) /* 72: Reserved */
#define XMC4_IRQ_RESVD073 (XMC4_IRQ_FIRST + 73) /* 73: Reserved */
#define XMC4_IRQ_RESVD074 (XMC4_IRQ_FIRST + 74) /* 74: Reserved */
#define XMC4_IRQ_RESVD075 (XMC4_IRQ_FIRST + 75) /* 75: Reserved */
#define XMC4_IRQ_CAN_SR0 (XMC4_IRQ_FIRST + 76) /* 76: MultiCAN, SR0 */
#define XMC4_IRQ_CAN_SR1 (XMC4_IRQ_FIRST + 77) /* 77: MultiCAN, SR1 */
#define XMC4_IRQ_CAN_SR2 (XMC4_IRQ_FIRST + 78) /* 78: MultiCAN, SR2 */
#define XMC4_IRQ_CAN_SR3 (XMC4_IRQ_FIRST + 79) /* 79: MultiCAN, SR3 */
#define XMC4_IRQ_CAN_SR4 (XMC4_IRQ_FIRST + 80) /* 80: MultiCAN, SR4 */
#define XMC4_IRQ_CAN_SR5 (XMC4_IRQ_FIRST + 81) /* 81: MultiCAN, SR5 */
#define XMC4_IRQ_CAN_SR6 (XMC4_IRQ_FIRST + 82) /* 82: MultiCAN, SR6 */
#define XMC4_IRQ_CAN_SR7 (XMC4_IRQ_FIRST + 83) /* 83: MultiCAN, SR7 */
#define XMC4_IRQ_USIC0_SR0 (XMC4_IRQ_FIRST + 84) /* 84: USIC0 Channel, SR0 */
#define XMC4_IRQ_USIC0_SR1 (XMC4_IRQ_FIRST + 85) /* 85: USIC0 Channel, SR1 */
#define XMC4_IRQ_USIC0_SR2 (XMC4_IRQ_FIRST + 86) /* 86: USIC0 Channel, SR2 */
#define XMC4_IRQ_USIC0_SR3 (XMC4_IRQ_FIRST + 87) /* 87: USIC0 Channel, SR3 */
#define XMC4_IRQ_USIC0_SR4 (XMC4_IRQ_FIRST + 88) /* 88: USIC0 Channel, SR4 */
#define XMC4_IRQ_USIC0_SR5 (XMC4_IRQ_FIRST + 89) /* 89: USIC0 Channel, SR5 */
#define XMC4_IRQ_USIC1_SR0 (XMC4_IRQ_FIRST + 90) /* 90: USIC1 Channel, SR0 */
#define XMC4_IRQ_USIC1_SR1 (XMC4_IRQ_FIRST + 91) /* 91: USIC1 Channel, SR1 */
#define XMC4_IRQ_USIC1_SR2 (XMC4_IRQ_FIRST + 92) /* 92: USIC1 Channel, SR2 */
#define XMC4_IRQ_USIC1_SR3 (XMC4_IRQ_FIRST + 93) /* 93: USIC1 Channel, SR3 */
#define XMC4_IRQ_USIC1_SR4 (XMC4_IRQ_FIRST + 94) /* 94: USIC1 Channel, SR4 */
#define XMC4_IRQ_USIC1_SR5 (XMC4_IRQ_FIRST + 95) /* 95: USIC1 Channel, SR5 */
#define XMC4_IRQ_USIC2_SR0 (XMC4_IRQ_FIRST + 96) /* 96: USIC2 Channel, SR0 */
#define XMC4_IRQ_USIC2_SR1 (XMC4_IRQ_FIRST + 97) /* 97: USIC2 Channel, SR1 */
#define XMC4_IRQ_USIC2_SR2 (XMC4_IRQ_FIRST + 98) /* 98: USIC2 Channel, SR2 */
#define XMC4_IRQ_USIC2_SR3 (XMC4_IRQ_FIRST + 99) /* 99: USIC2 Channel, SR3 */
#define XMC4_IRQ_USIC2_SR4 (XMC4_IRQ_FIRST + 100) /* 100: USIC2 Channel, SR4 */
#define XMC4_IRQ_USIC2_SR5 (XMC4_IRQ_FIRST + 101) /* 101: USIC2 Channel, SR5 */
#define XMC4_IRQ_LEDTS0_SR0 (XMC4_IRQ_FIRST + 102) /* 102: LEDTS0, SR0 */
#define XMC4_IRQ_RESVD103 (XMC4_IRQ_FIRST + 103) /* 103: Reserved */
#define XMC4_IRQ_FCR_SR0 (XMC4_IRQ_FIRST + 104) /* 102: FCE, SR0 */
#define XMC4_IRQ_GPCMA0_SR0 (XMC4_IRQ_FIRST + 105) /* 105: GPDMA0, SR0 */
#define XMC4_IRQ_SDMMC_SR0 (XMC4_IRQ_FIRST + 106) /* 106: SDMMC, SR0 */
#define XMC4_IRQ_USB0_SR0 (XMC4_IRQ_FIRST + 107) /* 107: USB, SR0 */
#define XMC4_IRQ_ETH0_SR0 (XMC4_IRQ_FIRST + 108) /* 108: Ethernet, module 0, SR0 */
#define XMC4_IRQ_ECAT0_SR0 (XMC4_IRQ_FIRST + 109) /* 109: EtherCAT, module 0, SR0 */
#define XMC4_IRQ_GPCMA1_SR0 (XMC4_IRQ_FIRST + 110) /* 110: GPDMA1, SR0 */
#define XMC4_IRQ_RESVD111 (XMC4_IRQ_FIRST + 111) /* 111: Reserved */
#define NR_INTERRUPTS 112 /* 112 Non core IRQs*/
#define NR_VECTORS (XMC4_IRQ_FIRST+NR_INTERRUPTS) /* 128 vectors */
#define XMC4_IRQ_NEXTINTS 112 /* 112 Non core IRQs*/
#define XMC4_IRQ_NVECTORS (XMC4_IRQ_FIRST + XMC4_IRQ_NEXTINTS) /* 128 vectors */
/* GPIO IRQ interrupts -- To be provided */
#define NR_IRQS NR_VECTORS
#define NR_IRQS XM4C_IRQ_NVECTORS
/*****************************************************************************
* Public Types

16
arch/arm/src/efm32/efm32_irq.c
View File

@ -130,15 +130,15 @@ static void efm32_dumpnvic(const char *msg, int irq)
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 32)
#if EFM32_IRQ_NVECTORS >= (EFM32_IRQ_INTERRUPTS + 32)
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 48)
#if EFM32_IRQ_NVECTORS >= (EFM32_IRQ_INTERRUPTS + 48)
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 64)
#if EFM32_IRQ_NVECTORS >= (EFM32_IRQ_INTERRUPTS + 64)
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
#endif
@ -255,7 +255,7 @@ static int efm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
if (irq >= EFM32_IRQ_INTERRUPTS)
{
if (irq < NR_VECTORS)
if (irq < EFM32_IRQ_NVECTORS)
{
n = irq - EFM32_IRQ_INTERRUPTS;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
@ -314,7 +314,7 @@ void up_irqinitialize(void)
/* Disable all interrupts */
for (i = 0; i < NR_VECTORS - EFM32_IRQ_INTERRUPTS; i += 32)
for (i = 0; i < EFM32_IRQ_NVECTORS - EFM32_IRQ_INTERRUPTS; i += 32)
{
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
@ -404,7 +404,7 @@ void up_irqinitialize(void)
irq_attach(EFM32_IRQ_RESERVED, efm32_reserved, NULL);
#endif
efm32_dumpnvic("initial", NR_VECTORS);
efm32_dumpnvic("initial", EFM32_IRQ_NVECTORS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
#ifdef CONFIG_EFM32_GPIO_IRQ
@ -541,7 +541,7 @@ int up_prioritize_irq(int irq, int priority)
uint32_t regval;
int shift;
DEBUGASSERT(irq >= EFM32_IRQ_MEMFAULT && irq < NR_VECTORS &&
DEBUGASSERT(irq >= EFM32_IRQ_MEMFAULT && irq < EFM32_IRQ_NVECTORS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < EFM32_IRQ_INTERRUPTS)
@ -553,7 +553,7 @@ int up_prioritize_irq(int irq, int priority)
regaddr = NVIC_SYSH_PRIORITY(irq);
irq -= 4;
}
else (irq < NR_VECTORS)
else (irq < EFM32_IRQ_NVECTORS)
{
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */

5
arch/arm/src/imxrt/imxrt_enet.c
View File

@ -90,6 +90,11 @@
/* Select work queue. Always use the LP work queue if available. If not,
* then LPWORK will re-direct to the HP work queue.
*
* NOTE: However, the network should NEVER run on the high priority work
* queue! That queue is intended only to service short back end interrupt
* processing that never suspends. Suspending the high priority work queue
* may bring the system to its knees!
*/
# define ETHWORK LPWORK

2
arch/arm/src/kinetis/chip.h
View File

@ -60,6 +60,6 @@
* header file.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS
#define ARMV7M_PERIPHERAL_INTERRUPTS KINETIS_IRQ_NEXTINTS
#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_H */

2
arch/arm/src/kinetis/kinetis_irq.c
View File

@ -147,7 +147,7 @@ static void kinetis_dumpnvic(const char *msg, int irq)
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
#if NR_VECTORS > 111
#if KINETIS_IRQ_NVECTORS > 111
irqinfo(" %08x %08x\n",
getreg32(NVIC_IRQ112_115_PRIORITY), getreg32(NVIC_IRQ116_119_PRIORITY));
#endif

2
arch/arm/src/stm32f7/chip.h
View File

@ -57,7 +57,7 @@
* header file.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
/* Cache line sizes (in bytes)for the STM32F7 */

30
arch/arm/src/stm32f7/stm32_irq.c
View File

@ -134,37 +134,37 @@ static void stm32_dumpnvic(const char *msg, int irq)
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
#if NR_INTERRUPTS > 15
#if STM32_IRQ_NEXTINTS > 15
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#endif
#if NR_INTERRUPTS > 31
#if STM32_IRQ_NEXTINTS > 31
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#endif
#if NR_INTERRUPTS > 47
#if STM32_IRQ_NEXTINTS > 47
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#endif
#if NR_INTERRUPTS > 63
#if STM32_IRQ_NEXTINTS > 63
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
#endif
#if NR_INTERRUPTS > 79
#if STM32_IRQ_NEXTINTS > 79
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY));
#endif
#if NR_INTERRUPTS > 95
#if STM32_IRQ_NEXTINTS > 95
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
#endif
#if NR_INTERRUPTS > 111
#if STM32_IRQ_NEXTINTS > 111
# warning Missing logic
#endif
@ -278,26 +278,26 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
if (irq >= STM32_IRQ_FIRST)
{
#if NR_INTERRUPTS <= 32
if (extint < NR_INTERRUPTS)
#if STM32_IRQ_NEXTINTS <= 32
if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else
#elif NR_INTERRUPTS <= 64
#elif STM32_IRQ_NEXTINTS <= 64
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else if (extint < NR_INTERRUPTS)
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else
#elif NR_INTERRUPTS <= 96
#elif STM32_IRQ_NEXTINTS <= 96
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
@ -308,13 +308,13 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else if (extint < NR_INTERRUPTS)
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else
#elif NR_INTERRUPTS <= 128
#elif STM32_IRQ_NEXTINTS <= 128
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
@ -330,7 +330,7 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else if (extint < NR_INTERRUPTS)
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ96_127_ENABLE + offset);
*bit = 1 << (extint - 96);

2
arch/arm/src/stm32h7/chip.h
View File

@ -55,7 +55,7 @@
* header file.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
/* Cache line sizes (in bytes)for the STM32H7 */

30
arch/arm/src/stm32h7/stm32_irq.c
View File

@ -130,37 +130,37 @@ static void stm32_dumpnvic(const char *msg, int irq)
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
#if NR_INTERRUPTS > 15
#if STM32_IRQ_NEXTINTS > 15
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#endif
#if NR_INTERRUPTS > 31
#if STM32_IRQ_NEXTINTS > 31
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#endif
#if NR_INTERRUPTS > 47
#if STM32_IRQ_NEXTINTS > 47
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#endif
#if NR_INTERRUPTS > 63
#if STM32_IRQ_NEXTINTS > 63
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
#endif
#if NR_INTERRUPTS > 79
#if STM32_IRQ_NEXTINTS > 79
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY));
#endif
#if NR_INTERRUPTS > 95
#if STM32_IRQ_NEXTINTS > 95
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
#endif
#if NR_INTERRUPTS > 111
#if STM32_IRQ_NEXTINTS > 111
# warning Missing logic
#endif
@ -276,26 +276,26 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
if (irq >= STM32_IRQ_FIRST)
{
#if NR_INTERRUPTS <= 32
if (extint < NR_INTERRUPTS)
#if STM32_IRQ_NEXTINTS <= 32
if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else
#elif NR_INTERRUPTS <= 64
#elif STM32_IRQ_NEXTINTS <= 64
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else if (extint < NR_INTERRUPTS)
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else
#elif NR_INTERRUPTS <= 96
#elif STM32_IRQ_NEXTINTS <= 96
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
@ -306,13 +306,13 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else if (extint < NR_INTERRUPTS)
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else
#elif NR_INTERRUPTS <= 128
#elif STM32_IRQ_NEXTINTS <= 128
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
@ -328,7 +328,7 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else if (extint < NR_INTERRUPTS)
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ96_127_ENABLE + offset);
*bit = 1 << (extint - 96);

2
arch/arm/src/stm32l4/chip.h
View File

@ -61,7 +61,7 @@
* header file.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32L4_IRQ_NEXTINTS
/* Cache line sizes (in bytes) for the STM32L4 */

2
arch/arm/src/stm32l4/stm32l4_dac.c
View File

@ -225,7 +225,7 @@
# define DAC1_TIMER_BASE STM32L4_TIM4_BASE
# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY
# else
# error "Unsupported CONFIG_STM32_DAC1_TIMER"
# error "Unsupported CONFIG_STM32L4_DAC1_TIMER"
# endif
#else
# define DAC1_TSEL_VALUE DAC_CR_TSEL_SW

2
arch/arm/src/stm32l4/stm32l4_iwdg.c
View File

@ -165,7 +165,7 @@ static struct stm32l4_lowerhalf_s g_wdgdev;
*
****************************************************************************/
#ifdef CONFIG_STM32_IWDG_REGDEBUG
#ifdef CONFIG_STM32L4_IWDG_REGDEBUG
static uint16_t stm32l4_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;

2
arch/arm/src/xmc4/chip.h
View File

@ -56,7 +56,7 @@
* header file.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS
#define ARMV7M_PERIPHERAL_INTERRUPTS XMC4_IRQ_NEXTINTS
/************************************************************************************
* Pre-processor Definitions

2
arch/arm/src/xmc4/xmc4_irq.c
View File

@ -147,7 +147,7 @@ static void xmc4_dump_nvic(const char *msg, int irq)
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
#if NR_VECTORS > 111
#if XMC4_IRQ_NVECTORS > 111
irqinfo(" %08x %08x\n",
getreg32(NVIC_IRQ112_115_PRIORITY), getreg32(NVIC_IRQ116_119_PRIORITY));
#endif

5
drivers/net/skeleton.c
View File

@ -74,6 +74,11 @@
/* The low priority work queue is preferred. If it is not enabled, LPWORK
* will be the same as HPWORK.
*
* NOTE: However, the network should NEVER run on the high priority work
* queue! That queue is intended only to service short back end interrupt
* processing that never suspends. Suspending the high priority work queue
* may bring the system to its knees!
*/
#define ETHWORK LPWORK