sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

arch/: Clean up some naming and spacing.

Browse Source
This commit is contained in:
Gregory Nutt 2018-06-20 15:38:06 -06:00
parent 49ec86ddb1
commit cb374e6e62
54 changed files with 1519 additions and 1541 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm/include/bcm2708/irq.h
View File

@ -186,24 +186,24 @@
#define IPR2_IRQ_LAST BCM_IRQ_AVSPMON /* IRQ of last defined bit */
#define IPR2_BIT_LAST (31) /* Last defined bit */
/* Number of interrupts */
/* Number of hardware interrupt vectors */
#define NR_INTERRUPTS (IPR2_IRQ_LAST + 1)
#define BCM_IRQ_NVECTORS (IPR2_IRQ_LAST + 1)
/* Second level GPIO interrupts */
#ifdef CONFIG_BCM2708_GPIO_IRQ
# define BCM_IRQ_GPIO(n) (NR_INTERRUPTS + (n)) /* IRQ number of pin n */
# define BCM_IRQ_GPIO0_FIRST (NR_INTERRUPTS) /* IRQ number of first GPIO0 interrupt */
# define BCM_IRQ_GPIO1_FIRST (NR_INTERRUPTS + 32) /* IRQ number of first GPIO1 interrupt */
# define NR_GPIOINTS (54)
# define BCM_IRQ_GPIO(n) (BCM_IRQ_NVECTORS + (n)) /* IRQ number of pin n */
# define BCM_IRQ_GPIO0_FIRST (BCM_IRQ_NVECTORS) /* IRQ number of first GPIO0 interrupt */
# define BCM_IRQ_GPIO1_FIRST (BCM_IRQ_NVECTORS + 32) /* IRQ number of first GPIO1 interrupt */
# define BCM_IRQ_NGPIOINTS (54)
#else
# define NR_GPIOINTS (0)
# define BCM_IRQ_NGPIOINTS (0)
#endif
/* Number of supported IRQs */
#define NR_IRQS (NR_INTERRUPTS + NR_GPIOINTS)
#define NR_IRQS (BCM_IRQ_NVECTORS + BCM_IRQ_NGPIOINTS)
#else
# error Unrecognized BCM2708 chip

2
arch/arm/include/efm32/efm32g_irq.h
View File

@ -90,7 +90,7 @@
#define EFM32_IRQ_AES (EFM32_IRQ_INTERRUPTS + 29) /* 29 AES */
#define EFM32_PERIPH_INTS (30)
#define NR_VECTORS (EFM32_IRQ_INTERRUPTS + EFM32_PERIPH_INTS)
#define EFM32_IRQ_NVECTORS (EFM32_IRQ_INTERRUPTS + EFM32_PERIPH_INTS)
/****************************************************************************
* Public Types

2
arch/arm/include/efm32/efm32gg_irq.h
View File

@ -99,7 +99,7 @@
#define EFM32_IRQ_EMI (EFM32_IRQ_INTERRUPTS + 38)
#define EFM32_PERIPH_INTS (39)
#define NR_VECTORS (EFM32_IRQ_INTERRUPTS + EFM32_PERIPH_INTS)
#define EFM32_IRQ_NVECTORS (EFM32_IRQ_INTERRUPTS + EFM32_PERIPH_INTS)
/****************************************************************************
* Public Types

2
arch/arm/include/efm32/efm32tg_irq.h
View File

@ -83,7 +83,7 @@
#define EFM32_IRQ_AES (EFM32_IRQ_INTERRUPTS + 22)
#define EFM32_PERIPH_INTS (23)
#define NR_VECTORS (EFM32_IRQ_INTERRUPTS + EFM32_PERIPH_INTS)
#define EFM32_IRQ_NVECTORS (EFM32_IRQ_INTERRUPTS + EFM32_PERIPH_INTS)
/****************************************************************************
* Public Types

36
arch/arm/include/efm32/irq.h
View File

@ -95,26 +95,26 @@
* 16-additional interrupts generated from a second level of decoding.
*/
# define EFM32_IRQ_EXTI0 (NR_VECTORS + 0) /* Port[n], pin0 external interrupt */
# define EFM32_IRQ_EXTI1 (NR_VECTORS + 1) /* Port[n], pin1 external interrupt */
# define EFM32_IRQ_EXTI2 (NR_VECTORS + 2) /* Port[n], pin2 external interrupt */
# define EFM32_IRQ_EXTI3 (NR_VECTORS + 3) /* Port[n], pin3 external interrupt */
# define EFM32_IRQ_EXTI4 (NR_VECTORS + 4) /* Port[n], pin4 external interrupt */
# define EFM32_IRQ_EXTI5 (NR_VECTORS + 5) /* Port[n], pin5 external interrupt */
# define EFM32_IRQ_EXTI6 (NR_VECTORS + 6) /* Port[n], pin6 external interrupt */
# define EFM32_IRQ_EXTI7 (NR_VECTORS + 7) /* Port[n], pin7 external interrupt */
# define EFM32_IRQ_EXTI8 (NR_VECTORS + 8) /* Port[n], pin8 external interrupt */
# define EFM32_IRQ_EXTI9 (NR_VECTORS + 9) /* Port[n], pin9 external interrupt */
# define EFM32_IRQ_EXTI10 (NR_VECTORS + 10) /* Port[n], pin10 external interrupt */
# define EFM32_IRQ_EXTI11 (NR_VECTORS + 11) /* Port[n], pin11 external interrupt */
# define EFM32_IRQ_EXTI12 (NR_VECTORS + 12) /* Port[n], pin12 external interrupt */
# define EFM32_IRQ_EXTI13 (NR_VECTORS + 13) /* Port[n], pin13 external interrupt */
# define EFM32_IRQ_EXTI14 (NR_VECTORS + 14) /* Port[n], pin14 external interrupt */
# define EFM32_IRQ_EXTI15 (NR_VECTORS + 15) /* Port[n], pin15 external interrupt */
# define EFM32_IRQ_EXTI0 (EFM32_IRQ_NVECTORS + 0) /* Port[n], pin0 external interrupt */
# define EFM32_IRQ_EXTI1 (EFM32_IRQ_NVECTORS + 1) /* Port[n], pin1 external interrupt */
# define EFM32_IRQ_EXTI2 (EFM32_IRQ_NVECTORS + 2) /* Port[n], pin2 external interrupt */
# define EFM32_IRQ_EXTI3 (EFM32_IRQ_NVECTORS + 3) /* Port[n], pin3 external interrupt */
# define EFM32_IRQ_EXTI4 (EFM32_IRQ_NVECTORS + 4) /* Port[n], pin4 external interrupt */
# define EFM32_IRQ_EXTI5 (EFM32_IRQ_NVECTORS + 5) /* Port[n], pin5 external interrupt */
# define EFM32_IRQ_EXTI6 (EFM32_IRQ_NVECTORS + 6) /* Port[n], pin6 external interrupt */
# define EFM32_IRQ_EXTI7 (EFM32_IRQ_NVECTORS + 7) /* Port[n], pin7 external interrupt */
# define EFM32_IRQ_EXTI8 (EFM32_IRQ_NVECTORS + 8) /* Port[n], pin8 external interrupt */
# define EFM32_IRQ_EXTI9 (EFM32_IRQ_NVECTORS + 9) /* Port[n], pin9 external interrupt */
# define EFM32_IRQ_EXTI10 (EFM32_IRQ_NVECTORS + 10) /* Port[n], pin10 external interrupt */
# define EFM32_IRQ_EXTI11 (EFM32_IRQ_NVECTORS + 11) /* Port[n], pin11 external interrupt */
# define EFM32_IRQ_EXTI12 (EFM32_IRQ_NVECTORS + 12) /* Port[n], pin12 external interrupt */
# define EFM32_IRQ_EXTI13 (EFM32_IRQ_NVECTORS + 13) /* Port[n], pin13 external interrupt */
# define EFM32_IRQ_EXTI14 (EFM32_IRQ_NVECTORS + 14) /* Port[n], pin14 external interrupt */
# define EFM32_IRQ_EXTI15 (EFM32_IRQ_NVECTORS + 15) /* Port[n], pin15 external interrupt */
# define NR_IRQS (NR_VECTORS + 16) /* Total number of interrupts */
# define NR_IRQS (EFM32_IRQ_NVECTORS + 16) /* Total number of interrupts */
#else
# define NR_IRQS NR_VECTORS /* Total number of interrupts */
# define NR_IRQS EFM32_IRQ_NVECTORS /* Total number of interrupts */
#endif
/************************************************************************************

1
arch/arm/include/imxrt/imxrt105x_irq.h
View File

@ -482,7 +482,6 @@
/* Total number of IRQ numbers **********************************************************/
#define NR_VECTORS IMXRT_IRQ_NIRQS
#define NR_IRQS (IMXRT_IRQ_EXTINT + IMXRT_IRQ_NEXTINT + IMXRT_GPIO_NIRQS)
/****************************************************************************************

32
arch/arm/include/kinetis/kinetis_k20irq.h
View File

@ -1,4 +1,4 @@
/*****************************************************************************
/**************************************************************************************
* arch/arm/include/kinetis/kinetis_k20irq.h
*
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
@ -32,7 +32,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
*************************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
@ -41,15 +41,15 @@
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_K20IRQ_H
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_K20IRQ_H
/*****************************************************************************
/**************************************************************************************
* Included Files
****************************************************************************/
*************************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
/**************************************************************************************
* Pre-processor Definitions
****************************************************************************/
*************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
@ -60,7 +60,7 @@
*
* External interrupts (vectors >= 16)
*
* K20 Family ****************************************************************
* K20 Family *************************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale
* document K20P64M72SF1RM
@ -163,20 +163,20 @@
#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST + 93) /* 93: Reserved */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST + 94) /* 94: Software interrupt */
#define NR_INTERRUPTS 95 /* 95 Non core IRQs*/
#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 111 vectors */
#define KINETIS_IRQ_NEXTINTS 95 /* 95 Non core IRQs */
#define KINETIS_IRQ_NVECTORS (KINETIS_IRQ_FIRST + KINETIS_IRQ_NEXTINTS) /* 111 vectors */
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS KINETIS_IRQ_NVECTORS
/*****************************************************************************
/**************************************************************************************
* Public Types
****************************************************************************/
*************************************************************************************/
/*****************************************************************************
/**************************************************************************************
* Public Data
****************************************************************************/
*************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@ -187,9 +187,9 @@ extern "C"
#define EXTERN extern
#endif
/*****************************************************************************
/**************************************************************************************
* Public Functions
****************************************************************************/
*************************************************************************************/
#undef EXTERN
#ifdef __cplusplus

6
arch/arm/include/kinetis/kinetis_k28irq.h
View File

@ -185,12 +185,12 @@
#define KINETIS_IRQ_RESVD105 (KINETIS_IRQ_FIRST + 105) /* 105: Reserved */
#define KINETIS_IRQ_RESVD106 (KINETIS_IRQ_FIRST + 106) /* 106: Reserved */
#define NR_INTERRUPTS 107 /* 107 Non core IRQs*/
#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 123 vectors */
#define KINETIS_IRQ_NEXTINTS 107 /* 107 Non core IRQs */
#define KINETIS_IRQ_NVECTORS (KINETIS_IRQ_FIRST + KINETIS_IRQ_NEXTINTS) /* 123 vectors */
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS KINETIS_IRQ_NVECTORS
/*********************************************************************************************
* Public Types

32
arch/arm/include/kinetis/kinetis_k40irq.h
View File

@ -1,4 +1,4 @@
/*****************************************************************************
/*************************************************************************************
* arch/arm/include/kinetis/kinetis_k40irq.h
*
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
@ -32,7 +32,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
************************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
@ -41,15 +41,15 @@
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_40KIRQ_H
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_40KIRQ_H
/*****************************************************************************
/*************************************************************************************
* Included Files
****************************************************************************/
************************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
/*************************************************************************************
* Pre-processor Definitions
****************************************************************************/
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
@ -60,7 +60,7 @@
*
* External interrupts (vectors >= 16)
*
* K40 Family ****************************************************************
* K40 Family ************************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale
* document K40P144M100SF2RM
@ -163,20 +163,20 @@
#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST + 93) /* 93: Reserved */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST + 94) /* 94: Software interrupt */
#define NR_INTERRUPTS 95 /* 95 Non core IRQs*/
#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 111 vectors */
#define KINETIS_IRQ_NEXTINTS 95 /* 95 Non core IRQs */
#define KINETIS_IRQ_NVECTORS (KINETIS_IRQ_FIRST + KINETIS_IRQ_NEXTINTS) /* 111 vectors */
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS KINETIS_IRQ_NVECTORS
/*****************************************************************************
/*************************************************************************************
* Public Types
****************************************************************************/
************************************************************************************/
/*****************************************************************************
/*************************************************************************************
* Public Data
****************************************************************************/
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@ -187,9 +187,9 @@ extern "C"
#define EXTERN extern
#endif
/*****************************************************************************
/*************************************************************************************
* Public Functions
****************************************************************************/
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus

32
arch/arm/include/kinetis/kinetis_k60irq.h
View File

@ -1,4 +1,4 @@
/*****************************************************************************
/************************************************************************************
* arch/arm/include/kinetis/kinetis_k60irq.h
*
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
@ -32,7 +32,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
************************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
@ -41,15 +41,15 @@
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_60KIRQ_H
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_60KIRQ_H
/*****************************************************************************
/************************************************************************************
* Included Files
****************************************************************************/
************************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
/************************************************************************************
* Pre-processor Definitions
****************************************************************************/
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
@ -60,7 +60,7 @@
*
* External interrupts (vectors >= 16)
*
* K60 Family ****************************************************************
* K60 Family ************************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale
* document K60P144M100SF2RM
@ -163,20 +163,20 @@
#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST + 93) /* 93: Reserved */
#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST + 94) /* 94: Software interrupt */
#define NR_INTERRUPTS 95 /* 95 Non core IRQs*/
#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 111 vectors */
#define KINETIS_IRQ_NEXTINTS 95 /* 95 Non core IRQs */
#define KINETIS_IRQ_NVECTORS (KINETIS_IRQ_FIRST + KINETIS_IRQ_NEXTINTS) /* 111 vectors */
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS KINETIS_IRQ_NVECTORS
/*****************************************************************************
/************************************************************************************
* Public Types
****************************************************************************/
************************************************************************************/
/*****************************************************************************
/************************************************************************************
* Public Data
****************************************************************************/
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@ -187,9 +187,9 @@ extern "C"
#define EXTERN extern
#endif
/*****************************************************************************
/************************************************************************************
* Public Functions
****************************************************************************/
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus

32
arch/arm/include/kinetis/kinetis_k64irq.h
View File

@ -1,4 +1,4 @@
/*****************************************************************************
/************************************************************************************
* arch/arm/include/kinetis/kinetis_k64irq.h
*
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
@ -32,7 +32,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
************************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
@ -41,15 +41,15 @@
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_64KIRQ_H
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_64KIRQ_H
/*****************************************************************************
/************************************************************************************
* Included Files
****************************************************************************/
************************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
/************************************************************************************
* Pre-processor Definitions
****************************************************************************/
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
@ -60,7 +60,7 @@
*
* External interrupts (vectors >= 16)
*
* K60 Family ****************************************************************
* K60 Family ************************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale
* document K64P144M120SF5RM.pdf
@ -153,20 +153,20 @@
#define KINETIS_IRQ_EMACRX (KINETIS_IRQ_FIRST + 84) /* 84: Ethernet MAC receive interrupt */
#define KINETIS_IRQ_EMACMISC (KINETIS_IRQ_FIRST + 85) /* 85: Ethernet MAC error and misc interrupt */
#define NR_INTERRUPTS 86 /* 86 Non core IRQs*/
#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 102 vectors */
#define KINETIS_IRQ_NEXTINTS 86 /* 86 Non core IRQs */
#define KINETIS_IRQ_NVECTORS (KINETIS_IRQ_FIRST + KINETIS_IRQ_NEXTINTS) /* 102 vectors */
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS KINETIS_IRQ_NVECTORS
/*****************************************************************************
/************************************************************************************
* Public Types
****************************************************************************/
************************************************************************************/
/*****************************************************************************
/************************************************************************************
* Public Data
****************************************************************************/
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@ -177,9 +177,9 @@ extern "C"
#define EXTERN extern
#endif
/*****************************************************************************
/************************************************************************************
* Public Functions
****************************************************************************/
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus

32
arch/arm/include/kinetis/kinetis_k66irq.h
View File

@ -1,4 +1,4 @@
/*****************************************************************************
/************************************************************************************
* arch/arm/include/kinetis/kinetis_k66irq.h
*
* Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
@ -32,7 +32,7 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
************************************************************************************/
/* This file should never be included directed but, rather, only indirectly
* through nuttx/irq.h
@ -41,15 +41,15 @@
#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_K66IRQ_H
#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_K66IRQ_H
/*****************************************************************************
/************************************************************************************
* Included Files
****************************************************************************/
************************************************************************************/
#include <nuttx/config.h>
/*****************************************************************************
/************************************************************************************
* Pre-processor Definitions
****************************************************************************/
************************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words of
@ -60,7 +60,7 @@
*
* External interrupts (vectors >= 16)
*
* K66 Family ****************************************************************
* K66 Family ************************************************************************
*
* The interrupt vectors for the following parts is defined in Freescale
* document K66P144M180SF5RMV2
@ -169,20 +169,20 @@
#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST + 99) /* 99: CAN1 Wake UP */
#define NR_INTERRUPTS 100 /* 100 Non core IRQs*/
#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 116 vectors */
#define KINETIS_IRQ_NEXTINTS 100 /* 100 Non core IRQs*/
#define KINETIS_IRQ_NVECTORS (KINETIS_IRQ_FIRST + KINETIS_IRQ_NEXTINTS) /* 116 vectors */
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS KINETIS_IRQ_NVECTORS
/*****************************************************************************
/************************************************************************************
* Public Types
****************************************************************************/
************************************************************************************/
/*****************************************************************************
/************************************************************************************
* Public Data
****************************************************************************/
************************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
@ -193,9 +193,9 @@ extern "C"
#define EXTERN extern
#endif
/*****************************************************************************
/************************************************************************************
* Public Functions
****************************************************************************/
************************************************************************************/
#undef EXTERN
#ifdef __cplusplus

2
arch/arm/include/kl/irq.h
View File

@ -122,7 +122,6 @@
* now) seems to justify the waste.
*/
# define NR_VECTORS (64) /* 64 vectors */
# define NR_IRQS (48) /* 64 interrupts but 48 IRQ numbers */
#elif defined(CONFIG_ARCH_CHIP_MKL26Z128)
@ -168,7 +167,6 @@
* now) seems to justify the waste.
*/
# define NR_VECTORS (64) /* 64 vectors */
# define NR_IRQS (48) /* 64 interrupts but 48 IRQ numbers */
#else

1
arch/arm/include/lc823450/irq.h
View File

@ -258,7 +258,6 @@
#define LC823450_IRQ_NVIRTUALIRQS (0)
#endif /* CONFIG_LC823450_VIRQ */
#define NR_VECTORS (LC823450_IRQ_NIRQS)
#define NR_IRQS (LC823450_IRQ_NIRQS + LC823450_IRQ_NGPIOIRQS + \
LC823450_IRQ_NVIRTUALIRQS)

1
arch/arm/include/lpc11xx/irq.h
View File

@ -109,7 +109,6 @@
#define LPC11_IRQ_PIO0 (47) /* Vector 47: PIO0 */
#endif
#define NR_VECTORS (48) /* 48 vectors */
#define NR_IRQS (48) /* 32 interrupts plus 16 exceptions */
/****************************************************************************

1
arch/arm/include/lpc17xx/lpc176x_irq.h
View File

@ -223,7 +223,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS LPC17_IRQ_NIRQS
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
/****************************************************************************

1
arch/arm/include/lpc17xx/lpc178x_irq.h
View File

@ -269,7 +269,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS LPC17_IRQ_NIRQS
#define NR_IRQS (LPC17_IRQ_EXTINT+LPC17_IRQ_NEXTINT+LPC17_NGPIOAIRQS)
/****************************************************************************

2
arch/arm/include/lpc43xx/irq.h
View File

@ -133,7 +133,6 @@
* supported)
*/
#define NR_VECTORS LPC43M4_IRQ_NIRQS
#define NR_IRQS LPC43M4_IRQ_NIRQS
/* Cortex-M0 External interrupts (vectors >= 16) */
@ -184,7 +183,6 @@
*/
#if 0
#define NR_VECTORS LPC43M0_IRQ_NIRQS
#define NR_IRQS LPC43M0_IRQ_NIRQS
#endif

1
arch/arm/include/lpc54xx/lpc546x_irq.h
View File

@ -109,7 +109,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS LPC54_IRQ_NIRQS
#define NR_IRQS LPC54_IRQ_NIRQS
#endif /* __ARCH_ARM_INCLUDE_LPC54XX_LPC543X_IRQ_H */

1
arch/arm/include/nrf52/nrf52832_irq.h
View File

@ -91,7 +91,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS NRF52_IRQ_NIRQS
#define NR_IRQS NRF52_IRQ_NIRQS
#endif /* __ARCH_ARM_INCLUDE_NRF52_NRF52_IRQ_H */

1
arch/arm/include/sam34/sam3u_irq.h
View File

@ -238,7 +238,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)

1
arch/arm/include/sam34/sam3x_irq.h
View File

@ -392,7 +392,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \
SAM_NGPIODIRQS + SAM_NGPIOEIRQS + SAM_NGPIOFIRQS)

1
arch/arm/include/sam34/sam4cm_irq.h
View File

@ -267,7 +267,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)

1
arch/arm/include/sam34/sam4e_irq.h
View File

@ -300,7 +300,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \
SAM_NGPIODIRQS + SAM_NGPIOEIRQS)

1
arch/arm/include/sam34/sam4l_irq.h
View File

@ -299,7 +299,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)

1
arch/arm/include/sam34/sam4s_irq.h
View File

@ -249,7 +249,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS)

1
arch/arm/include/samdl/samd20_irq.h
View File

@ -105,7 +105,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_INTERRUPT + SAM_IRQ_NINTS + SAM_IRQ_NEXTINTS)
/****************************************************************************************

1
arch/arm/include/samdl/samd21_irq.h
View File

@ -112,7 +112,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_INTERRUPT + SAM_IRQ_NINTS + SAM_IRQ_NEXTINTS)
/****************************************************************************************

1
arch/arm/include/samdl/saml21_irq.h
View File

@ -113,7 +113,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_INTERRUPT + SAM_IRQ_NINTS + SAM_IRQ_NEXTINTS)
/****************************************************************************************

1
arch/arm/include/samv7/same70_irq.h
View File

@ -399,7 +399,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \
SAM_NGPIODIRQS + SAM_NGPIOEIRQS)

1
arch/arm/include/samv7/samv71_irq.h
View File

@ -399,7 +399,6 @@
/* Total number of IRQ numbers */
#define NR_VECTORS SAM_IRQ_NIRQS
#define NR_IRQS (SAM_IRQ_EXTINT + SAM_IRQ_NEXTINT + \
SAM_NGPIOAIRQS + SAM_NGPIOBIRQS + SAM_NGPIOCIRQS + \
SAM_NGPIODIRQS + SAM_NGPIOEIRQS)

1
arch/arm/include/stm32f0/irq.h
View File

@ -108,7 +108,6 @@
#define STM32F0_IRQ_CEC_CAN (46) /* Vector 46: HDMI CEC and CAN */
#define STM32F0_IRQ_USB (47) /* Vector 47: USB */
#define NR_VECTORS (48) /* 48 vectors */
#define NR_IRQS (48) /* 32 interrupts plus 16 exceptions */
/****************************************************************************

5
arch/arm/include/stm32f7/stm32f72xx73xx_irq.h
View File

@ -160,12 +160,11 @@
#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST + 103) /* 103: SDMMC2 global interrupt */
#define NR_INTERRUPTS 103
#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
#define STM32_IRQ_NEXTINTS 104
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************************************
* Public Types

5
arch/arm/include/stm32f7/stm32f74xx75xx_irq.h
View File

@ -165,12 +165,11 @@
#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST + 96) /* 96: I2C4 Error interrupt */
#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST + 97) /* 97: SPDIFRX global interrupt */
#define NR_INTERRUPTS 98
#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
#define STM32_IRQ_NEXTINTS 98
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************************************
* Public Types

5
arch/arm/include/stm32f7/stm32f76xx77xx_irq.h
View File

@ -178,12 +178,11 @@
#define STM32_IRQ_JPEG (STM32_IRQ_FIRST + 108) /* 108: JPEG global interrupt */
#define STM32_IRQ_MDIOS (STM32_IRQ_FIRST + 109) /* 109: MDIO slave global interrupt */
#define NR_INTERRUPTS 110
#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
#define STM32_IRQ_NEXTINTS 110
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************************************
* Public Types

5
arch/arm/include/stm32h7/stm32h7x3xx_irq.h
View File

@ -214,9 +214,8 @@
#define STM32_IRQ_RESERVED148 (STM32_IRQ_FIRST + 148) /* 148: Reserved */
#define STM32_IRQ_WKUP (STM32_IRQ_FIRST + 149) /* 149: WKUP1 to WKUP6 pins */
#define NR_INTERRUPTS 150
#define NR_VECTORS (STM32_IRQ_FIRST + NR_INTERRUPTS)
#define NR_IRQS NR_VECTORS
#define STM32_IRQ_NEXTINTS 150
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************************************
* Public Types

8
arch/arm/include/stm32l4/stm32l4x3xx_irq.h
View File

@ -144,16 +144,14 @@
#define STM32L4_IRQ_I2C4ER (STM32L4_IRQ_FIRST + 84) /* 84: I2C4 error interrupt */
#if defined(CONFIG_STM32L4_STM32L4X3)
# define NR_INTERRUPTS 85
# define STM32L4_IRQ_NEXTINTS 85
#else
# error "Unsupported STM32L4 chip"
#endif
#define NR_VECTORS (STM32L4_IRQ_FIRST+NR_INTERRUPTS)
/* (EXTI interrupts do not use IRQ numbers) */
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
/****************************************************************************************************
* Public Types

9
arch/arm/include/stm32l4/stm32l4x5xx_irq.h
View File

@ -143,17 +143,16 @@
#define STM32L4_IRQ_SAI2 (STM32L4_IRQ_FIRST + 75) /* 75: SAI2 global interrupt */
#define STM32L4_IRQ_SWPMI1 (STM32L4_IRQ_FIRST + 76) /* 76: SWPMI1 global interrupt */
#define STM32L4_IRQ_TSC (STM32L4_IRQ_FIRST + 77) /* 77: TSC global interrupt */
#define STM32_IRQ_RESERVED78 (STM32L4_IRQ_FIRST+78) /* 78: Reserved */
#define STM32_IRQ_RESERVED79 (STM32L4_IRQ_FIRST+79) /* 79: Reserved */
#define STM32L4_IRQ_RESERVED78 (STM32L4_IRQ_FIRST + 78) /* 78: Reserved */
#define STM32L4_IRQ_RESERVED79 (STM32L4_IRQ_FIRST + 79) /* 79: Reserved */
#define STM32L4_IRQ_RNG (STM32L4_IRQ_FIRST + 80) /* 80: RNG global interrupt */
#define STM32L4_IRQ_FPU (STM32L4_IRQ_FIRST + 81) /* 81: FPU global interrupt */
#define NR_INTERRUPTS 82
#define NR_VECTORS (STM32L4_IRQ_FIRST+NR_INTERRUPTS)
#define STM32L4_IRQ_NEXTINTS 82
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
/****************************************************************************************************
* Public Types

8
arch/arm/include/stm32l4/stm32l4x6xx_irq.h
View File

@ -159,18 +159,16 @@
#define STM32L4_IRQ_DMA2D (STM32L4_IRQ_FIRST + 90) /* 90: DMA2D global interrupt */
#if defined(CONFIG_STM32L4_STM32L476XX) || defined(CONFIG_STM32L4_STM32L486XX)
# define NR_INTERRUPTS 82
# define STM32L4_IRQ_NEXTINTS 82
#elif defined(CONFIG_STM32L4_STM32L496XX)
# define NR_INTERRUPTS 91
# define STM32L4_IRQ_NEXTINTS 91
#else
# error "Unsupported STM32L4 chip"
#endif
#define NR_VECTORS (STM32L4_IRQ_FIRST+NR_INTERRUPTS)
/* EXTI interrupts (Do not use IRQ numbers) */
#define NR_IRQS NR_VECTORS
#define NR_IRQS (STM32L4_IRQ_FIRST + STM32L4_IRQ_NEXTINTS)
/****************************************************************************************************
* Public Types

6
arch/arm/include/xmc4/xmc4500_irq.h
View File

@ -188,12 +188,12 @@
#define XMC4_IRQ_GPCMA1_SR0 (XMC4_IRQ_FIRST + 110) /* 110: GPDMA1, SR0 */
#define XMC4_IRQ_RESVD111 (XMC4_IRQ_FIRST + 111) /* 111: Reserved */
#define NR_INTERRUPTS 112 /* 112 Non core IRQs*/
#define NR_VECTORS (XMC4_IRQ_FIRST+NR_INTERRUPTS) /* 128 vectors */
#define XMC4_IRQ_NEXTINTS 112 /* 112 Non core IRQs*/
#define XMC4_IRQ_NVECTORS (XMC4_IRQ_FIRST + XMC4_IRQ_NEXTINTS) /* 128 vectors */
/* GPIO IRQ interrupts -- To be provided */
#define NR_IRQS NR_VECTORS
#define NR_IRQS XM4C_IRQ_NVECTORS
/*****************************************************************************
* Public Types

16
arch/arm/src/efm32/efm32_irq.c
View File

@ -130,15 +130,15 @@ static void efm32_dumpnvic(const char *msg, int irq)
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 32)
#if EFM32_IRQ_NVECTORS >= (EFM32_IRQ_INTERRUPTS + 32)
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 48)
#if EFM32_IRQ_NVECTORS >= (EFM32_IRQ_INTERRUPTS + 48)
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 64)
#if EFM32_IRQ_NVECTORS >= (EFM32_IRQ_INTERRUPTS + 64)
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
#endif
@ -255,7 +255,7 @@ static int efm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
if (irq >= EFM32_IRQ_INTERRUPTS)
{
if (irq < NR_VECTORS)
if (irq < EFM32_IRQ_NVECTORS)
{
n = irq - EFM32_IRQ_INTERRUPTS;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
@ -314,7 +314,7 @@ void up_irqinitialize(void)
/* Disable all interrupts */
for (i = 0; i < NR_VECTORS - EFM32_IRQ_INTERRUPTS; i += 32)
for (i = 0; i < EFM32_IRQ_NVECTORS - EFM32_IRQ_INTERRUPTS; i += 32)
{
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
@ -404,7 +404,7 @@ void up_irqinitialize(void)
irq_attach(EFM32_IRQ_RESERVED, efm32_reserved, NULL);
#endif
efm32_dumpnvic("initial", NR_VECTORS);
efm32_dumpnvic("initial", EFM32_IRQ_NVECTORS);
#ifndef CONFIG_SUPPRESS_INTERRUPTS
#ifdef CONFIG_EFM32_GPIO_IRQ
@ -541,7 +541,7 @@ int up_prioritize_irq(int irq, int priority)
uint32_t regval;
int shift;
DEBUGASSERT(irq >= EFM32_IRQ_MEMFAULT && irq < NR_VECTORS &&
DEBUGASSERT(irq >= EFM32_IRQ_MEMFAULT && irq < EFM32_IRQ_NVECTORS &&
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < EFM32_IRQ_INTERRUPTS)
@ -553,7 +553,7 @@ int up_prioritize_irq(int irq, int priority)
regaddr = NVIC_SYSH_PRIORITY(irq);
irq -= 4;
}
else (irq < NR_VECTORS)
else (irq < EFM32_IRQ_NVECTORS)
{
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */

5
arch/arm/src/imxrt/imxrt_enet.c
View File

@ -90,6 +90,11 @@
/* Select work queue. Always use the LP work queue if available. If not,
* then LPWORK will re-direct to the HP work queue.
*
* NOTE: However, the network should NEVER run on the high priority work
* queue! That queue is intended only to service short back end interrupt
* processing that never suspends. Suspending the high priority work queue
* may bring the system to its knees!
*/
# define ETHWORK LPWORK

2
arch/arm/src/kinetis/chip.h
View File

@ -60,6 +60,6 @@
* header file.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS
#define ARMV7M_PERIPHERAL_INTERRUPTS KINETIS_IRQ_NEXTINTS
#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_H */

2
arch/arm/src/kinetis/kinetis_irq.c
View File

@ -147,7 +147,7 @@ static void kinetis_dumpnvic(const char *msg, int irq)
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
#if NR_VECTORS > 111
#if KINETIS_IRQ_NVECTORS > 111
irqinfo(" %08x %08x\n",
getreg32(NVIC_IRQ112_115_PRIORITY), getreg32(NVIC_IRQ116_119_PRIORITY));
#endif

2
arch/arm/src/stm32f7/chip.h
View File

@ -57,7 +57,7 @@
* header file.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
/* Cache line sizes (in bytes)for the STM32F7 */

30
arch/arm/src/stm32f7/stm32_irq.c
View File

@ -134,37 +134,37 @@ static void stm32_dumpnvic(const char *msg, int irq)
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
#if NR_INTERRUPTS > 15
#if STM32_IRQ_NEXTINTS > 15
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#endif
#if NR_INTERRUPTS > 31
#if STM32_IRQ_NEXTINTS > 31
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#endif
#if NR_INTERRUPTS > 47
#if STM32_IRQ_NEXTINTS > 47
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#endif
#if NR_INTERRUPTS > 63
#if STM32_IRQ_NEXTINTS > 63
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
#endif
#if NR_INTERRUPTS > 79
#if STM32_IRQ_NEXTINTS > 79
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY));
#endif
#if NR_INTERRUPTS > 95
#if STM32_IRQ_NEXTINTS > 95
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
#endif
#if NR_INTERRUPTS > 111
#if STM32_IRQ_NEXTINTS > 111
# warning Missing logic
#endif
@ -278,26 +278,26 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
if (irq >= STM32_IRQ_FIRST)
{
#if NR_INTERRUPTS <= 32
if (extint < NR_INTERRUPTS)
#if STM32_IRQ_NEXTINTS <= 32
if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else
#elif NR_INTERRUPTS <= 64
#elif STM32_IRQ_NEXTINTS <= 64
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else if (extint < NR_INTERRUPTS)
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else
#elif NR_INTERRUPTS <= 96
#elif STM32_IRQ_NEXTINTS <= 96
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
@ -308,13 +308,13 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else if (extint < NR_INTERRUPTS)
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else
#elif NR_INTERRUPTS <= 128
#elif STM32_IRQ_NEXTINTS <= 128
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
@ -330,7 +330,7 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else if (extint < NR_INTERRUPTS)
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ96_127_ENABLE + offset);
*bit = 1 << (extint - 96);

2
arch/arm/src/stm32h7/chip.h
View File

@ -55,7 +55,7 @@
* header file.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
/* Cache line sizes (in bytes)for the STM32H7 */

30
arch/arm/src/stm32h7/stm32_irq.c
View File

@ -130,37 +130,37 @@ static void stm32_dumpnvic(const char *msg, int irq)
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
#if NR_INTERRUPTS > 15
#if STM32_IRQ_NEXTINTS > 15
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY), getreg32(NVIC_IRQ28_31_PRIORITY));
#endif
#if NR_INTERRUPTS > 31
#if STM32_IRQ_NEXTINTS > 31
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY), getreg32(NVIC_IRQ44_47_PRIORITY));
#endif
#if NR_INTERRUPTS > 47
#if STM32_IRQ_NEXTINTS > 47
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY), getreg32(NVIC_IRQ60_63_PRIORITY));
#endif
#if NR_INTERRUPTS > 63
#if STM32_IRQ_NEXTINTS > 63
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY), getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY), getreg32(NVIC_IRQ76_79_PRIORITY));
#endif
#if NR_INTERRUPTS > 79
#if STM32_IRQ_NEXTINTS > 79
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ80_83_PRIORITY), getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY), getreg32(NVIC_IRQ92_95_PRIORITY));
#endif
#if NR_INTERRUPTS > 95
#if STM32_IRQ_NEXTINTS > 95
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
#endif
#if NR_INTERRUPTS > 111
#if STM32_IRQ_NEXTINTS > 111
# warning Missing logic
#endif
@ -276,26 +276,26 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
if (irq >= STM32_IRQ_FIRST)
{
#if NR_INTERRUPTS <= 32
if (extint < NR_INTERRUPTS)
#if STM32_IRQ_NEXTINTS <= 32
if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else
#elif NR_INTERRUPTS <= 64
#elif STM32_IRQ_NEXTINTS <= 64
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else if (extint < NR_INTERRUPTS)
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else
#elif NR_INTERRUPTS <= 96
#elif STM32_IRQ_NEXTINTS <= 96
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
@ -306,13 +306,13 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else if (extint < NR_INTERRUPTS)
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else
#elif NR_INTERRUPTS <= 128
#elif STM32_IRQ_NEXTINTS <= 128
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
@ -328,7 +328,7 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else if (extint < NR_INTERRUPTS)
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ96_127_ENABLE + offset);
*bit = 1 << (extint - 96);

2
arch/arm/src/stm32l4/chip.h
View File

@ -61,7 +61,7 @@
* header file.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32L4_IRQ_NEXTINTS
/* Cache line sizes (in bytes) for the STM32L4 */

2
arch/arm/src/stm32l4/stm32l4_dac.c
View File

@ -225,7 +225,7 @@
# define DAC1_TIMER_BASE STM32L4_TIM4_BASE
# define DAC1_TIMER_PCLK_FREQUENCY STM32L4_PCLK1_FREQUENCY
# else
# error "Unsupported CONFIG_STM32_DAC1_TIMER"
# error "Unsupported CONFIG_STM32L4_DAC1_TIMER"
# endif
#else
# define DAC1_TSEL_VALUE DAC_CR_TSEL_SW

2
arch/arm/src/stm32l4/stm32l4_iwdg.c
View File

@ -165,7 +165,7 @@ static struct stm32l4_lowerhalf_s g_wdgdev;
*
****************************************************************************/
#ifdef CONFIG_STM32_IWDG_REGDEBUG
#ifdef CONFIG_STM32L4_IWDG_REGDEBUG
static uint16_t stm32l4_getreg(uint32_t addr)
{
static uint32_t prevaddr = 0;

2
arch/arm/src/xmc4/chip.h
View File

@ -56,7 +56,7 @@
* header file.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS NR_INTERRUPTS
#define ARMV7M_PERIPHERAL_INTERRUPTS XMC4_IRQ_NEXTINTS
/************************************************************************************
* Pre-processor Definitions

2
arch/arm/src/xmc4/xmc4_irq.c
View File

@ -147,7 +147,7 @@ static void xmc4_dump_nvic(const char *msg, int irq)
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY), getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY), getreg32(NVIC_IRQ108_111_PRIORITY));
#if NR_VECTORS > 111
#if XMC4_IRQ_NVECTORS > 111
irqinfo(" %08x %08x\n",
getreg32(NVIC_IRQ112_115_PRIORITY), getreg32(NVIC_IRQ116_119_PRIORITY));
#endif

5
drivers/net/skeleton.c
View File

@ -74,6 +74,11 @@
/* The low priority work queue is preferred. If it is not enabled, LPWORK
* will be the same as HPWORK.
*
* NOTE: However, the network should NEVER run on the high priority work
* queue! That queue is intended only to service short back end interrupt
* processing that never suspends. Suspending the high priority work queue
* may bring the system to its knees!
*/
#define ETHWORK LPWORK