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Update a few comments

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This commit is contained in:
Gregory Nutt 2015-12-10 06:32:27 -06:00
parent a0594ec60e
commit cb5c221ce7
2 changed files with 7 additions and 2 deletions
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5
arch/arm/src/sama5/sam_udphs.c
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@ -2395,8 +2395,9 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno)
* REVISIT: On the SAMV7, I found that you really need to * REVISIT: On the SAMV7, I found that you really need to
* wait for the TX completion interrupt before calling * wait for the TX completion interrupt before calling
* sam_req_write(). For the SAMV7, the logic here just * sam_req_write(). For the SAMV7, the logic here just
* enables that TX completion interrupt. The symptom of * enables that TX completion interrupt if BYCT > 0. The
* the problem was occassional missing zero-length packets. * symptom of the problem was occasional missing zero-length
* packets because sam_req_write() was called too soon.
*/ */
DEBUGASSERT(USB_ISEPIN(privep->ep.eplog)); DEBUGASSERT(USB_ISEPIN(privep->ep.eplog));

4
arch/arm/src/samv7/sam_usbdevhs.c
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@ -2524,6 +2524,10 @@ static void sam_dma_interrupt(struct sam_usbdev_s *priv, int epno)
/* All bytes have been sent to the host. We must call /* All bytes have been sent to the host. We must call
* sam_req_write() now in the IDLE state with the number of * sam_req_write() now in the IDLE state with the number of
* bytes transferred in 'inflight' * bytes transferred in 'inflight'
*
* REVISIT: Isn't there a race condition here? Could TXIN
* have fired just before calculating byct? Could TXIN be
* pending here?
*/ */
privep->epstate = USBHS_EPSTATE_IDLE; privep->epstate = USBHS_EPSTATE_IDLE;