From cb64096da6d046e97bb2a5afeda3a803e66bf414 Mon Sep 17 00:00:00 2001 From: Jorge Guzman Date: Sat, 20 Jul 2024 11:33:14 -0300 Subject: [PATCH] board/linum-stm32h753bi: Add support to external sdram Signed-off-by: Jorge Guzman --- .../boards/linum-stm32h753bi/index.rst | 20 +++- .../linum-stm32h753bi/configs/sdram/defconfig | 57 ++++++++++ .../stm32h7/linum-stm32h753bi/include/board.h | 105 ++++++++++++++++++ 3 files changed, 181 insertions(+), 1 deletion(-) create mode 100644 boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig diff --git a/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst b/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst index 55fd0f249f..d987e6006c 100644 --- a/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst +++ b/Documentation/platforms/arm/stm32h7/boards/linum-stm32h753bi/index.rst @@ -759,7 +759,7 @@ This configuration is focused on network testing using the ethernet periferal:: qencoder -------- -Configures and enables TIM5 on CH1(PA0) and CH2(PH11) to handle Quadrature Encoder: +Configures and enables TIM5 on CH1(PA0) and CH2(PH11) to handle Quadrature Encoder:: nsh> qe qe_main: Hardware initialized. Opening the encoder device: /dev/qe0 @@ -769,3 +769,21 @@ Configures and enables TIM5 on CH1(PA0) and CH2(PH11) to handle Quadrature Encod qe_main: 3. 3 qe_main: 4. 2 qe_main: 5. 1 + +sdram +-------- + +This configuration uses the FMC peripheral to connect to external SDRAM with 8 MB and add it to the nuttx heap. + +To test the sdram use the command **ramtest**:: + + nsh> free + total used free maxused maxfree nused nfree + Umem: 9397168 5488 9391680 5880 8388592 28 5 + nsh> ramtest -w -a 0xc0000000 -s 8388608 + RAMTest: Marching ones: c0000000 8388608 + RAMTest: Marching zeroes: c0000000 8388608 + RAMTest: Pattern test: c0000000 8388608 55555555 aaaaaaaa + RAMTest: Pattern test: c0000000 8388608 66666666 99999999 + RAMTest: Pattern test: c0000000 8388608 33333333 cccccccc + RAMTest: Address-in-address test: c0000000 8388608 diff --git a/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig new file mode 100644 index 0000000000..5b37d606d6 --- /dev/null +++ b/boards/arm/stm32h7/linum-stm32h753bi/configs/sdram/defconfig @@ -0,0 +1,57 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_STANDARD_SERIAL is not set +# CONFIG_STM32H7_USE_LEGACY_PINMAP is not set +CONFIG_ARCH="arm" +CONFIG_ARCH_BOARD="linum-stm32h753bi" +CONFIG_ARCH_BOARD_LINUM_STM32H753BI=y +CONFIG_ARCH_CHIP="stm32h7" +CONFIG_ARCH_CHIP_STM32H753BI=y +CONFIG_ARCH_CHIP_STM32H7=y +CONFIG_ARCH_CHIP_STM32H7_CORTEXM7=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARMV7M_DCACHE=y +CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y +CONFIG_ARMV7M_DTCM=y +CONFIG_ARMV7M_ICACHE=y +CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_EXAMPLES_ALARM=y +CONFIG_FS_PROCFS=y +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_INTELHEX_BINARY=y +CONFIG_LIBM=y +CONFIG_MM_REGIONS=5 +CONFIG_NSH_ARCHINIT=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_DISABLE_IFUPDOWN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20010000 +CONFIG_RAW_BINARY=y +CONFIG_RR_INTERVAL=200 +CONFIG_RTC_ALARM=y +CONFIG_RTC_DATETIME=y +CONFIG_RTC_DRIVER=y +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=6 +CONFIG_START_MONTH=12 +CONFIG_START_YEAR=2011 +CONFIG_STM32H7_FMC=y +CONFIG_STM32H7_PWR=y +CONFIG_STM32H7_RTC=y +CONFIG_STM32H7_USART1=y +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_TESTING_RAMTEST=y +CONFIG_USART1_SERIAL_CONSOLE=y diff --git a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h index 594ed09015..3430686f19 100644 --- a/boards/arm/stm32h7/linum-stm32h753bi/include/board.h +++ b/boards/arm/stm32h7/linum-stm32h753bi/include/board.h @@ -439,7 +439,112 @@ #define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_3|GPIO_SPEED_100MHz) /* PG14 */ #define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2|GPIO_SPEED_100MHz) /* PG11 */ +/* SDRAM FMC definitions ****************************************************/ + +/* The following settings correspond to W9864G6KH-6 SDRAM + * part-number ("-6" speed grades ) and FMC_SDCLK frequency of 166 MHz + * (period is ~ 6.25 ns). + */ + +/* Though W9864G6KH-6 SDRAM itself provides 16-bit data bus, + * linum board routes only DQ[15:0] bits. + */ +#define BOARD_FMC_CLK RCC_D1CCIPR_FMCSEL_HCLK + +#if CONFIG_STM32H7_FMC +# define FMC_SDCLK_FREQUENCY (STM32_HCLK_FREQUENCY / 2) +# if FMC_SDCLK_FREQUENCY > 120000000 +# error "FMC SDRAM settings need to be adjusted for a higher FMC_SDCLK frequency" +# elif FMC_SDCLK_FREQUENCY < 120000000 +# warning "The current FMC SDRAM settings may not be optimal for a lower FMC_SDCLK frequency" +# endif +#endif + +#define BOARD_SDRAM1_SIZE (8*1024*1024) + +/* BOARD_FMC_SDCR1 - Initial value for SDRAM control registers for SDRAM + * bank 1. Note bank 2 isn't used! + */ + +#define BOARD_FMC_SDCR1 (FMC_SDCR_COLBITS_8 | /* numcols = 8 bits */ \ + FMC_SDCR_ROWBITS_12 | /* numrows = 12 bits */ \ + FMC_SDCR_WIDTH_16 | /* width = 16 bits */ \ + FMC_SDCR_SDCLK_2X | /* sdclk = 2 hclk */ \ + FMC_SDCR_BANKS_4 | /* 4 internal banks */ \ + FMC_SDCR_BURST_READ | /* enable burst read */ \ + FMC_SDCR_RPIPE_0 | /* rpipe = 0 hclk */ \ + FMC_SDCR_CASLAT_3) /* cas latency = 3 cycles */ + +/* BOARD_FMC_SDTR1 - Initial value for SDRAM timing registers for SDRAM + * bank 1. + * + * FMC_SDTR_TMRD - Load mode register to active delay + * FMC_SDTR_TXSR - Exit self-refresh delay + * FMC_SDTR_TRAS - Self-refresh time + * FMC_SDTR_TRCD - SDRAM common row cycle delay + * FMC_SDTR_TWR - Write recovery time + * FMC_SDTR_TRP - SDRAM common row percharge delay + * FMC_SDTR_TRC - Row to collumn delay + */ + +#define BOARD_FMC_SDTR1 (FMC_SDTR_TMRD(2) | /* tMRD = 2CLK */ \ + FMC_SDTR_TXSR(9) | /* tXSR min = ns */ \ + FMC_SDTR_TRCD(8) | /* tRCD min = ns */ \ + FMC_SDTR_TRAS(6) | /* tRAS min = ns */ \ + FMC_SDTR_TWR(4) | /* tWR = ns */ \ + FMC_SDTR_TRP(2) | /* tRP min = ns */ \ + FMC_SDTR_TRC(8)) /* tRC min = ns */ + +#define BOARD_FMC_SDRAM_REFR_CYCLES 4096 +#define BOARD_FMC_SDRAM_REFR_PERIOD 64 +#define BOARD_FMC_SDRAM_AUTOREFRESH 8 +#define BOARD_FMC_SDRAM_MODE (FMC_SDCMR_MRD_BURST_LENGTH_1 | \ + FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL | \ + FMC_SDCMR_MRD_CAS_LATENCY_3 | \ + FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) + +#define BOARD_FMC_GPIO_CONFIGS \ + (GPIO_FMC_A0_0 | GPIO_SPEED_100MHz), /* PF0 */ \ + (GPIO_FMC_A1_0 | GPIO_SPEED_100MHz), /* PF1 */ \ + (GPIO_FMC_A2_0 | GPIO_SPEED_100MHz), /* PF2 */ \ + (GPIO_FMC_A3_0 | GPIO_SPEED_100MHz), /* PF3 */ \ + (GPIO_FMC_A4_0 | GPIO_SPEED_100MHz), /* PF4 */ \ + (GPIO_FMC_A5_0 | GPIO_SPEED_100MHz), /* PF5 */ \ + (GPIO_FMC_A6_0 | GPIO_SPEED_100MHz), /* PF12 */ \ + (GPIO_FMC_A7_0 | GPIO_SPEED_100MHz), /* PF13 */ \ + (GPIO_FMC_A8_0 | GPIO_SPEED_100MHz), /* PF14 */ \ + (GPIO_FMC_A9_0 | GPIO_SPEED_100MHz), /* PF15 */ \ + (GPIO_FMC_A10_0 | GPIO_SPEED_100MHz), /* PG0 */ \ + (GPIO_FMC_A11_0 | GPIO_SPEED_100MHz), /* PG1 */ \ + (GPIO_FMC_D0_0 | GPIO_SPEED_100MHz), /* PD14 */ \ + (GPIO_FMC_D1_0 | GPIO_SPEED_100MHz), /* PD15 */ \ + (GPIO_FMC_D2_0 | GPIO_SPEED_100MHz), /* PD0 */ \ + (GPIO_FMC_D3_0 | GPIO_SPEED_100MHz), /* PD1 */ \ + (GPIO_FMC_D4_0 | GPIO_SPEED_100MHz), /* PE7 */ \ + (GPIO_FMC_D5_0 | GPIO_SPEED_100MHz), /* PE8 */ \ + (GPIO_FMC_D6_0 | GPIO_SPEED_100MHz), /* PE9 */ \ + (GPIO_FMC_D7_0 | GPIO_SPEED_100MHz), /* PE10 */ \ + (GPIO_FMC_D8_0 | GPIO_SPEED_100MHz), /* PE11 */ \ + (GPIO_FMC_D9_0 | GPIO_SPEED_100MHz), /* PE12 */ \ + (GPIO_FMC_D10_0 | GPIO_SPEED_100MHz), /* PE13 */ \ + (GPIO_FMC_D11_0 | GPIO_SPEED_100MHz), /* PE14 */ \ + (GPIO_FMC_D12_0 | GPIO_SPEED_100MHz), /* PE15 */ \ + (GPIO_FMC_D13_0 | GPIO_SPEED_100MHz), /* PD8 */ \ + (GPIO_FMC_D14_0 | GPIO_SPEED_100MHz), /* PD9 */ \ + (GPIO_FMC_D15_0 | GPIO_SPEED_100MHz), /* PD10 */ \ + (GPIO_FMC_NBL0_0 | GPIO_SPEED_100MHz), /* PE0 */ \ + (GPIO_FMC_NBL1_0 | GPIO_SPEED_100MHz), /* PE1 */ \ + (GPIO_FMC_BA0_0 | GPIO_SPEED_100MHz), /* PG4 */ \ + (GPIO_FMC_BA1_0 | GPIO_SPEED_100MHz), /* PG5 */ \ + (GPIO_FMC_SDNCAS_0 | GPIO_SPEED_100MHz), /* PG15 */ \ + (GPIO_FMC_SDNRAS_0 | GPIO_SPEED_100MHz), /* PF11 */ \ + (GPIO_FMC_SDNWE_2 | GPIO_SPEED_100MHz), /* PC0 */ \ + (GPIO_FMC_SDNE0_1 | GPIO_SPEED_100MHz), /* PC2 */ \ + (GPIO_FMC_SDCKE0_1 | GPIO_SPEED_100MHz), /* PC3 */ \ + (GPIO_FMC_SDCLK_0 | GPIO_SPEED_100MHz) /* PG8 */ + /* QEncoder - TIM5: CH1 and CH2 */ + #define GPIO_TIM5_CH1IN GPIO_TIM5_CH1IN_1 /* PA0 */ #define GPIO_TIM5_CH2IN GPIO_TIM5_CH2IN_2 /* PH11 */