arch/stm32f0l0g0: Fix nxstyle errors
arch/arm/include/stm32f0l0g0/chip.h:
arch/arm/include/stm32f0l0g0/irq.h:
arch/arm/include/stm32f0l0g0/stm32f0_irq.h:
arch/arm/include/stm32f0l0g0/stm32g0_irq.h:
* Fix nxstyle errors.
This commit is contained in:
Nathan Hartman
Abdelatif Guettouche
parent
be572c11b6
commit
cbb8a542e5
@ -1,4 +1,4 @@
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/************************************************************************************
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/****************************************************************************
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* arch/arm/include/stm32f0l0g0/chip.h
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*
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* Copyright (C) 2017-2018 Gregory Nutt. All rights reserved.
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@ -33,27 +33,27 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H
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#define __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H
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/************************************************************************************
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/****************************************************************************
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* Included Files
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************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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****************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_STM32F030RC) || defined(CONFIG_ARCH_CHIP_STM32F030CC)
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# define STM32_FLASH_SIZE (256*1024) /* 256Kb */
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# define STM32_SRAM_SIZE (32*1024) /* 32Kb */
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# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */
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# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 0 /* No I2S modules */
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@ -71,8 +71,8 @@
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#elif defined(CONFIG_ARCH_CHIP_STM32F051R8)
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# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
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# define STM32_SRAM_SIZE (8*1024) /* 8Kb */
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# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */
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# define STM32_SRAM_SIZE (8 * 1024) /* 8Kb */
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# define STM32_NSPI 2 /* Two SPI modules (SPI or I2S) */
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# define STM32_NI2S 2 /* Two I2S modules (SPI or I2S) */
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@ -91,11 +91,11 @@
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#elif defined(CONFIG_ARCH_CHIP_STM32F072C8) || defined(CONFIG_ARCH_CHIP_STM32F072CB)
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# ifdef CONFIG_ARCH_CHIP_STM32F072C8
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# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
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# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */
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# else
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# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
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# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
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# endif
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# define STM32_SRAM_SIZE (16*1024) /* 16Kb */
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# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
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@ -147,11 +147,11 @@
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#elif defined(CONFIG_ARCH_CHIP_STM32F072V8) || defined(CONFIG_ARCH_CHIP_STM32F072VB)
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# ifdef CONFIG_ARCH_CHIP_STM32F072V8
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# define STM32_FLASH_SIZE (64*1024) /* 64Kb */
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# define STM32_FLASH_SIZE (64 * 1024) /* 64Kb */
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# else
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# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
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# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
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# endif
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# define STM32_SRAM_SIZE (16*1024) /* 16Kb */
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# define STM32_SRAM_SIZE (16 * 1024) /* 16Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
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@ -175,11 +175,11 @@
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#elif defined(CONFIG_ARCH_CHIP_STM32F091CB) || defined(CONFIG_ARCH_CHIP_STM32F091CC)
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# ifdef CONFIG_ARCH_CHIP_STM32F091CB
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# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
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# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
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# else
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# define STM32_FLASH_SIZE (256*1024) /* 256Kb */
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# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */
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# endif
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# define STM32_SRAM_SIZE (32*1024) /* 32Kb */
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# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
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@ -204,11 +204,11 @@
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defined(CONFIG_ARCH_CHIP_STM32F091VB) || defined(CONFIG_ARCH_CHIP_STM32F091VC)
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# if defined(CONFIG_ARCH_CHIP_STM32F091RB) || defined(CONFIG_ARCH_CHIP_STM32F091VB)
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# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
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# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
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# else
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# define STM32_FLASH_SIZE (256*1024) /* 256Kb */
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# define STM32_FLASH_SIZE (256 * 1024) /* 256Kb */
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# endif
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# define STM32_SRAM_SIZE (32*1024) /* 32Kb */
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# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3, TIM14-17 */
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@ -236,8 +236,8 @@
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#elif defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \
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defined(CONFIG_ARCH_CHIP_STM32G070RB)
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# define STM32_FLASH_SIZE (128*1024) /* 128Kb */
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# define STM32_SRAM_SIZE (32*1024) /* 32Kb */
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# define STM32_FLASH_SIZE (128 * 1024) /* 128Kb */
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# define STM32_SRAM_SIZE (32 * 1024) /* 32Kb */
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# define STM32_NATIM 1 /* One advanced timer TIM1 */
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# define STM32_NGTIM16 5 /* 16-bit general up/down timers TIM3,
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@ -287,7 +287,7 @@
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# define STM32_NUSBDEV 0 /* No USB full-speed device controller */
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# define STM32_NUSBOTG 0 /* No USB OTG */
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# define STM32_NCEC 1 /* One HDMI-CEC controller */
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# define STM32_NADC 1 /* (1) ADC1, 12-channels */
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# define STM32_NADC 1 /* (1) ADC1, 12-channels */
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# define STM32_NDAC 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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@ -296,7 +296,7 @@
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# define STM32_NCAP 0 /* No Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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/* STM32L EnergyLite Line ***********************************************************/
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/* STM32L EnergyLite Line ***************************************************/
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/* STM32L073XX - With LCD
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* STM32L072XX - No LCD
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@ -491,7 +491,7 @@
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 24 /* Twenty-four Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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@ -544,7 +544,7 @@
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# define STM32_NADC 1 /* One 12-bit module */
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# define STM32_NDAC 2 /* Two DAC channels */
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# define STM32_NCOMP 2 /* Two Analog Comparators */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NCRC 1 /* One CRC module */
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# define STM32_NRNG 1 /* One Random number generator (RNG) */
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# define STM32_NCAP 17 /* Seventeen Capacitive sensing channels */
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# define STM32_NPORTS 6 /* Six GPIO ports, GPIOA-E, H */
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@ -579,10 +579,12 @@
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# error "Unsupported STM32F0xx chip"
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#endif
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/* NVIC priority levels *************************************************************/
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/* Each priority field holds a priority value, 0-31. The lower the value, the greater
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* the priority of the corresponding interrupt. The processor implements only
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* bits[7:6] of each field, bits[5:0] read as zero and ignore writes.
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds a priority value, 0-31. The lower the value,
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* the greater the priority of the corresponding interrupt. The processor
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* implements only bits[7:6] of each field, bits[5:0] read as zero and
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* ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xc0 /* All bits[7:6] set is minimum priority */
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@ -590,16 +592,16 @@
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt priority used */
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/************************************************************************************
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/****************************************************************************
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* Public Types
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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/****************************************************************************
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* Public Data
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************************************************************************************/
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****************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_STM32F0L0G0_CHIP_H */
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@ -76,6 +76,10 @@
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#define STM32_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
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/****************************************************************************
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* Included Files
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****************************************************************************/
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/* Include MCU-specific external interrupt definitions */
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#if defined(CONFIG_ARCH_CHIP_STM32F0)
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@ -53,12 +53,12 @@
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* Pre-processor Definitions
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found
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* in nuttx/arch/arm/include/stm32f0l0g0/irq.h
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* Processor Exceptions (vectors 0-15). These common definitions can be
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* found in nuttx/arch/arm/include/stm32f0l0g0/irq.h
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*/
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#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: WWDG */
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@ -1,4 +1,4 @@
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/****************************************************************************************************
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/****************************************************************************
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* arch/arm/include/stm32f0l0g0/stm32g0_irq.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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@ -32,31 +32,33 @@
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************************************/
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly through nuttx/irq.h */
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H
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#define __ARCH_ARM_INCLUDE_STM32F0L0G0_STM32G0_IRQ_H
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/****************************************************************************************************
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/****************************************************************************
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* Included Files
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****************************************************************************************************/
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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#include <arch/stm32f0l0g0/chip.h>
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/****************************************************************************************************
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************************************/
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
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* bits in the NVIC. This does, however, waste several words of memory in the IRQ
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* to handle mapping tables.
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*
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* Processor Exceptions (vectors 0-15). These common definitions can be found
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* in nuttx/arch/arm/include/stm32f0l0g0/irq.h
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* Processor Exceptions (vectors 0-15). These common definitions can be
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* found in nuttx/arch/arm/include/stm32f0l0g0/irq.h
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*/
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#define STM32_IRQ_WWDG (STM32_IRQ_EXTINT + 0) /* 0: Window Watchdog interrupt */
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@ -97,6 +99,7 @@
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#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \
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defined(CONFIG_ARCH_CHIP_STM32G070RB)
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/* No STM32_IRQ_COMP */
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#else
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# define STM32_IRQ_COMP (STM32_IRQ_EXTINT + 12) /* 12: COMP */
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#endif
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@ -117,7 +120,9 @@
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#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \
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defined(CONFIG_ARCH_CHIP_STM32G070RB)
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/* No STM32_IRQ_DAC */
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/* No STM32_IRQ_LPTIM1 */
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#else
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# define STM32_IRQ_DAC (STM32_IRQ_EXTINT + 17) /* 17: DAC */
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# define STM32_IRQ_LPTIM1 (STM32_IRQ_EXTINT + 17) /* 17: LPTIM1 */
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@ -128,6 +133,7 @@
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#if defined(CONFIG_ARCH_CHIP_STM32G070KB) || defined(CONFIG_ARCH_CHIP_STM32G070CB) || \
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defined(CONFIG_ARCH_CHIP_STM32G070RB)
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/* No STM32_IRQ_LPTIM2 */
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#else
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# define STM32_IRQ_LPTIM2 (STM32_IRQ_EXTINT + 18) /* 18: LPTIM2 */
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#endif
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@ -161,16 +167,15 @@
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# define STM32_IRQ_RNG (STM32_IRQ_EXTINT + 31) /* 31: RNG */
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#endif
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#define STM32_IRQ_NEXTINT (32)
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/****************************************************************************************************
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/****************************************************************************
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* Public Types
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****************************************************************************************************/
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****************************************************************************/
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/****************************************************************************************************
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/****************************************************************************
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* Public Data
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****************************************************************************************************/
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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@ -181,9 +186,9 @@ extern "C"
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#define EXTERN extern
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#endif
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/****************************************************************************************************
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* Public Functions
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****************************************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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