configs/stm32l4r9ai-disco: Fix HSE clock config and clock board to maximum 120 MHz
This commit is contained in:
Juha Niskanen
Gregory Nutt
parent
affc50df66
commit
cbdcb2deed
@ -11,11 +11,13 @@ STM32L4R9AI:
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Microprocessor: 32-bit ARM Cortex M4 at 120MHz STM32L4R9AI
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Memory: 2048 KB Flash and 192+64+384 KB SRAM
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ADC: 1x12-bit, 2.4 MSPS A/D converter: up to 24 channels
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ADC: 1x12-bit, 5 MSPS A/D converter: up to 14 external channels
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DAC: 2 channels
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DFSDM: 4 filters, 8 channels
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DMA: 16-stream DMA controllers with FIFOs and burst support
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Timers: Up to 11 timers: up to eight 16-bit, two 32-bit timers, two
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watchdog timers, and a SysTick timer
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GPIO: Up to 51 I/O ports with interrupt capability
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GPIO: Up to 131 I/O ports with interrupt capability
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I2C: Up to 4 x I2C interfaces
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USARTs: Up to 3 USARTs, 2 UARTs, 1 LPUART
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SPIs: Up to 3 SPIs
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@ -23,23 +25,21 @@ STM32L4R9AI:
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CAN interface
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SDIO interface
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OCTOSPI interface
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Camera interface
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USB: USB 2.0 full-speed device/host/OTG controller with on-chip PHY
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CRC calculation unit
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RTC
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Board features:
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Peripherals: 2 led, 1 d-pad joystick, 2 x LED, LCD, USC OTG FS, SAI stereo
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Digital Microphone, MEMS Accelerometer, Magnetometer,
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Gyroscope, 512 Mbit OCTOSPI Flash, current ammeter
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Peripherals: 1 d-pad joystick, 2 x LED, AMOLED display, USC OTG FS,
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2 x MEMS Digital Microphones, SAI codec, 16 Mbit PSRAM,
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512 Mbit OCTOSPI Flash, current ammeter
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Debug: Serial wire debug and JTAG interfaces
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Uses a STM32F103 to provide a ST-Link for programming, debug similar to the
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OpenOcd FTDI function - USB to JTAG front-end.
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See http://mbed.org/platforms/ST-Nucleo-L476RG for more
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information about these boards.
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Contents
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========
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@ -56,39 +56,22 @@ Contents
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mbed
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====
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The Nucleo-F401RE includes boot loader from mbed:
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The STM32L4R9AI-DISCO includes boot loader from mbed:
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https://mbed.org/platforms/ST-Nucleo-F401RE/
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https://mbed.org/handbook/Homepage
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Using the mbed loader:
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1. Connect the Nucleo-F4x1RE to the host PC using the USB connector.
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2. A new file system will appear called NUCLEO; open it with Windows
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1. Connect the board to the host PC using the USB connector.
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2. A new file system will appear called DIS_L4R9AI; open it with Windows
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Explorer (assuming that you are using Windows).
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3. Drag and drop nuttx.bin into the MBED window. This will load the
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nuttx.bin binary into the Nucleo-F4x1RE. The NUCLEO window will
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close then re-open and the Nucleo-F4x1RE will be running the new code.
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nuttx.bin binary into the board. The DIS_L49RAIO window will
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close then re-open and the board will be running the new code.
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Hardware
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========
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GPIO
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----
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SERIAL_TX=PA_2 USER_BUTTON=PC_13
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SERIAL_RX=PA_3 LED1 =PA_5
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A0=PA_0 USART2RX D0=PA_3 D8 =PA_9
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A1=PA_1 USART2TX D1=PA_2 D9 =PC_7
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A2=PA_4 D2=PA_10 WIFI_CS=D10=PB_6 SPI_CS
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A3=PB_0 WIFI_INT=D3=PB_3 D11=PA_7 SPI_MOSI
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A4=PC_1 SDCS=D4=PB_5 D12=PA_6 SPI_MISO
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A5=PC_0 WIFI_EN=D5=PB_4 LED1=D13=PA_5 SPI_SCK
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LED2=D6=PB_10 I2C1_SDA=D14=PB_9 Probe
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D7=PA_8 I2C1_SCL=D15=PB_8 Probe
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From: https://mbed.org/platforms/ST-Nucleo-F401RE/
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Buttons
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-------
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B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
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@ -96,17 +79,16 @@ Hardware
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LEDs
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----
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The Nucleo F401RE and Nucleo F411RE provide a single user LED, LD2. LD2
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is the green LED connected to Arduino signal D13 corresponding to MCU I/O
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PA5 (pin 21) or PB13 (pin 34) depending on the STM32target.
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The STM32L4R9AI-DISCO board provides two user LEDs, LD1 (orange) and LD2 (green).
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PB0 is LD1 (orange)
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PH4 is LD2 (green)
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- When the I/O is HIGH value, the LED is on.
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- When the I/O is LOW, the LED is off.
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These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
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defined. In that case, the usage by the board port is defined in
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include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
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events as follows when the red LED (PE24) is available:
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include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS-related
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events as follows when the green LED (PH4) is available:
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SYMBOL Meaning LD2
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------------------- ----------------------- -----------
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@ -120,8 +102,8 @@ Hardware
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LED_PANIC The system has crashed Blinking
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LED_IDLE MCU is is sleep mode Not used
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Thus if LD2, NuttX has successfully booted and is, apparently, running
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normally. If LD2 is flashing at approximately 2Hz, then a fatal error
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Thus if LD2 is on, NuttX has successfully booted and is, apparently,
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running normally. If LD2 is flashing at approximately 2Hz, then a fatal error
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has been detected and the system has halted.
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Serial Consoles
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@ -150,7 +132,7 @@ Serial Consoles
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To configure USART1 as the console:
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CONFIG_STM32_USART1=y
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CONFIG_STM32L4_USART1=y
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CONFIG_USART1_SERIALDRIVER=y
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CONFIG_USART1_SERIAL_CONSOLE=y
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CONFIG_USART1_RXBUFSIZE=256
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@ -169,8 +151,6 @@ Serial Consoles
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TXD: PA2 CN9 pin 2(See SB13, 14, 62, 63). CN10 pin 35
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PD5
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UART2 is the default in all of these configurations.
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TTL to RS-232 converter connection:
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Nucleo CN9 STM32F4x1RE
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@ -189,7 +169,7 @@ Serial Consoles
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To configure USART2 as the console:
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CONFIG_STM32_USART2=y
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CONFIG_STM32L4_USART2=y
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CONFIG_USART2_SERIALDRIVER=y
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CONFIG_USART2_SERIAL_CONSOLE=y
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CONFIG_USART2_RXBUFSIZE=256
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@ -199,26 +179,24 @@ Serial Consoles
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CONFIG_USART2_PARITY=0
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CONFIG_USART2_2STOP=0
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USART6
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UART4
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------
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Pins and Connectors:
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RXD: PC7 CN5 pin2, CN10 pin 19
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PA12 CN10, pin 12
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TXD: PC6 CN10, pin 4
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PA11 CN10, pin 14
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RXD: PA1 -> CN11 D5
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TXD: PA0 -> CN17 A4
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To configure USART6 as the console:
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To configure USART4 as the console:
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CONFIG_STM32_USART6=y
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CONFIG_USART6_SERIALDRIVER=y
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CONFIG_USART6_SERIAL_CONSOLE=y
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CONFIG_USART6_RXBUFSIZE=256
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CONFIG_USART6_TXBUFSIZE=256
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CONFIG_USART6_BAUD=115200
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CONFIG_USART6_BITS=8
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CONFIG_USART6_PARITY=0
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CONFIG_USART6_2STOP=0
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CONFIG_STM32L4_UART4=y
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CONFIG_USART4_SERIALDRIVER=y
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CONFIG_USART4_SERIAL_CONSOLE=y
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CONFIG_USART4_RXBUFSIZE=512
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CONFIG_USART4_TXBUFSIZE=256
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CONFIG_USART4_BAUD=2000000
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CONFIG_USART4_BITS=8
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CONFIG_USART4_PARITY=0
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CONFIG_USART4_2STOP=0
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Virtual COM Port
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----------------
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@ -246,97 +224,6 @@ Serial Consoles
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As shipped, SB62 and SB63 are open and SB13 and SB14 closed, so the
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virtual COM port is enabled.
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Shields
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=======
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RS-232 from Cutedigi.com
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------------------------
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Supports a single RS-232 connected via
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Nucleo CN9 STM32F4x1RE Cutedigi
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----------- ------------ --------
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Pin 1 PA3 USART2_RX RXD
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Pin 2 PA2 USART2_TX TXD
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Support for this shield is enabled by selecting USART2 and configuring
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SB13, 14, 62, and 63 as described above under "Serial Consoles"
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Itead Joystick Shield
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---------------------
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See http://imall.iteadstudio.com/im120417014.html for more information
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about this joystick.
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Itead Joystick Connection:
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--------- ----------------- ---------------------------------
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ARDUINO ITEAD NUCLEO-F4x1
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PIN NAME SIGNAL SIGNAL
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--------- ----------------- ---------------------------------
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D3 Button E Output PB3
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D4 Button D Output PB5
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D5 Button C Output PB4
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D6 Button B Output PB10
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D7 Button A Output PA8
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D8 Button F Output PA9
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D9 Button G Output PC7
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A0 Joystick Y Output PA0 ADC1_0
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A1 Joystick X Output PA1 ADC1_1
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--------- ----------------- ---------------------------------
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All buttons are pulled on the shield. A sensed low value indicates
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when the button is pressed.
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NOTE: Button F cannot be used with the default USART1 configuration
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because PA9 is configured for USART1_RX by default. Use select
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different USART1 pins in the board.h file or select a different
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USART or select CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS which will
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eliminate all but buttons A, B, and C.
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Itead Joystick Signal interpretation:
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--------- ----------------------- ---------------------------
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BUTTON TYPE NUTTX ALIAS
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--------- ----------------------- ---------------------------
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Button A Large button A JUMP/BUTTON 3
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Button B Large button B FIRE/BUTTON 2
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Button C Joystick select button SELECT/BUTTON 1
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Button D Tiny Button D BUTTON 6
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Button E Tiny Button E BUTTON 7
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Button F Large Button F BUTTON 4
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Button G Large Button G BUTTON 5
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--------- ----------------------- ---------------------------
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Itead Joystick configuration settings:
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System Type -> STM32 Peripheral Support
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CONFIG_STM32_ADC1=y : Enable ADC1 driver support
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Drivers
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CONFIG_ANALOG=y : Should be automatically selected
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CONFIG_ADC=y : Should be automatically selected
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CONFIG_INPUT=y : Select input device support
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CONFIG_AJOYSTICK=y : Select analog joystick support
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There is nothing in the configuration that currently uses the joystick.
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For testing, you can add the following configuration options to enable the
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analog joystick example at apps/examples/ajoystick:
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CONFIG_NSH_ARCHINIT=y
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CONFIG_EXAMPLES_AJOYSTICK=y
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CONFIG_EXAMPLES_AJOYSTICK_DEVNAME="/dev/ajoy0"
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CONFIG_EXAMPLES_AJOYSTICK_SIGNO=13
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STATUS:
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2014-12-04:
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- Without ADC DMA support, it is not possible to sample both X and Y
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with a single ADC. Right now, only one axis is being converted.
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- There is conflicts with some of the Arduino data pins and the
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default USART1 configuration. I am currently running with USART1
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but with CONFIG_NUCLEO_F401RE_AJOY_MINBUTTONS to eliminate the
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conflict.
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- Current showstopper: I appear to be getting infinite interrupts as
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soon as joystick button interrupts are enabled.
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Configurations
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==============
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@ -424,8 +311,8 @@ Configurations
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nsh:
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---
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Configures the NuttShell (nsh) located at apps/examples/nsh for the
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Nucleo-F401RE board. The Configuration enables the serial interfaces
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on UART2. Support for builtin applications is enabled, but in the base
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STM32L4R9AI-DISCO board. The Configuration enables the serial interfaces
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on UART4. Support for builtin applications is enabled, but in the base
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configuration no builtin applications are selected (see NOTES below).
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NOTES:
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@ -433,11 +320,8 @@ Configurations
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1. This configuration uses the mconf-based configuration tool. To
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change this configuration using that tool, you should:
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a. Build and install the kconfig-mconf tool. See nuttx/README.txt
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see additional README.txt files in the NuttX tools repository.
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b. Execute 'make menuconfig' in nuttx/ in order to start the
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reconfiguration process.
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Execute 'make menuconfig' in nuttx/ in order to start the
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reconfiguration process.
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2. By default, this configuration uses the Generic ARM EABI toolchain
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for Linux. That can easily be reconfigured, of course.
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@ -445,14 +329,11 @@ Configurations
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CONFIG_HOST_LINUX=y : Builds under Linux
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CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : Generic EABI toolchain for Linux
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3. Although the default console is USART2 (which would correspond to
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the Virtual COM port) I have done all testing with the console
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device configured for USART1 (see instruction above under "Serial
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Consoles). I have been using a TTL-to-RS-232 converter.
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3. The default console is UART4
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4. This example has been used to verify the OTGFS functionality. USB is
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4. This example can be used to verify the OTGFS functionality. USB is
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not enabled in the default configuration but can be enabled with the
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following settings:
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following settings: (TODO: need to test!)
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CONFIG_STM32L4_OTGFS=y
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@ -158,51 +158,12 @@
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
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/* SPI2 is used for several peripherals on the Discovery board, including
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* L3GD20 - 3 axis Gyroscope
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* LSM303CTR - eCompass, comprising an accelerometer and magnetometer
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*/
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/* XXX is SPI2 used on Disco? */
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_3
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_3
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_3
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/* PD7; gyroscope CS */
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#define GPIO_SPI_CS_GYRO_OFF \
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(GPIO_INPUT | GPIO_PULLDOWN | GPIO_SPEED_2MHz | \
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GPIO_PORTD | GPIO_PIN7)
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#define GPIO_SPI_CS_GYRO \
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(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | \
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GPIO_OUTPUT_SET | GPIO_PORTD | GPIO_PIN7)
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/* PE0; accelerometer CS */
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#define GPIO_SPI_CS_ACCEL_OFF \
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(GPIO_INPUT | GPIO_PULLDOWN | GPIO_SPEED_2MHz | \
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GPIO_PORTE | GPIO_PIN0)
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#define GPIO_SPI_CS_ACCEL \
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(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | \
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GPIO_OUTPUT_SET | GPIO_PORTE | GPIO_PIN0)
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/* PC0; magnetometer CS */
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#define GPIO_SPI_CS_MAGNETO_OFF \
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(GPIO_INPUT | GPIO_PULLDOWN | GPIO_SPEED_2MHz | \
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GPIO_PORTC | GPIO_PIN0)
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#define GPIO_SPI_CS_MAGNETO \
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(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | \
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GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN0)
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/* XXX these will need to be set up when these get implemented:
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* PD2 gyro INT1
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* PB8 gyro INT2/DRDY
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*
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* PE1 accel INT
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* PC2 magneto DRDY
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* PC1 magneto INT
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*/
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/* LEDs
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*
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* The STM32L4R9AI-DISCO board provides two user LEDs, LD1 (orange) and LD2 (green).
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@ -52,22 +52,30 @@
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/* Clocking *************************************************************************/
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/* The stm32l4r9ai-disco supports both HSE and LSE crystals. As shipped, the HSE
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* crystal is not populated. Therefore the stm32l4r9ai-disco will need to run off the
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* 16MHz HSI clock, or the 32khz-synced MSI, unless you install the HSE xtal.
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* is a 16 MHz crystal X2. Therefore the stm32l4r9ai-disco can run off the 16MHz
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* HSI clock, or the MSI, or the HSE. Here we configure HSE to give us 120MHz system
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* clock (maximum supported for STM32L4+ chips) instead of the more traditional 80MHz
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* that is used by most STM32L4 boards supported by NuttX.
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*/
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/* HSI - 16 MHz RC factory-trimmed
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* LSI - 32 KHz RC
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* MSI - variable up to 48 MHz, synchronized to LSE
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* HSE - not installed
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* HSE - 16 MHz installed
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* LSE - 32.768 kHz installed
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*/
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#define STM32L4_HSI_FREQUENCY 16000000ul
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#define STM32L4_LSI_FREQUENCY 32000
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#define STM32L4_LSE_FREQUENCY 32768
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#define STM32L4_HSE_FREQUENCY 16000000ul
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#define BOARD_AHB_FREQUENCY 80000000ul
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#define STM32L4_SYSCLK_FREQUENCY 120000000ul
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#define BOARD_AHB_FREQUENCY STM32L4_SYSCLK_FREQUENCY
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/* Higher SYSCLK reguires more flash wait states. */
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#define BOARD_FLASH_WAITSTATES 5
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/* XXX there needs to be independent selections for the System Clock Mux and
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* the PLL Source Mux; currently System Clock Mux always is PLL, and PLL
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@ -77,10 +85,8 @@
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#if 0
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# define HSI_CLOCK_CONFIG 1 /* HSI-16 clock configuration */
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#elif 0
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/* Make sure you actually installed one! */
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# define HSE_CLOCK_CONFIG 1 /* HSE with 8 MHz xtal */
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#elif 1
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# define HSE_CLOCK_CONFIG 1 /* HSE with 16 MHz xtal */
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#else
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# define MSI_CLOCK_CONFIG 1 /* MSI @ 4 MHz autotrimmed via LSE */
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#endif
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@ -89,20 +95,19 @@
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#define STM32L4_BOARD_USEHSI 1
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/* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly
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as per comment above HSI) */
|
||||
/* Prescaler common to all PLL inputs; will be 1 */
|
||||
|
||||
#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
|
||||
|
||||
/* 'main' PLL config; we use this to generate our system clock via the R
|
||||
* output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz
|
||||
* output. We set it up as 16 MHz / 1 * 15 / 2 = 120 MHz
|
||||
*
|
||||
* XXX NOTE: currently the main PLL is implicitly turned on and is implicitly
|
||||
* the system clock; this should be configurable since not all applications may
|
||||
* want things done this way.
|
||||
*/
|
||||
|
||||
#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10)
|
||||
#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(15)
|
||||
#define STM32L4_PLLCFG_PLLP 0
|
||||
#undef STM32L4_PLLCFG_PLLP_ENABLED
|
||||
#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2
|
||||
@ -138,8 +143,6 @@
|
||||
#define STM32L4_PLLSAI2CFG_PLLR 0
|
||||
#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
|
||||
|
||||
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
|
||||
|
||||
/* CLK48 will come from PLLSAI1 (implicitly Q) */
|
||||
|
||||
#define STM32L4_USE_CLK48 1
|
||||
@ -149,31 +152,35 @@
|
||||
|
||||
#define STM32L4_USE_LSE 1
|
||||
|
||||
/* AHB clock (HCLK) is SYSCLK (80MHz) */
|
||||
/* AHB clock (HCLK) is SYSCLK (120 MHz) */
|
||||
|
||||
#define STM32L4_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32L4_HCLK_FREQUENCY STM32L4_SYSCLK_FREQUENCY
|
||||
#define STM32L4_BOARD_HCLK STM32L4_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */
|
||||
/* APB1 clock (PCLK1) is HCLK/1 (120 MHz) */
|
||||
|
||||
#define STM32L4_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
|
||||
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
|
||||
#define STM32L4_PCLK1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1)
|
||||
|
||||
/* Timers driven from APB1 will be twice PCLK1 */
|
||||
/* REVISIT : this can be configured */
|
||||
/* The timer clock frequencies are automatically defined by hardware.
|
||||
* If the APB prescaler equals 1, the timer clock frequencies are set to the
|
||||
* same frequency as that of the APB domain. Otherwise they are set to twice.
|
||||
*
|
||||
* REVISIT : this can be configured
|
||||
*/
|
||||
|
||||
#define STM32L4_APB1_TIM2_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM3_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM4_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM5_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM6_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM7_CLKIN (2*STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM2_CLKIN (STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM3_CLKIN (STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM4_CLKIN (STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM5_CLKIN (STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM6_CLKIN (STM32L4_PCLK1_FREQUENCY)
|
||||
#define STM32L4_APB1_TIM7_CLKIN (STM32L4_PCLK1_FREQUENCY)
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (80MHz) */
|
||||
/* APB2 clock (PCLK2) is HCLK (120 MHz) */
|
||||
|
||||
#define STM32L4_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
|
||||
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY/1)
|
||||
#define STM32L4_PCLK2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 1)
|
||||
|
||||
/* The timer clock frequencies are automatically defined by hardware.
|
||||
* If the APB prescaler equals 1, the timer clock frequencies are set to the
|
||||
@ -191,30 +198,42 @@
|
||||
|
||||
#define STM32L4_BOARD_USEHSE 1
|
||||
|
||||
/* XXX sysclk mux = pllclk */
|
||||
|
||||
/* XXX pll source mux = hse */
|
||||
|
||||
/* Prescaler common to all PLL inputs */
|
||||
|
||||
#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
|
||||
|
||||
/* 'main' PLL config; we use this to generate our system clock */
|
||||
/* 'main' PLL config; we use this to generate our system clock via the R
|
||||
* output. We set it up as 16 MHz / 1 * 15 / 2 = 120 MHz
|
||||
*
|
||||
* XXX NOTE: currently the main PLL is implicitly turned on and is implicitly
|
||||
* the system clock; this should be configurable since not all applications may
|
||||
* want things done this way.
|
||||
*/
|
||||
|
||||
#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20)
|
||||
#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(15)
|
||||
#define STM32L4_PLLCFG_PLLP 0
|
||||
#undef STM32L4_PLLCFG_PLLP_ENABLED
|
||||
#define STM32L4_PLLCFG_PLLQ 0
|
||||
#undef STM32L4_PLLCFG_PLLQ_ENABLED
|
||||
#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2
|
||||
#define STM32L4_PLLCFG_PLLQ_ENABLED
|
||||
#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
|
||||
#define STM32L4_PLLCFG_PLLR_ENABLED
|
||||
|
||||
/* 'SAIPLL1' is used to generate the 48 MHz clock */
|
||||
/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't
|
||||
* do that with the main PLL's N value. We set N = 12, and enable
|
||||
* the Q output (ultimately for CLK48) with /4. So,
|
||||
* 16 MHz / 1 * 12 / 4 = 48 MHz
|
||||
*
|
||||
* XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the
|
||||
* menuconfig, or else all this is a moot point, and the various 48 MHz
|
||||
* peripherals will not work (RNG at present). I would suggest removing
|
||||
* that option from Kconfig altogether, and simply making it an option
|
||||
* that is selected via a #define here, like all these other params.
|
||||
*/
|
||||
|
||||
#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(12)
|
||||
#define STM32L4_PLLSAI1CFG_PLLP 0
|
||||
#undef STM32L4_PLLSAI1CFG_PLLP_ENABLED
|
||||
#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_2
|
||||
#define STM32L4_PLLSAI1CFG_PLLQ RCC_PLLSAI1CFG_PLLQ_4
|
||||
#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
|
||||
#define STM32L4_PLLSAI1CFG_PLLR 0
|
||||
#undef STM32L4_PLLSAI1CFG_PLLR_ENABLED
|
||||
@ -227,11 +246,9 @@
|
||||
#define STM32L4_PLLSAI2CFG_PLLR 0
|
||||
#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
|
||||
|
||||
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
|
||||
|
||||
/* Enable CLK48; get it from PLLSAI1 */
|
||||
|
||||
#define STM32L4_USE_CLK48
|
||||
#define STM32L4_USE_CLK48 1
|
||||
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
|
||||
|
||||
/* Enable LSE (for the RTC) */
|
||||
@ -271,25 +288,37 @@
|
||||
#define STM32L4_BOARD_USEMSI 1
|
||||
#define STM32L4_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M
|
||||
|
||||
/* XXX sysclk mux = pllclk */
|
||||
|
||||
/* XXX pll source mux = msi */
|
||||
|
||||
/* Prescaler common to all PLL inputs */
|
||||
|
||||
#define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
|
||||
|
||||
/* 'main' PLL config; we use this to generate our system clock */
|
||||
/* 'main' PLL config; we use this to generate our system clock via the R
|
||||
* output. We set it up as 4 MHz / 1 * 60 / 2 = 120 MHz
|
||||
*
|
||||
* XXX NOTE: currently the main PLL is implicitly turned on and is implicitly
|
||||
* the system clock; this should be configurable since not all applications may
|
||||
* want things done this way.
|
||||
*/
|
||||
|
||||
#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40)
|
||||
#define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(60)
|
||||
#define STM32L4_PLLCFG_PLLP 0
|
||||
#undef STM32L4_PLLCFG_PLLP_ENABLED
|
||||
#define STM32L4_PLLCFG_PLLQ 0
|
||||
#undef STM32L4_PLLCFG_PLLQ_ENABLED
|
||||
#define STM32L4_PLLCFG_PLLQ RCC_PLLCFG_PLLQ_2
|
||||
#define STM32L4_PLLCFG_PLLQ_ENABLED
|
||||
#define STM32L4_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
|
||||
#define STM32L4_PLLCFG_PLLR_ENABLED
|
||||
|
||||
/* 'SAIPLL1' is used to generate the 48 MHz clock */
|
||||
/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't
|
||||
* do that with the main PLL's N value. We set N = 12, and enable
|
||||
* the Q output (ultimately for CLK48) with /4. So,
|
||||
* 4 MHz / 1 * 24 / 2 = 48 MHz
|
||||
*
|
||||
* XXX NOTE: currently the SAIPLL /must/ be explicitly selected in the
|
||||
* menuconfig, or else all this is a moot point, and the various 48 MHz
|
||||
* peripherals will not work (RNG at present). I would suggest removing
|
||||
* that option from Kconfig altogether, and simply making it an option
|
||||
* that is selected via a #define here, like all these other params.
|
||||
*/
|
||||
|
||||
#define STM32L4_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24)
|
||||
#define STM32L4_PLLSAI1CFG_PLLP 0
|
||||
@ -307,11 +336,9 @@
|
||||
#define STM32L4_PLLSAI2CFG_PLLR 0
|
||||
#undef STM32L4_PLLSAI2CFG_PLLR_ENABLED
|
||||
|
||||
#define STM32L4_SYSCLK_FREQUENCY 80000000ul
|
||||
|
||||
/* Enable CLK48; get it from PLLSAI1 */
|
||||
|
||||
#define STM32L4_USE_CLK48
|
||||
#define STM32L4_USE_CLK48 1
|
||||
#define STM32L4_CLK48_SEL RCC_CCIPR_CLK48SEL_PLLSAI1
|
||||
|
||||
/* Enable LSE (for the RTC) */
|
||||
@ -344,7 +371,7 @@
|
||||
#define STM32L4_APB2_TIM1_CLKIN (STM32L4_PCLK2_FREQUENCY)
|
||||
#define STM32L4_APB2_TIM8_CLKIN (STM32L4_PCLK2_FREQUENCY)
|
||||
|
||||
#endif
|
||||
#endif /* clock selection */
|
||||
|
||||
/* The timer clock frequencies are automatically defined by hardware.
|
||||
* If the APB prescaler equals 1, the timer clock frequencies are set to the same
|
||||
|
||||
@ -14,7 +14,7 @@ CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_BOARDCTL_IOCTL=y
|
||||
CONFIG_BOARDCTL_UNIQUEID=y
|
||||
CONFIG_BOARDCTL_UNIQUEID_SIZE=12
|
||||
CONFIG_BOARD_LOOPSPERMSEC=8499
|
||||
CONFIG_BOARD_LOOPSPERMSEC=9234
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DEV_LOOP=y
|
||||
CONFIG_DEV_ZERO=y
|
||||
|
||||
Loading…
Reference in New Issue
Block a user