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stm32h7:Use inttypes in printing macros

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This commit is contained in:
David Sidrane 2021-04-20 07:04:07 -07:00 committed by Xiang Xiao
parent 9b8399effe
commit cbe3e120d5
4 changed files with 68 additions and 49 deletions
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2
arch/arm/src/stm32h7/stm32_dma.c
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@ -2054,7 +2054,7 @@ static bool stm32_bdma_capable(FAR stm32_dmacfg_t *cfg)
((mend + 1) & (ARMV7M_DCACHE_LINESIZE - 1)) != 0)
{
dmainfo("stm32_dmacapable: dcache unaligned "
"maddr:0x%08" PRIx32 " mend:0x%08x\n",
"maddr:0x%08" PRIx32 " mend:0x%08" PRIx32 "\n",
cfg->maddr, mend);
#if !defined(CONFIG_STM32H7_DMACAPABLE_ASSUME_CACHE_ALIGNED)
return false;

15
arch/arm/src/stm32h7/stm32_otgdev.c
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@ -25,6 +25,7 @@
#include <nuttx/config.h>
#include <sys/types.h>
#include <inttypes.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
@ -905,7 +906,7 @@ static uint32_t stm32_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
uinfo("[repeats %d more times]\n", count - 3);
uinfo("[repeats %" PRId32 " more times]\n", count - 3);
}
/* Save the new address, value, and count */
@ -917,7 +918,7 @@ static uint32_t stm32_getreg(uint32_t addr)
/* Show the register value read */
uinfo("%08x->%08x\n", addr, val);
uinfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val);
return val;
}
#endif
@ -935,7 +936,7 @@ static void stm32_putreg(uint32_t val, uint32_t addr)
{
/* Show the register value being written */
uinfo("%08x<-%08x\n", addr, val);
uinfo("%08" PRIx32 "->%08" PRIx32 "\n", addr, val);
/* Write the value */
@ -1289,8 +1290,8 @@ static void stm32_epin_request(FAR struct stm32_usbdev_s *priv,
return;
}
uinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n",
privep->epphy, privreq, privreq->req.len,
uinfo("EP%" PRId8 " req=%p: len=%" PRId16 " xfrd=%" PRId16" zlp=%"
PRId8 "\n", privep->epphy, privreq, privreq->req.len,
privreq->req.xfrd, privep->zlp);
/* Check for a special case: If we are just starting a request (xfrd==0)
@ -2731,7 +2732,7 @@ static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv)
if ((daint & 1) != 0)
{
regval = stm32_getreg(STM32_OTG_DOEPINT(epno));
uerr("DOEPINT(%d) = %08x\n", epno, regval);
uerr("DOEPINT(%d) = %08" PRIx32 "\n", epno, regval);
stm32_putreg(0xff, STM32_OTG_DOEPINT(epno));
}
@ -2970,7 +2971,7 @@ static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv)
{
if ((daint & 1) != 0)
{
uerr("DIEPINT(%d) = %08x\n",
uerr("DIEPINT(%d) = %08" PRIx32 "\n",
epno, stm32_getreg(STM32_OTG_DIEPINT(epno)));
stm32_putreg(0xff, STM32_OTG_DIEPINT(epno));
}

81
arch/arm/src/stm32h7/stm32_sdmmc.c
View File

@ -24,6 +24,7 @@
#include <nuttx/config.h>
#include <inttypes.h>
#include <stdint.h>
#include <stdbool.h>
#include <string.h>
@ -742,7 +743,7 @@ static inline void stm32_setclkcr(struct stm32_dev_s *priv, uint32_t clkcr)
sdmmc_putreg32(priv, regval, STM32_SDMMC_CLKCR_OFFSET);
mcinfo("CLKCR: %08x PWR: %08x\n",
mcinfo("CLKCR: %08" PRIx32 " PWR: %08" PRIx32 "\n",
sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET),
sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET));
}
@ -981,14 +982,22 @@ static void stm32_sample(struct stm32_dev_s *priv, int index)
static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg)
{
mcinfo("SDIO Registers: %s\n", msg);
mcinfo(" POWER[%08x]: %08x\n", STM32_SDMMC_POWER_OFFSET, regs->power);
mcinfo(" CLKCR[%08x]: %08x\n", STM32_SDMMC_CLKCR_OFFSET, regs->clkcr);
mcinfo(" DCTRL[%08x]: %08x\n", STM32_SDMMC_DCTRL_OFFSET, regs->dctrl);
mcinfo(" DTIMER[%08x]: %08x\n", STM32_SDMMC_DTIMER_OFFSET, regs->dtimer);
mcinfo(" DLEN[%08x]: %08x\n", STM32_SDMMC_DLEN_OFFSET, regs->dlen);
mcinfo(" DCOUNT[%08x]: %08x\n", STM32_SDMMC_DCOUNT_OFFSET, regs->dcount);
mcinfo(" STA[%08x]: %08x\n", STM32_SDMMC_STA_OFFSET, regs->sta);
mcinfo(" MASK[%08x]: %08x\n", STM32_SDMMC_MASK_OFFSET, regs->mask);
mcinfo(" POWER[%08x]: %08" PRIx8 "\n", STM32_SDMMC_POWER_OFFSET,
regs->power);
mcinfo(" CLKCR[%08x]: %08" PRIx16 "\n", STM32_SDMMC_CLKCR_OFFSET,
regs->clkcr);
mcinfo(" DCTRL[%08x]: %08" PRIx16 "\n", STM32_SDMMC_DCTRL_OFFSET,
regs->dctrl);
mcinfo(" DTIMER[%08x]: %08" PRIx32 "\n", STM32_SDMMC_DTIMER_OFFSET,
regs->dtimer);
mcinfo(" DLEN[%08x]: %08" PRIx32 "\n", STM32_SDMMC_DLEN_OFFSET,
regs->dlen);
mcinfo(" DCOUNT[%08x]: %08" PRIx32 "\n", STM32_SDMMC_DCOUNT_OFFSET,
regs->dcount);
mcinfo(" STA[%08x]: %08" PRIx32 "\n", STM32_SDMMC_STA_OFFSET,
regs->sta);
mcinfo(" MASK[%08x]: %08" PRIx32 "\n", STM32_SDMMC_MASK_OFFSET,
regs->mask);
}
#endif
@ -1403,7 +1412,7 @@ static void stm32_eventtimeout(wdparm_t arg)
DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0 ||
priv->wkupevent != 0);
mcinfo("sta: %08x enabled irq: %08x\n",
mcinfo("sta: %08" PRIx32 " enabled irq: %08" PRIx32 "\n",
sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET),
sdmmc_getreg32(priv, STM32_SDMMC_MASK_OFFSET));
@ -1414,7 +1423,7 @@ static void stm32_eventtimeout(wdparm_t arg)
/* Yes.. wake up any waiting threads */
stm32_endwait(priv, SDIOWAIT_TIMEOUT);
mcerr("Timeout: remaining: %d\n", priv->remaining);
mcerr("Timeout: remaining: %u\n", priv->remaining);
}
}
@ -1712,7 +1721,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
* Sets STM32_SDMMC_ICR_DCRCFAILC
*/
mcerr("ERROR: Data block CRC failure, remaining: %d\n",
mcerr("ERROR: Data block CRC failure, remaining: %u\n",
priv->remaining);
stm32_endtransfer(priv,
@ -1727,7 +1736,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
* Sets STM32_SDMMC_ICR_DTIMEOUTC
*/
mcerr("ERROR: Data timeout, remaining: %d\n",
mcerr("ERROR: Data timeout, remaining: %u\n",
priv->remaining);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE |
@ -1742,7 +1751,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
* Sets STM32_SDMMC_ICR_RXOVERRC
*/
mcerr("ERROR: RX FIFO overrun, remaining: %d\n",
mcerr("ERROR: RX FIFO overrun, remaining: %u\n",
priv->remaining);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE |
@ -1757,7 +1766,7 @@ static int stm32_sdmmc_interrupt(int irq, void *context, void *arg)
* Sets STM32_SDMMC_ICR_TXUNDERRC
*/
mcerr("ERROR: TX FIFO underrun, remaining: %d\n",
mcerr("ERROR: TX FIFO underrun, remaining: %u\n",
priv->remaining);
stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE |
@ -1943,7 +1952,7 @@ static void stm32_reset(FAR struct sdio_dev_s *dev)
leave_critical_section(flags);
mcinfo("CLCKR: %08x POWER: %08x\n",
mcinfo("CLCKR: %08" PRIx32 " POWER: %08" PRIx32 "\n",
sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET),
sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET));
}
@ -2212,7 +2221,8 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
sdmmc_putreg32(priv, STM32_SDMMC_CMDDONE_ICR | STM32_SDMMC_RESPDONE_ICR,
STM32_SDMMC_ICR_OFFSET);
mcinfo("cmd: %08x arg: %08x regval: %08x enabled irq: %08x\n",
mcinfo("cmd: %08" PRIx32 " arg: %08" PRIx32 " regval: %08" PRIx32
" enabled irq: %08" PRIx32 "\n",
cmd, arg, regval, sdmmc_getreg32(priv, STM32_SDMMC_MASK_OFFSET));
/* Write the SDIO CMD */
@ -2486,7 +2496,8 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
{
if (--timeout <= 0)
{
mcerr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n",
mcerr("ERROR: Timeout cmd: %08" PRIx32 " events: %08" PRIx32
" STA: %08" PRIx32 "\n",
cmd, events, sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET));
return -ETIMEDOUT;
@ -2565,7 +2576,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R5_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE)
{
mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd);
ret = -EINVAL;
}
else
@ -2576,12 +2587,12 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET);
if ((regval & STM32_SDMMC_STA_CTIMEOUT) != 0)
{
mcerr("ERROR: Command timeout: %08x\n", regval);
mcerr("ERROR: Command timeout: %08" PRIx32 "\n", regval);
ret = -ETIMEDOUT;
}
else if ((regval & STM32_SDMMC_STA_CCRCFAIL) != 0)
{
mcerr("ERROR: CRC failure: %08x\n", regval);
mcerr("ERROR: CRC failure: %08" PRIx32 "\n", regval);
ret = -EIO;
}
#if defined(CONFIG_DEBUG_FEATURES)
@ -2593,7 +2604,8 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd,
if ((uint8_t)(respcmd & STM32_SDMMC_RESPCMD_MASK) !=
(cmd & MMCSD_CMDIDX_MASK))
{
mcerr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd);
mcerr("ERROR: RESCMD=%02" PRIx32 " CMD=%08" PRIx32
"\n", respcmd, cmd);
ret = -EINVAL;
}
}
@ -2631,7 +2643,7 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE)
{
mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd);
ret = -EINVAL;
}
else
@ -2642,12 +2654,12 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd,
regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET);
if (regval & STM32_SDMMC_STA_CTIMEOUT)
{
mcerr("ERROR: Timeout STA: %08x\n", regval);
mcerr("ERROR: Timeout STA: %08" PRIx32 "\n", regval);
ret = -ETIMEDOUT;
}
else if (regval & STM32_SDMMC_STA_CCRCFAIL)
{
mcerr("ERROR: CRC fail STA: %08x\n", regval);
mcerr("ERROR: CRC fail STA: %08" PRIx32 "\n", regval);
ret = -EIO;
}
}
@ -2690,7 +2702,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd,
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R4_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
{
mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd);
ret = -EINVAL;
}
else
@ -2703,7 +2715,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd,
regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET);
if (regval & STM32_SDMMC_STA_CTIMEOUT)
{
mcerr("ERROR: Timeout STA: %08x\n", regval);
mcerr("ERROR: Timeout STA: %08" PRIx32 "\n", regval);
ret = -ETIMEDOUT;
}
}
@ -2969,7 +2981,7 @@ static void stm32_callbackenable(FAR struct sdio_dev_s *dev,
{
struct stm32_dev_s *priv = (struct stm32_dev_s *)dev;
mcinfo("eventset: %02x\n", eventset);
mcinfo("eventset: %02" PRIx8 "\n", eventset);
DEBUGASSERT(priv != NULL);
priv->cbevents = eventset;
@ -3050,8 +3062,8 @@ static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
(uintptr_t)buffer + buflen <= SRAM4_END))
{
mcerr("invalid IDMA address "
"buffer:0x%08x end:0x%08x\n",
buffer, buffer + buflen - 1);
"buffer:0x%08" PRIxPTR " end:0x%08" PRIxPTR "\n",
(uintptr_t)buffer, (uintptr_t)(buffer + buflen - 1));
return -EFAULT;
}
}
@ -3070,7 +3082,7 @@ static int stm32_dmapreflight(FAR struct sdio_dev_s *dev,
((uintptr_t)(buffer + buflen) & (ARMV7M_DCACHE_LINESIZE - 1)) != 0))
{
mcerr("dcache unaligned "
"buffer:0x%08x end:0x%08x\n",
"buffer:%p end:%p\n",
buffer, buffer + buflen - 1);
return -EFAULT;
}
@ -3282,7 +3294,7 @@ static void stm32_callback(void *arg)
/* Is a callback registered? */
DEBUGASSERT(priv != NULL);
mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n",
mcinfo("Callback %p(%p) cbevents: %02" PRIx8 " cdstatus: %02" PRIx8 "\n",
priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus);
if (priv->callback)
@ -3518,7 +3530,8 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot)
leave_critical_section(flags);
mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus);
mcinfo("cdstatus OLD: %02" PRIx8 " NEW: %02" PRIx8 "\n",
cdstatus, priv->cdstatus);
/* Perform any requested callback if the status has changed */
@ -3561,7 +3574,7 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect)
priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED;
}
mcinfo("cdstatus: %02x\n", priv->cdstatus);
mcinfo("cdstatus: %02" PRIx8 "\n", priv->cdstatus);
leave_critical_section(flags);
}
#endif /* CONFIG_STM32H7_SDMMC1 || CONFIG_STM32H7_SDMMC2 */

19
arch/arm/src/stm32h7/stm32_spi.c
View File

@ -48,6 +48,7 @@
#include <nuttx/config.h>
#include <sys/types.h>
#include <inttypes.h>
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
@ -1026,11 +1027,13 @@ static inline void spi_writebyte(FAR struct stm32_spidev_s *priv,
#ifdef CONFIG_DEBUG_SPI_INFO
static void spi_dumpregs(FAR struct stm32_spidev_s *priv)
{
spiinfo("CR1: 0x%08x CFG1: 0x%08x CFG2: 0x%08x\n",
spiinfo("CR1: 0x%08" PRIx32 " CFG1: 0x%08" PRIx32
" CFG2: 0x%08" PRIx32 "\n",
spi_getreg(priv, STM32_SPI_CR1_OFFSET),
spi_getreg(priv, STM32_SPI_CFG1_OFFSET),
spi_getreg(priv, STM32_SPI_CFG2_OFFSET));
spiinfo("IER: 0x%08x SR: 0x%08x I2SCFGR: 0x%08x\n",
spiinfo("IER: 0x%08" PRIx32 " SR: 0x%08" PRIx32
" I2SCFGR: 0x%08" PRIx32 "\n",
spi_getreg(priv, STM32_SPI_IER_OFFSET),
spi_getreg(priv, STM32_SPI_SR_OFFSET),
spi_getreg(priv, STM32_SPI_I2SCFGR_OFFSET));
@ -1527,7 +1530,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev,
* will be faster.
*/
spiinfo("Frequency %d->%d\n", frequency, actual);
spiinfo("Frequency %" PRId32 "->%" PRId32 "\n", frequency, actual);
priv->frequency = frequency;
priv->actual = actual;
@ -1557,7 +1560,7 @@ static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
uint32_t setbits = 0;
uint32_t clrbits = 0;
spiinfo("mode=%d\n", mode);
spiinfo("mode=%" PRIx32 "\n", (uint32_t) mode);
/* Has the mode changed? */
@ -1697,7 +1700,7 @@ static int spi_hwfeatures(FAR struct spi_dev_s *dev,
uint32_t setbits = 0;
uint32_t clrbits = 0;
spiinfo("features=%08x\n", features);
spiinfo("features=%08" PRIx8 "\n", features);
/* Transfer data LSB first? */
@ -1802,11 +1805,13 @@ static uint32_t spi_send(FAR struct spi_dev_s *dev, uint32_t wd)
if (priv->nbits > 8)
{
spiinfo("Sent: %04x Return: %04x Status: %02x\n", wd, ret, regval);
spiinfo("Sent: %04" PRIx32 " Return: %04" PRIx32 " Status: %02" PRIx32
"\n", wd, ret, regval);
}
else
{
spiinfo("Sent: %02x Return: %02x Status: %02x\n", wd, ret, regval);
spiinfo("Sent: %02" PRIx32 " Return: %02" PRIx32 " Status: %02" PRIx32
"\n", wd, ret, regval);
}
UNUSED(regval);