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Add clock initialization logic for the Nucleus2g boad

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2741 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo 2010-06-12 18:47:02 +00:00
parent d1246d9af7
commit cbfefda2f3
3 changed files with 74 additions and 0 deletions
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4
configs/nucleus2g/README.txt
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@ -286,6 +286,9 @@ Nucleus 2G Configuration Options
the delay actually is 100 seconds.
Individual subsystems can be enabled:
CONFIG_LPC17_MAINOSC=y
CONFIG_LPC17_PLL0=y
CONFIG_LPC17_PLL1=n
CONFIG_LPC17_ETHERNET=n
CONFIG_LPC17_USBHOST=n
CONFIG_LPC17_USBOTG=n
@ -315,6 +318,7 @@ Nucleus 2G Configuration Options
CONFIG_LPC17_ADC=n
CONFIG_LPC17_DAC=n
CONFIG_LPC17_GPDMA=n
CONFIG_LP17_FLASH=n
LPC17xx specific device driver settings

69
configs/nucleus2g/include/board.h
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@ -48,9 +48,78 @@
************************************************************************************/
/* Clocking *************************************************************************/
/* NOTE: The following definitions require lpc17_syscon.h. It is not included here
* because the including C file may not have that file in its include path.
*/
#define BOARD_XTAL_FREQUENCY (12000000) /* XTAL oscillator frequency */
#define BOARD_OSCCLK_FREQUENCY BOARD_XTAL_FREQUENCY /* Main oscillator frequency */
#define BOARD_RTCCLK_FREQUENCY (32000) /* RTC oscillator frequency */
#define BOARD_INTRCOSC_FREQUENCY (4000000) /* Internal RC oscillator frequency */
/* This is the clock setup we configure for:
*
* SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source
* PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, pre-divider=1
* CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6
*/
#define LPC17_CCLK 80000000 /* 80Mhz*/
/* Select the main oscillator as the frequency source. SYSCLK is then the frequency
* of the main osciallator.
*/
#undef CONFIG_LPC17_MAINOSC
#define CONFIG_LPC17_MAINOSC 1
#define BOARD_SCS_VALUE SYSCON_SCS_OSCEN
/* Select the main oscillator and CCLK divider. The output of the divider is CCLK.
* The input to the divider (PLLCLK) will be determined by the PLL output.
*/
#define BOARD_CCLKCFG_DIVIDER 6
#define BOARD_CCLKCFG_VALUE ((BOARD_CCLKCFG_DIVIDER-1) << SYSCON_CCLKCFG_SHIFT)
/* PLL0. PLL0 is used to generate the CPU clock divider input (PLLCLK).
*
* Source clock: Main oscillator
* PLL0 Multiplier value (M): 20
* PLL0 Pre-divider value (N): 1
*/
#undef CONFIG_LPC17_PLL0
#define CONFIG_LPC17_PLL0 1
#define BOARD_CLKSRCSEL_VALUE SYSCON_CLKSRCSEL_MAIN
#define BOARD_PLL0CFG_MSEL 20
#define BOARD_PLL0CFG_NSEL 1
#define BOARD_PLL0CFG_VALUE \
(((BOARD_PLL0CFG_MSEL-1) << SYSCON_PLL0CFG_MSEL_SHIFT) | \
((BOARD_PLL0CFG_NSEL-1) << SYSCON_PLL0CFG_NSEL_SHIFT))
/* PLL1 -- Not used. */
#undef CONFIG_LPC17_PLL0
#define BOARD_PLL1CFG_MSEL 36
#define BOARD_PLL1CFG_NSEL 1
#define BOARD_PLL1CFG_VALUE \
(((BOARD_PLL1CFG_MSEL-1) << SYSCON_PLL1CFG_MSEL_SHIFT) | \
((BOARD_PLL1CFG_NSEL-1) << SYSCON_PLL1CFG_NSEL_SHIFT))
/* USB divider. This divder is used when PLL1 is not enabled to get the USB clock
* from PLL0:
*
* USBCLK = PLL0CLK / 10 = 48MHz
*/
#define BOARD_USBCLKCFG_VALUE SYSCON_USBCLKCFG_DIV10
/* FLASH Configuration */
#undef CONFIG_LP17_FLASH
#define CONFIG_LP17_FLASH 1
#define BOARD_FLASHCFG_VALUE 0x0000303a
/* LED definitions ******************************************************************/

1
configs/nucleus2g/ostest/defconfig
View File

@ -101,6 +101,7 @@ CONFIG_LPC17_BUILDROOT=y
# Individual subsystems can be enabled:
#
# Individual subsystems can be enabled:
# (MAINOSC, PLL0, PLL1 and FLASH are controlled in board.h)
CONFIG_LPC17_ETHERNET=n
CONFIG_LPC17_USBHOST=n
CONFIG_LPC17_USBOTG=n