SAM3U/4L changes to hide differences by clocking in those MCUs
This commit is contained in:
Gregory Nutt
parent
88226dd5b1
commit
cc8906e701
@ -4927,4 +4927,6 @@
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WDT register definition header file (2013-6-8).
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* nuttx/arch/arm/src/sam34/chip/sam4l_usart.h and sam4l_picouart.h:
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Add UART/USART register defintion files for the SAM4L (2013-6-8).
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* arm/src/sam34/chip/sam3u_periphclks.h: More macros and definitions
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to generalize peripheral clocking and to hide differences between
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the SAM3U and the SAM4L (2013-6-8).
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@ -362,6 +362,15 @@ config SAM34_HSMCI
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endmenu
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config SAM32_RESET_PERIPHCLKS
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bool "Enable all peripheral clocks on reset"
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default n
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depends on ARCH_CHIP_SAM4L
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---help---
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By default, only a few necessary peripheral clocks are enabled at
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reset. If this setting is enabled, then all clocking will be enabled
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to all of the selected peripherals on reset.
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comment "AT91SAM3/4 USART Configuration"
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config USART0_ISUART
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@ -1,5 +1,5 @@
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/****************************************************************************************
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* arch/arm/src/sam34/chip/sam_pmc.h
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* arch/arm/src/sam34/chip/sam3u_pmc.h
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*
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* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@ -33,8 +33,8 @@
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*
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****************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H
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#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H
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#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H
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/****************************************************************************************
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* Included Files
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@ -312,4 +312,4 @@
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* Public Functions
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****************************************************************************************/
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM_PMC_H */
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#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_PMC_H */
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@ -107,7 +107,7 @@
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#define SAM_USART_VERSION(n) (SAM_USARTN_BASE(n)+SAM_UART_VERSION_OFFSET)
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#define SAM_USART0_CR (SAM_USART0_BASE+SAM_UART_CR_OFFSET)
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#define SAM_USART0_MR_ (SAM_USART0_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART0_MR (SAM_USART0_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART0_IER (SAM_USART0_BASE+SAM_UART_IER_OFFSET)
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#define SAM_USART0_IDR (SAM_USART0_BASE+SAM_UART_IDR_OFFSET)
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#define SAM_USART0_IMR (SAM_USART0_BASE+SAM_UART_IMR_OFFSET)
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@ -126,7 +126,7 @@
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#define SAM_USART0_VERSION (SAM_USART0_BASE+SAM_UART_VERSION_OFFSET)
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#define SAM_USART1_CR (SAM_USART1_BASE+SAM_UART_CR_OFFSET)
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#define SAM_USART1_MR_ (SAM_USART1_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART1_MR (SAM_USART1_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART1_IER (SAM_USART1_BASE+SAM_UART_IER_OFFSET)
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#define SAM_USART1_IDR (SAM_USART1_BASE+SAM_UART_IDR_OFFSET)
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#define SAM_USART1_IMR (SAM_USART1_BASE+SAM_UART_IMR_OFFSET)
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@ -145,7 +145,7 @@
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#define SAM_USART1_VERSION (SAM_USART1_BASE+SAM_UART_VERSION_OFFSET)
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#define SAM_USART2_CR (SAM_USART2_BASE+SAM_UART_CR_OFFSET)
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#define SAM_USART2_MR_ (SAM_USART2_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART2_MR (SAM_USART2_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART2_IER (SAM_USART2_BASE+SAM_UART_IER_OFFSET)
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#define SAM_USART2_IDR (SAM_USART2_BASE+SAM_UART_IDR_OFFSET)
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#define SAM_USART2_IMR (SAM_USART2_BASE+SAM_UART_IMR_OFFSET)
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@ -164,7 +164,7 @@
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#define SAM_USART2_VERSION (SAM_USART2_BASE+SAM_UART_VERSION_OFFSET)
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#define SAM_USART3_CR (SAM_USART3_BASE+SAM_UART_CR_OFFSET)
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#define SAM_USART3_MR_ (SAM_USART3_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART3_MR (SAM_USART3_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART3_IER (SAM_USART3_BASE+SAM_UART_IER_OFFSET)
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#define SAM_USART3_IDR (SAM_USART3_BASE+SAM_UART_IDR_OFFSET)
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#define SAM_USART3_IMR (SAM_USART3_BASE+SAM_UART_IMR_OFFSET)
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@ -103,7 +103,7 @@
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#define SAM_USART_VERSION(n) (SAM_USARTN_BASE(n)+SAM_UART_VERSION_OFFSET)
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#define SAM_USART0_CR (SAM_USART0_BASE+SAM_UART_CR_OFFSET)
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#define SAM_USART0_MR_ (SAM_USART0_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART0_MR (SAM_USART0_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART0_IER (SAM_USART0_BASE+SAM_UART_IER_OFFSET)
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#define SAM_USART0_IDR (SAM_USART0_BASE+SAM_UART_IDR_OFFSET)
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#define SAM_USART0_IMR (SAM_USART0_BASE+SAM_UART_IMR_OFFSET)
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@ -125,7 +125,7 @@
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#define SAM_USART0_VERSION (SAM_USART0_BASE+SAM_UART_VERSION_OFFSET)
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#define SAM_USART1_CR (SAM_USART1_BASE+SAM_UART_CR_OFFSET)
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#define SAM_USART1_MR_ (SAM_USART1_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART1_MR (SAM_USART1_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART1_IER (SAM_USART1_BASE+SAM_UART_IER_OFFSET)
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#define SAM_USART1_IDR (SAM_USART1_BASE+SAM_UART_IDR_OFFSET)
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#define SAM_USART1_IMR (SAM_USART1_BASE+SAM_UART_IMR_OFFSET)
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@ -147,7 +147,7 @@
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#define SAM_USART1_VERSION (SAM_USART1_BASE+SAM_UART_VERSION_OFFSET)
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#define SAM_USART2_CR (SAM_USART2_BASE+SAM_UART_CR_OFFSET)
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#define SAM_USART2_MR_ (SAM_USART2_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART2_MR (SAM_USART2_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART2_IER (SAM_USART2_BASE+SAM_UART_IER_OFFSET)
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#define SAM_USART2_IDR (SAM_USART2_BASE+SAM_UART_IDR_OFFSET)
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#define SAM_USART2_IMR (SAM_USART2_BASE+SAM_UART_IMR_OFFSET)
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@ -169,7 +169,7 @@
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#define SAM_USART2_VERSION (SAM_USART2_BASE+SAM_UART_VERSION_OFFSET)
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#define SAM_USART3_CR (SAM_USART3_BASE+SAM_UART_CR_OFFSET)
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#define SAM_USART3_MR_ (SAM_USART3_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART3_MR (SAM_USART3_BASE+SAM_UART_MR_OFFSET)
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#define SAM_USART3_IER (SAM_USART3_BASE+SAM_UART_IER_OFFSET)
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#define SAM_USART3_IDR (SAM_USART3_BASE+SAM_UART_IDR_OFFSET)
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#define SAM_USART3_IMR (SAM_USART3_BASE+SAM_UART_IMR_OFFSET)
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@ -231,9 +231,9 @@
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# define UART_MR_MODE_SPISLV (15 << UART_MR_MODE_SHIFT) /* SPI Slave */
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#define UART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection */
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#define UART_MR_USCLKS_MASK (3 << UART_MR_USCLKS_SHIFT)
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# define UART_MR_USCLKS_MCK (0 << UART_MR_USCLKS_SHIFT) /* MCK */
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# define UART_MR_USCLKS_MCKDIV (1 << UART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */
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# define UART_MR_USCLKS_SCK (3 << UART_MR_USCLKS_SHIFT) /* SCK */
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# define UART_MR_USCLKS_USART (0 << UART_MR_USCLKS_SHIFT) /* CLK_USART */
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# define UART_MR_USCLKS_USARTDIV (0 << UART_MR_USCLKS_SHIFT) /* CLK_USART/DIV(1) */
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# define UART_MR_USCLKS_CLK (0 << UART_MR_USCLKS_SHIFT) /* CLK */
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#define UART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length */
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#define UART_MR_CHRL_MASK (3 << UART_MR_CHRL_SHIFT)
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# define UART_MR_CHRL_5BITS (0 << UART_MR_CHRL_SHIFT) /* 5 bits */
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@ -49,7 +49,7 @@
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#include "up_internal.h"
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#include "sam_clockconfig.h"
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#include "chip/sam_pmc.h"
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#include "chip/sam3u_pmc.h"
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#include "chip/sam3u_eefc.h"
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#include "chip/sam3u_wdt.h"
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#include "chip/sam3u_supc.h"
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149
arch/arm/src/sam34/sam3u_periphclks.h
Normal file
149
arch/arm/src/sam34/sam3u_periphclks.h
Normal file
@ -0,0 +1,149 @@
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/************************************************************************************
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* arch/arm/src/sam34/sam3u_periphclks.h
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*
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* Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H
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#define __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <arch/irq.h>
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#include "chip/sam3u_pmc.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Helper macros */
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#define sam_enableperipheral(s) putreg32((1 << (s)), SAM_PMC_PCER)
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#define sam_disableperipheral(s) putreg32((1 << (s)), SAM_PMC_PDER)
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#define sam_supc_enableclk() sam_enableperipheral(SAM_PID_SUPC)
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#define sam_rstc_enableclk() sam_enableperipheral(SAM_PID_RSTC)
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#define sam_rtc_enableclk() sam_enableperipheral(SAM_PID_RTC)
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#define sam_rtt_enableclk() sam_enableperipheral(SAM_PID_RTT)
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#define sam_wdt_enableclk() sam_enableperipheral(SAM_PID_WDT)
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#define sam_pmc_enableclk() sam_enableperipheral(SAM_PID_PMC)
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#define sam_eefc0_enableclk() sam_enableperipheral(SAM_PID_EEFC0)
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#define sam_eefc1_enableclk() sam_enableperipheral(SAM_PID_EEFC1)
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#define sam_uart_enableclk() sam_enableperipheral(SAM_PID_UART)
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#define sam_smc_enableclk() sam_enableperipheral(SAM_PID_SMC)
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#define sam_pioa_enableclk() sam_enableperipheral(SAM_PID_PIOA)
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#define sam_piob_enableclk() sam_enableperipheral(SAM_PID_PIOB)
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#define sam_pioc_enableclk() sam_enableperipheral(SAM_PID_PIOC)
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#define sam_usart0_enableclk() sam_enableperipheral(SAM_PID_USART0)
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#define sam_usart1_enableclk() sam_enableperipheral(SAM_PID_USART1)
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#define sam_usart2_enableclk() sam_enableperipheral(SAM_PID_USART2)
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#define sam_usart3_enableclk() sam_enableperipheral(SAM_PID_USART3)
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#define sam_hsmci_enableclk() sam_enableperipheral(SAM_PID_HSMCI)
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#define sam_twi0_enableclk() sam_enableperipheral(SAM_PID_TWI0)
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#define sam_twi1_enableclk() sam_enableperipheral(SAM_PID_TWI1)
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#define sam_spi_enableclk() sam_enableperipheral(SAM_PID_SPI)
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#define sam_ssc_enableclk() sam_enableperipheral(SAM_PID_SSC)
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#define sam_tc0_enableclk() sam_enableperipheral(SAM_PID_TC0)
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#define sam_tc1_enableclk() sam_enableperipheral(SAM_PID_TC1)
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#define sam_tc2_enableclk() sam_enableperipheral(SAM_PID_TC2)
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#define sam_pwm_enableclk() sam_enableperipheral(SAM_PID_PWM)
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#define sam_adc12b_enableclk() sam_enableperipheral(SAM_PID_ADC12B)
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#define sam_dmac_enableclk() sam_enableperipheral(SAM_PID_DMAC)
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#define sam_udphs_enableclk() sam_enableperipheral(SAM_PID_UDPHS)
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#define sam_supc_disableclk() sam_disableperipheral(SAM_PID_SUPC)
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#define sam_rstc_disableclk() sam_disableperipheral(SAM_PID_RSTC)
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#define sam_rtc_disableclk() sam_disableperipheral(SAM_PID_RTC)
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#define sam_rtt_disableclk() sam_disableperipheral(SAM_PID_RTT)
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#define sam_wdt_disableclk() sam_disableperipheral(SAM_PID_WDT)
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#define sam_pmc_disableclk() sam_disableperipheral(SAM_PID_PMC)
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#define sam_eefc0_disableclk() sam_disableperipheral(SAM_PID_EEFC0)
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#define sam_eefc1_disableclk() sam_disableperipheral(SAM_PID_EEFC1)
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#define sam_uart_disableclk() sam_disableperipheral(SAM_PID_UART)
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#define sam_smc_disableclk() sam_disableperipheral(SAM_PID_SMC)
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#define sam_pioa_disableclk() sam_disableperipheral(SAM_PID_PIOA)
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#define sam_piob_disableclk() sam_disableperipheral(SAM_PID_PIOB)
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#define sam_pioc_disableclk() sam_disableperipheral(SAM_PID_PIOC)
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#define sam_usart0_disableclk() sam_disableperipheral(SAM_PID_USART0)
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#define sam_usart1_disableclk() sam_disableperipheral(SAM_PID_USART1)
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#define sam_usart2_disableclk() sam_disableperipheral(SAM_PID_USART2)
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#define sam_usart3_disableclk() sam_disableperipheral(SAM_PID_USART3)
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#define sam_hsmci_disableclk() sam_disableperipheral(SAM_PID_HSMCI)
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#define sam_twi0_disableclk() sam_disableperipheral(SAM_PID_TWI0)
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#define sam_twi1_disableclk() sam_disableperipheral(SAM_PID_TWI1)
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#define sam_spi_disableclk() sam_disableperipheral(SAM_PID_SPI)
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#define sam_ssc_disableclk() sam_disableperipheral(SAM_PID_SSC)
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#define sam_tc0_disableclk() sam_disableperipheral(SAM_PID_TC0)
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#define sam_tc1_disableclk() sam_disableperipheral(SAM_PID_TC1)
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#define sam_tc2_disableclk() sam_disableperipheral(SAM_PID_TC2)
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#define sam_pwm_disableclk() sam_disableperipheral(SAM_PID_PWM)
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#define sam_adc12b_disableclk() sam_disableperipheral(SAM_PID_ADC12B)
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#define sam_dmac_disableclk() sam_disableperipheral(SAM_PID_DMAC)
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#define sam_udphs_disableclk() sam_disableperipheral(SAM_PID_UDPHS)
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Inline Functions
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************************************************************************************/
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#ifndef __ASSEMBLY__
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H */
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@ -105,8 +105,10 @@ static inline void sam_init_cpumask(void)
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/* OR in the user selected peripherals */
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#ifdef CONFIG_SAM32_RESET_PERIPHCLKS
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#ifdef CONFIG_SAM34_OCD
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mask |= PM_CPUMASK_OCD; /* On-Chip Debug */
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#endif
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#endif
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/* Save the new CPU mask */
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@ -134,6 +136,7 @@ static inline void sam_init_hsbmask(void)
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/* OR in the user selected peripherals */
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#ifdef CONFIG_SAM32_RESET_PERIPHCLKS
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#ifdef CONFIG_SAM34_PDCA
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mask |= PM_HSBMASK_PDCA; /* PDCA */
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#endif
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@ -151,6 +154,7 @@ static inline void sam_init_hsbmask(void)
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#endif
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#ifdef CONFIG_SAM34_AESA
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mask |= PM_HSBMASK_AESA; /* AESA */
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#endif
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#endif
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/* Save the new HSB mask */
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@ -178,6 +182,7 @@ static inline void sam_init_pbamask(void)
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/* OR in the user selected peripherals */
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#ifdef CONFIG_SAM32_RESET_PERIPHCLKS
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#ifdef CONFIG_SAM34_IISC
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mask |= PM_PBAMASK_IISC; /* IISC */
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#endif
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@ -252,6 +257,7 @@ static inline void sam_init_pbamask(void)
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#endif
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#ifdef CONFIG_SAM34_LCDCA
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mask |= PM_PBAMASK_LCDCA; /* LCDCA*/
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#endif
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#endif
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/* Save the new PBA mask */
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@ -284,6 +290,7 @@ static inline void sam_init_pbbmask(void)
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/* OR in the user selected peripherals */
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#ifdef CONFIG_SAM32_RESET_PERIPHCLKS
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#ifdef CONFIG_SAM34_HRAMC1
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mask |= PM_PBBMASK_HRAMC1; /* HRAMC1 */
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#endif
|
||||
@ -301,6 +308,7 @@ static inline void sam_init_pbbmask(void)
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_PEVC
|
||||
mask |= PM_PBBMASK_PEVC; /* PEVC */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Save the new PBB mask */
|
||||
@ -327,11 +335,13 @@ static inline void sam_init_pbcmask(void)
|
||||
|
||||
/* OR in the user selected peripherals */
|
||||
|
||||
#ifdef CONFIG_SAM32_RESET_PERIPHCLKS
|
||||
#ifdef CONFIG_SAM34_CHIPID
|
||||
mask |= PM_PBCMASK_CHIPID; /* CHIPID */
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_FREQM
|
||||
mask |= PM_PBCMASK_FREQM; /* FREQM */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Save the new PBC mask */
|
||||
@ -358,6 +368,7 @@ static inline void sam_init_pbdmask(void)
|
||||
|
||||
/* OR in the user selected peripherals */
|
||||
|
||||
#ifdef CONFIG_SAM32_RESET_PERIPHCLKS
|
||||
#ifdef CONFIG_SAM34_AST
|
||||
mask |= PM_PBDMASK_AST; /* AST */
|
||||
#endif
|
||||
@ -369,6 +380,7 @@ static inline void sam_init_pbdmask(void)
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_PICOUART
|
||||
mask |= PM_PBDMASK_PICOUART; /* PICOUART */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Save the new PBD mask */
|
||||
|
||||
@ -42,6 +42,8 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip/sam4l_pm.h"
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4L
|
||||
|
||||
/************************************************************************************
|
||||
@ -92,13 +94,13 @@
|
||||
#define sam_usart0_enableclk() \
|
||||
do { \
|
||||
sam_pba_enableperipheral(PM_PBAMASK_USART0); \
|
||||
sam_pba_enabledivmask(PBA_DIVMASK_CLK_USART); \
|
||||
sam_pba_enabledivmask(PM_PBADIVMASK_CLK_USART); \
|
||||
} while (0)
|
||||
|
||||
#define sam_usart1_enableclk() \
|
||||
do { \
|
||||
sam_pba_enableperipheral(PM_PBAMASK_USART1); \
|
||||
sam_pba_enabledivmask(PBA_DIVMASK_CLK_USART); \
|
||||
sam_pba_enabledivmask(PM_PBADIVMASK_CLK_USART); \
|
||||
} while (0)
|
||||
|
||||
#define sam_usart2_enableclk() \
|
||||
|
||||
@ -56,7 +56,7 @@
|
||||
#include "chip.h"
|
||||
|
||||
#include "sam_dmac.h"
|
||||
#include "chip/sam_pmc.h"
|
||||
#include "chip/sam3u_pmc.h"
|
||||
#include "chip/sam_dmac.h"
|
||||
|
||||
/****************************************************************************
|
||||
@ -1160,7 +1160,7 @@ void weak_function up_dmainitialize(void)
|
||||
{
|
||||
/* Enable peripheral clock */
|
||||
|
||||
putreg32((1 << SAM_PID_DMAC), SAM_PMC_PCER);
|
||||
sam_dmac_enableclk();
|
||||
|
||||
/* Disable all DMA interrupts */
|
||||
|
||||
|
||||
@ -55,7 +55,7 @@
|
||||
|
||||
#include "sam_gpio.h"
|
||||
#include "chip/sam3u_pio.h"
|
||||
#include "chip/sam_pmc.h"
|
||||
#include "chip/sam3u_pmc.h"
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
|
||||
@ -209,15 +209,12 @@ static int up_gpiocinterrupt(int irq, void *context)
|
||||
|
||||
void sam_gpioirqinitialize(void)
|
||||
{
|
||||
uint32_t pcer;
|
||||
|
||||
/* Configure GPIOA interrupts */
|
||||
|
||||
#ifdef CONFIG_GPIOA_IRQ
|
||||
/* Enable GPIOA clocking */
|
||||
|
||||
pcer |= (1 << SAM_PID_PIOA);
|
||||
putreg32(pcer, SAM_PMC_PCER);
|
||||
sam_pioa_enableclk();
|
||||
|
||||
/* Clear and disable all GPIOA interrupts */
|
||||
|
||||
@ -235,8 +232,7 @@ void sam_gpioirqinitialize(void)
|
||||
#ifdef CONFIG_GPIOB_IRQ
|
||||
/* Enable GPIOB clocking */
|
||||
|
||||
pcer |= (1 << SAM_PID_PIOB);
|
||||
putreg32(pcer, SAM_PMC_PCER);
|
||||
sam_piob_enableclk();
|
||||
|
||||
/* Clear and disable all GPIOB interrupts */
|
||||
|
||||
@ -254,8 +250,7 @@ void sam_gpioirqinitialize(void)
|
||||
#ifdef CONFIG_GPIOC_IRQ
|
||||
/* Enable GPIOC clocking */
|
||||
|
||||
pcer |= (1 << SAM_PID_PIOC);
|
||||
putreg32(pcer, SAM_PMC_PCER);
|
||||
sam_pioc_enableclk();
|
||||
|
||||
/* Clear and disable all GPIOC interrupts */
|
||||
|
||||
|
||||
@ -64,7 +64,7 @@
|
||||
#include "sam_dmac.h"
|
||||
#include "sam_hsmci.h"
|
||||
#include "chip/sam_dmac.h"
|
||||
#include "chip/sam_pmc.h"
|
||||
#include "chip/sam3u_pmc.h"
|
||||
#include "chip/sam_hsmci.h"
|
||||
#include "chip/sam_pinmap.h"
|
||||
|
||||
@ -667,7 +667,7 @@ static inline void sam_enable(void)
|
||||
{
|
||||
/* Enable the MCI peripheral clock */
|
||||
|
||||
putreg32((1 << SAM_PID_HSMCI), SAM_PMC_PCER);
|
||||
sam_hsmci_enableclk();
|
||||
|
||||
/* Enable the MCI and the Power Saving */
|
||||
|
||||
@ -1223,7 +1223,7 @@ static void sam_reset(FAR struct sdio_dev_s *dev)
|
||||
/* Enable the MCI clock */
|
||||
|
||||
flags = irqsave();
|
||||
putreg32((1 << SAM_PID_HSMCI), SAM_PMC_PCER);
|
||||
sam_hsmci_enableclk();
|
||||
fdbg("PCSR: %08x\n", getreg32(SAM_PMC_PCSR));
|
||||
|
||||
/* Reset the MCI */
|
||||
|
||||
@ -49,12 +49,13 @@
|
||||
|
||||
#include "sam_gpio.h"
|
||||
#include "sam_lowputc.h"
|
||||
#include "chip/sam_pmc.h"
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
# include "chip/sam3u_uart.h"
|
||||
# include "sam3u_periphclks.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
# include "chip/sam4l_usart.h"
|
||||
# include "sam4l_periphclks.h"
|
||||
#else
|
||||
# error Unknown UART
|
||||
#endif
|
||||
@ -125,6 +126,23 @@
|
||||
# undef HAVE_CONSOLE
|
||||
#endif
|
||||
|
||||
/* Select MCU-specific settings
|
||||
*
|
||||
* For the SAM3U, the USARTs are driven by the main clock.
|
||||
* For the SAM4L, the USARTs are driven by CLK_USART (undivided) which is
|
||||
* selected by the PBADIVMASK register.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */
|
||||
# define SAM_USART_CLOCK SAM_MCK_FREQUENCY /* Frequency of the main clock */
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
# define SAM_MR_USCLKS UART_MR_USCLKS_USART /* Source = USART_CLK (undefined) */
|
||||
# define SAM_USART_CLOCK BOARD_PBA_FREQUENCY /* PBA frequency is undivided */
|
||||
#else
|
||||
# error Unrecognized SAM architecture
|
||||
#endif
|
||||
|
||||
/* Select USART parameters for the selected console */
|
||||
|
||||
#if defined(CONFIG_UART_SERIAL_CONSOLE)
|
||||
@ -191,7 +209,7 @@
|
||||
# define MR_NBSTOP_VALUE UART_MR_NBSTOP_1
|
||||
#endif
|
||||
|
||||
#define MR_VALUE (UART_MR_MODE_NORMAL | UART_MR_USCLKS_MCK | \
|
||||
#define MR_VALUE (UART_MR_MODE_NORMAL | SAM_MR_USCLKS | \
|
||||
MR_CHRL_VALUE | MR_PAR_VALUE | MR_NBSTOP_VALUE)
|
||||
|
||||
/**************************************************************************
|
||||
@ -249,27 +267,23 @@ void up_lowputc(char ch)
|
||||
|
||||
void sam_lowsetup(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Enable clocking for all selected UART/USARTs */
|
||||
|
||||
regval = 0;
|
||||
#ifdef CONFIG_SAM34_UART
|
||||
regval |= (1 << SAM_PID_UART);
|
||||
sam_uart_enableclk();
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_USART0
|
||||
regval |= (1 << SAM_PID_USART0);
|
||||
sam_usart0_enableclk();
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_USART1
|
||||
regval |= (1 << SAM_PID_USART1);
|
||||
sam_usart1_enableclk();
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_USART2
|
||||
regval |= (1 << SAM_PID_USART2);
|
||||
sam_usart2_enableclk();
|
||||
#endif
|
||||
#ifdef CONFIG_SAM34_USART3
|
||||
regval |= (1 << SAM_PID_USART3);
|
||||
sam_usart3_enableclk();
|
||||
#endif
|
||||
putreg32(regval, SAM_PMC_PCER);
|
||||
|
||||
/* Configure UART pins for all selected UART/USARTs */
|
||||
|
||||
@ -277,41 +291,49 @@ void sam_lowsetup(void)
|
||||
(void)sam_configgpio(GPIO_UART_RXD);
|
||||
(void)sam_configgpio(GPIO_UART_TXD);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAM34_USART0
|
||||
(void)sam_configgpio(GPIO_USART0_RXD);
|
||||
(void)sam_configgpio(GPIO_USART0_TXD);
|
||||
#ifdef CONFIG_USART0_OFLOWCONTROL
|
||||
(void)sam_configgpio(GPIO_USART0_CTS);
|
||||
#endif
|
||||
#ifdef CONFIG_USART0_IFLOWCONTROL
|
||||
(void)sam_configgpio(GPIO_USART0_RTS);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAM34_USART1
|
||||
(void)sam_configgpio(GPIO_USART1_RXD);
|
||||
(void)sam_configgpio(GPIO_USART1_TXD);
|
||||
#ifdef CONFIG_USART1_OFLOWCONTROL
|
||||
(void)sam_configgpio(GPIO_USART1_CTS);
|
||||
#endif
|
||||
#ifdef CONFIG_USART1_IFLOWCONTROL
|
||||
(void)sam_configgpio(GPIO_USART1_RTS);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAM34_USART2
|
||||
(void)sam_configgpio(GPIO_USART2_RXD);
|
||||
(void)sam_configgpio(GPIO_USART2_TXD);
|
||||
#ifdef CONFIG_USART2_OFLOWCONTROL
|
||||
(void)sam_configgpio(GPIO_USART2_CTS);
|
||||
#endif
|
||||
#ifdef CONFIG_USART2_IFLOWCONTROL
|
||||
(void)sam_configgpio(GPIO_USART2_RTS);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAM34_USART3
|
||||
(void)sam_configgpio(GPIO_USART3_RXD);
|
||||
(void)sam_configgpio(GPIO_USART3_TXD);
|
||||
#ifdef CONFIG_USART3_OFLOWCONTROL
|
||||
(void)sam_configgpio(GPIO_USART3_CTS);
|
||||
#endif
|
||||
#ifdef CONFIG_USART3_IFLOWCONTROL
|
||||
(void)sam_configgpio(GPIO_USART3_RTS);
|
||||
#endif
|
||||
|
||||
#ifdef GPIO_CONSOLE_RXD
|
||||
#endif
|
||||
#ifdef GPIO_CONSOLE_TXD
|
||||
(void)sam_configgpio(GPIO_CONSOLE_TXD);
|
||||
#endif
|
||||
#ifdef GPIO_CONSOLE_CTS
|
||||
(void)sam_configgpio(GPIO_CONSOLE_CTS);
|
||||
#endif
|
||||
#ifdef GPIO_CONSOLE_RTS
|
||||
(void)sam_configgpio(GPIO_CONSOLE_RTS);
|
||||
#endif
|
||||
|
||||
/* Configure the console (only) */
|
||||
@ -331,7 +353,7 @@ void sam_lowsetup(void)
|
||||
|
||||
/* Configure the console baud */
|
||||
|
||||
putreg32(((SAM_MCK_FREQUENCY + (SAM_CONSOLE_BAUD << 3))/(SAM_CONSOLE_BAUD << 4)),
|
||||
putreg32(((SAM_USART_CLOCK + (SAM_CONSOLE_BAUD << 3)) / (SAM_CONSOLE_BAUD << 4)),
|
||||
SAM_CONSOLE_BASE + SAM_UART_BRGR_OFFSET);
|
||||
|
||||
/* Enable receiver & transmitter */
|
||||
|
||||
@ -551,6 +551,23 @@
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/* Select MCU-specific settings
|
||||
*
|
||||
* For the SAM3U, the USARTs are driven by the main clock.
|
||||
* For the SAM4L, the USARTs are driven by CLK_USART (undivided) which is
|
||||
* selected by the PBADIVMASK register.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
# define SAM_MR_USCLKS UART_MR_USCLKS_MCK /* Source = Main clock */
|
||||
# define SAM_USART_CLOCK SAM_MCK_FREQUENCY /* Frequency of the main clock */
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
# define SAM_MR_USCLKS UART_MR_USCLKS_USART /* Source = USART_CLK (undefined) */
|
||||
# define SAM_USART_CLOCK BOARD_PBA_FREQUENCY /* PBA frequency is undivided */
|
||||
#else
|
||||
# error Unrecognized SAM architecture
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
@ -879,7 +896,7 @@ static int up_setup(struct uart_dev_s *dev)
|
||||
* as the timing source
|
||||
*/
|
||||
|
||||
regval = (UART_MR_MODE_NORMAL | UART_MR_USCLKS_MCK);
|
||||
regval = (UART_MR_MODE_NORMAL | SAM_MR_USCLKS);
|
||||
|
||||
/* OR in settings for the selected number of bits */
|
||||
|
||||
@ -944,7 +961,7 @@ static int up_setup(struct uart_dev_s *dev)
|
||||
|
||||
/* Configure the console baud */
|
||||
|
||||
regval = (SAM_MCK_FREQUENCY + (priv->baud << 3))/(priv->baud << 4);
|
||||
regval = (SAM_USART_CLOCK + (priv->baud << 3))/(priv->baud << 4);
|
||||
up_serialout(priv, SAM_UART_BRGR_OFFSET, regval);
|
||||
|
||||
/* Enable receiver & transmitter */
|
||||
|
||||
@ -57,7 +57,7 @@
|
||||
#include "chip.h"
|
||||
#include "sam_gpio.h"
|
||||
#include "sam_spi.h"
|
||||
#include "chip/sam_pmc.h"
|
||||
#include "chip/sam3u_pmc.h"
|
||||
#include "chip/sam_spi.h"
|
||||
#include "chip/sam_pinmap.h"
|
||||
|
||||
@ -66,6 +66,19 @@
|
||||
/****************************************************************************
|
||||
* Definitions
|
||||
****************************************************************************/
|
||||
/* Select MCU-specific settings
|
||||
*
|
||||
* For the SAM3U, SPI is driven by the main clock.
|
||||
* For the SAM4L, SPI driven by CLK_SPI which is the PBB clock.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
# define SAM_SPI_CLOCK SAM_MCK_FREQUENCY /* Frequency of the main clock */
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
# define SAM_SPI_CLOCK BOARD_PBB_FREQUENCY /* PBA frequency */
|
||||
#else
|
||||
# error Unrecognized SAM architecture
|
||||
#endif
|
||||
|
||||
/* Check if SPI debut is enabled (non-standard.. no support in
|
||||
* include/debug.h
|
||||
@ -461,7 +474,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
|
||||
* SPCK frequency = MCK / SCBR, or SCBR = MCK / frequency
|
||||
*/
|
||||
|
||||
scbr = SAM_MCK_FREQUENCY / frequency;
|
||||
scbr = SAM_SPI_CLOCK / frequency;
|
||||
|
||||
if (scbr < 8)
|
||||
{
|
||||
@ -493,7 +506,7 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
|
||||
* DLYBS = MCK * 0.000002 = MCK / 500000
|
||||
*/
|
||||
|
||||
dlybs = SAM_MCK_FREQUENCY / 500000;
|
||||
dlybs = SAM_SPI_CLOCK / 500000;
|
||||
regval |= dlybs << SPI_CSR_DLYBS_SHIFT;
|
||||
|
||||
/* DLYBCT: Delay Between Consecutive Transfers. This field defines the delay
|
||||
@ -508,13 +521,13 @@ static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
|
||||
* DLYBCT = MCK * 0.000005 / 32 = MCK / 200000 / 32
|
||||
*/
|
||||
|
||||
dlybct = SAM_MCK_FREQUENCY / 200000 / 32;
|
||||
dlybct = SAM_SPI_CLOCK / 200000 / 32;
|
||||
regval |= dlybct << SPI_CSR_DLYBCT_SHIFT;
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
/* Calculate the new actual frequency */
|
||||
|
||||
actual = SAM_MCK_FREQUENCY / scbr;
|
||||
actual = SAM_SPI_CLOCK / scbr;
|
||||
spivdbg("csr[%08x]=%08x actual=%d\n", regaddr, regval, actual);
|
||||
|
||||
/* Save the frequency setting */
|
||||
@ -897,15 +910,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
|
||||
priv->cs = 0xff;
|
||||
|
||||
/* Apply power to the SPI block */
|
||||
/* Enable clocking to the SPI block */
|
||||
|
||||
flags = irqsave();
|
||||
regval = getreg32(SAM_PMC_PCER);
|
||||
regval |= (1 << SAM_PID_SPI);
|
||||
#ifdef CONFIG_SAM34_SPIINTERRUPT
|
||||
regval |= (1 << SAM_IRQ_SPI);
|
||||
#endif
|
||||
putreg32(regval, SAM_PMC_PCER);
|
||||
sam_spi_enableclk();
|
||||
|
||||
/* Configure multiplexed pins as connected on the board. Chip select pins
|
||||
* must be configured by board-specific logic.
|
||||
|
||||
@ -55,6 +55,20 @@
|
||||
/****************************************************************************
|
||||
* Definitions
|
||||
****************************************************************************/
|
||||
/* Select MCU-specific settings
|
||||
*
|
||||
* For the SAM3U, Systick is driven by the main clock.
|
||||
* For the SAM4L, Systick is driven by the CPU clock which is just the main
|
||||
* clock divided down.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_SAM3U)
|
||||
# define SAM_SYSTICK_CLOCK SAM_MCK_FREQUENCY /* Frequency of the main clock */
|
||||
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
|
||||
# define SAM_SYSTICK_CLOCK BOARD_CPU_FREQUENCY /* PBA frequency is undivided */
|
||||
#else
|
||||
# error Unrecognized SAM architecture
|
||||
#endif
|
||||
|
||||
/* The desired timer interrupt frequency is provided by the definition
|
||||
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
|
||||
@ -69,9 +83,9 @@
|
||||
#undef CONFIG_SAM34_SYSTICK_HCLKd8 /* Power up default is MCK, not MCK/8 */
|
||||
|
||||
#if CONFIG_SAM34_SYSTICK_HCLKd8
|
||||
# define SYSTICK_RELOAD ((SAM_MCK_FREQUENCY / 8 / CLK_TCK) - 1)
|
||||
# define SYSTICK_RELOAD ((SAM_SYSTICK_CLOCK / 8 / CLK_TCK) - 1)
|
||||
#else
|
||||
# define SYSTICK_RELOAD ((SAM_MCK_FREQUENCY / CLK_TCK) - 1)
|
||||
# define SYSTICK_RELOAD ((SAM_SYSTICK_CLOCK / CLK_TCK) - 1)
|
||||
#endif
|
||||
|
||||
/* The size of the reload field is 24 bits. Verify that the reload value
|
||||
|
||||
@ -165,6 +165,7 @@ CONFIG_SAM34_USART1=y
|
||||
# CONFIG_SAM34_AST is not set
|
||||
# CONFIG_SAM34_WDT is not set
|
||||
# CONFIG_SAM34_EIC is not set
|
||||
# CONFIG_SAM32_RESET_PERIPHCLKS is not set
|
||||
|
||||
#
|
||||
# AT91SAM3/4 USART Configuration
|
||||
|
||||
@ -80,7 +80,7 @@
|
||||
* 2Hz, then a fatal error has been detected and the system has halted.
|
||||
*/
|
||||
|
||||
#define GPIO_LED0 (GPIO_OUTPUT | GPIO_PULL_NONE GPIO_OUTPUT_SET | \
|
||||
#define GPIO_LED0 (GPIO_OUTPUT | GPIO_PULL_NONE | GPIO_OUTPUT_SET | \
|
||||
GPIO_PORTC | GPIO_PIN7)
|
||||
|
||||
/* QTouch button: The SAM4L Xplained Pro kit has one QTouch button. The connection
|
||||
|
||||
@ -123,19 +123,19 @@ void up_ledon(int led)
|
||||
|
||||
switch (led)
|
||||
{
|
||||
case LED_STARTED : /* NuttX has been started LED0=OFF */
|
||||
case LED_HEAPALLOCATE: /* Heap has been allocated LED0=OFF */
|
||||
case LED_IRQSENABLED: /* Interrupts enabled LED0=OFF */
|
||||
case 0: /* LED_STARTED: NuttX has been started LED0=OFF */
|
||||
/* LED_HEAPALLOCATE: Heap has been allocated LED0=OFF */
|
||||
/* LED_IRQSENABLED: Interrupts enabled LED0=OFF */
|
||||
break; /* Leave ledstate == true to turn OFF */
|
||||
|
||||
default:
|
||||
case LED_INIRQ: /* In an interrupt LED0=N/C */
|
||||
case LED_SIGNAL: /* In a signal handler LED0=N/C */
|
||||
case LED_ASSERTION: /* An assertion failed LED0=N/C */
|
||||
return;
|
||||
case 2: /* LED_INIRQ: In an interrupt LED0=N/C */
|
||||
/* LED_SIGNAL: In a signal handler LED0=N/C */
|
||||
/* LED_ASSERTION: An assertion failed LED0=N/C */
|
||||
return; /* Return to leave LED0 unchanged */
|
||||
|
||||
case LED_PANIC: /* The system has crashed LED0=FLASH */
|
||||
case LED_STACKCREATED: /* Idle stack created LED0=ON */
|
||||
case 3: /* LED_PANIC: The system has crashed LED0=FLASH */
|
||||
case 1: /* LED_STACKCREATED: Idle stack created LED0=ON */
|
||||
ledstate = false; /* Set ledstate == false to turn ON */
|
||||
break;
|
||||
}
|
||||
@ -154,21 +154,21 @@ void up_ledoff(int led)
|
||||
/* These should not happen and are ignored */
|
||||
|
||||
default:
|
||||
case LED_STARTED : /* NuttX has been started LED0=OFF */
|
||||
case LED_HEAPALLOCATE: /* Heap has been allocated LED0=OFF */
|
||||
case LED_IRQSENABLED: /* Interrupts enabled LED0=OFF */
|
||||
case LED_STACKCREATED: /* Idle stack created LED0=ON */
|
||||
case 0: /* LED_STARTED: NuttX has been started LED0=OFF */
|
||||
/* LED_HEAPALLOCATE: Heap has been allocated LED0=OFF */
|
||||
/* LED_IRQSENABLED: Interrupts enabled LED0=OFF */
|
||||
case 1: /* LED_STACKCREATED: Idle stack created LED0=ON */
|
||||
|
||||
/* These result in no-change */
|
||||
|
||||
case LED_INIRQ: /* In an interrupt LED0=N/C */
|
||||
case LED_SIGNAL: /* In a signal handler LED0=N/C */
|
||||
case LED_ASSERTION: /* An assertion failed LED0=N/C */
|
||||
return;
|
||||
case 2: /* LED_INIRQ: In an interrupt LED0=N/C */
|
||||
/* LED_SIGNAL: In a signal handler LED0=N/C */
|
||||
/* LED_ASSERTION: An assertion failed LED0=N/C */
|
||||
return; /* Return to leave LED0 unchanged */
|
||||
|
||||
/* Turn LED0 off set driving the output high */
|
||||
|
||||
case LED_PANIC: /* The system has crashed LED0=FLASH */
|
||||
case 3: /* LED_PANIC: The system has crashed LED0=FLASH */
|
||||
sam_gpiowrite(GPIO_LED0, true);
|
||||
break;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user