sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

arch/arm64/src/imx9: Add Ethernet driver

Browse Source 
This adds a driver for i.MX93 ENET1 MAC block

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>
This commit is contained in:
Jukka Laitinen 2024-05-02 16:20:36 +03:00 committed by Alan Carvalho de Assis
parent 9277be2503
commit cc9c3ed80b
7 changed files with 4180 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

113
arch/arm64/src/imx9/Kconfig
View File

@ -316,6 +316,12 @@ endmenu # USB device controller driver (DCD) options
endif # IMX9_USBDEV
config IMX9_ENET
bool "Ethernet"
default n
select ARCH_HAVE_PHY
select ARCH_HAVE_NETDEV_STATISTICS
config IMX9_GPIO_IRQ
bool "GPIO Interrupt Support"
default n
@ -783,6 +789,113 @@ config IMX9_LPSPI8_DMA
endmenu # LPSPI Configuration
menu "Ethernet Configuration"
depends on IMX9_ENET
config IMX9_ENET1
bool "Ethernet MAC (non-QoS)"
depends on IMX9_ENET
default y
config IMX9_ENET_NRXBUFFERS
int "Number of Rx buffers"
default 6
config IMX9_ENET_NTXBUFFERS
int "Number of Tx buffers"
default 2
config IMX9_ENET_USE_OTP_MAC
bool "Use MAC address from OCOTP"
default n
depends on IMX9_ENET
config IMX9_ENET1_OTP_MAC_ADDR
hex "MAC address offset in OCOTP"
default 0x4ec
depends on IMX9_ENET_USE_OTP_MAC
config IMX9_ENET1_PROMISCUOUS
bool "Set promiscuous mode"
depends on IMX9_ENET1
default n
choice
prompt "i.MX9 ENET1 interface type"
default IMX9_ENET1_RMII
depends on IMX9_ENET1
config IMX9_ENET1_RMII
bool "RMII"
config IMX9_ENET1_RGMII
bool "RGMII"
endchoice
config IMX9_ENET1_PHY_AUTONEG
bool "ENET1 PHY autonegotiation enable"
default y
---help---
Enable PHY autonegotiation. If set to n, configure the speed
and duplex mode manually. Note that only disabling this doesn't
disable the autonegotiation completely; it just sets the MAC
speed and duplex, and disables autonegotiation advertisement
for other than the configured mode. To disable autonegotiation
completely, also set the FORCE_SPEED flag.
choice
prompt "Select ENET1 PHY link duplex mode"
default IMX9_ENET1_PHY_FD
depends on !IMX9_ENET1_PHY_AUTONEG
config IMX9_ENET1_PHY_FD
bool "Full Duplex"
config IMX9_ENET1_PHY_HD
bool "Half Duplex"
endchoice
choice
prompt "Select ENET1 PHY link speed"
default IMX9_ENET1_PHY_100MBPS if IMX9_ENET1_RMII
default IMX9_ENET1_PHY_1000MBPS if IMX9_ENET1_RGMII
depends on !IMX9_ENET1_PHY_AUTONEG
config IMX9_ENET1_PHY_10MBPS
bool "10 MBPS"
config IMX9_ENET1_PHY_100MBPS
bool "100 MBPS"
config IMX9_ENET1_PHY_1000MBPS
bool "1000 MBPS"
depends on IMX9_ENET1_RGMII
endchoice
config IMX9_ENET1_PHY_FORCE_SPEED
bool "Disable PHY autonegotiation and force speed and duplex"
depends on !IMX9_ENET1_PHY_AUTONEG
default n
---help---
This disables PHY autonegotiation completely. Note that
if the link partner has got autonegotiation enabled, the
duplex mode is not auto-detected by the link partner. Only
enable if you really know what you are doing!
config IMX9_ENET1_PHYINIT
bool "Board-specific PHY Initialization for ENET1"
default n
---help---
Some boards require specialized initialization of the PHY before it
can be used. This may include such things as configuring GPIOs,
resetting the PHY, etc. If CONFIG_IMX9_ENET_PHYINIT is defined in
the configuration then the board specific logic must provide
imx9_phy_boardinitialize(); The i.MX9 ENET driver will call this
function one time before it first uses the PHY.
endmenu # IMX9_ENET
endmenu # iMX Peripheral Selection
endif # ARCH_CHIP_IMX9

4
arch/arm64/src/imx9/Make.defs
View File

@ -59,3 +59,7 @@ endif
ifeq ($(CONFIG_IMX9_DMA_ALLOC),y)
CHIP_CSRCS += imx9_dma_alloc.c
endif
ifeq ($(CONFIG_IMX9_ENET),y)
CHIP_CSRCS += imx9_enet.c
endif

646
arch/arm64/src/imx9/hardware/imx9_enet.h Normal file
View File

@ -0,0 +1,646 @@
/****************************************************************************
* arch/arm64/src/imx9/hardware/imx9_enet.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_ENET_H
#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_ENET_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define IMX9_ENET_EIR_OFFSET 0x0004 /* Interrupt Event Register */
#define IMX9_ENET_EIMR_OFFSET 0x0008 /* Interrupt Mask Register */
#define IMX9_ENET_RDAR_OFFSET 0x0010 /* Receive Descriptor Active Register */
#define IMX9_ENET_TDAR_OFFSET 0x0014 /* Transmit Descriptor Active Register */
#define IMX9_ENET_ECR_OFFSET 0x0024 /* Ethernet Control Register */
#define IMX9_ENET_MMFR_OFFSET 0x0040 /* MII Management Frame Register */
#define IMX9_ENET_MSCR_OFFSET 0x0044 /* MII Speed Control Register */
#define IMX9_ENET_MIBC_OFFSET 0x0064 /* MIB Control Register */
#define IMX9_ENET_RCR_OFFSET 0x0084 /* Receive Control Register */
#define IMX9_ENET_TCR_OFFSET 0x00c4 /* Transmit Control Register */
#define IMX9_ENET_PALR_OFFSET 0x00e4 /* Physical Address Lower Register */
#define IMX9_ENET_PAUR_OFFSET 0x00e8 /* Physical Address Upper Register */
#define IMX9_ENET_OPD_OFFSET 0x00ec /* Opcode/Pause Duration Register */
#define IMX9_ENET_TXIC_OFFSET 0x00f0 /* Transmit Interrupt Coalescing Register */
#define IMX9_ENET_RXIC_OFFSET 0x0100 /* Receive Interrupt Coalescing Register */
#define IMX9_ENET_IAUR_OFFSET 0x0118 /* Descriptor Individual Upper Address Register */
#define IMX9_ENET_IALR_OFFSET 0x011c /* Descriptor Individual Lower Address Register */
#define IMX9_ENET_GAUR_OFFSET 0x0120 /* Descriptor Group Upper Address Register */
#define IMX9_ENET_GALR_OFFSET 0x0124 /* Descriptor Group Lower Address Register */
#define IMX9_ENET_TFWR_OFFSET 0x0144 /* Transmit FIFO Watermark Register */
#define IMX9_ENET_RDSR1_OFFSET 0x0160 /* Receive Descriptor Ring 1 Start Register */
#define IMX9_ENET_TDSR1_OFFSET 0x0164 /* Transmit Buffer Descriptor Ring 1 Start Register */
#define IMX9_ENET_MRBR1_OFFSET 0x0168 /* Maximum Receive Buffer Size Register - Ring 1 */
#define IMX9_ENET_RDSR2_OFFSET 0x0170 /* Receive Descriptor Ring 2 Start Register */
#define IMX9_ENET_TDSR2_OFFSET 0x0174 /* Transmit Buffer Descriptor Ring 2 Start Register */
#define IMX9_ENET_MRBR2_OFFSET 0x0178 /* Maximum Receive Buffer Size Register - Ring 2 */
#define IMX9_ENET_RDSR_OFFSET 0x0180 /* Receive Descriptor Ring Start Register */
#define IMX9_ENET_TDSR_OFFSET 0x0184 /* Transmit Buffer Descriptor Ring Start Register */
#define IMX9_ENET_MRBR_OFFSET 0x0188 /* Maximum Receive Buffer Size Register */
#define IMX9_ENET_RSFL_OFFSET 0x0190 /* Receive FIFO Section Full Threshold */
#define IMX9_ENET_RSEM_OFFSET 0x0194 /* Receive FIFO Section Empty Threshold */
#define IMX9_ENET_RAEM_OFFSET 0x0198 /* Receive FIFO Almost Empty Threshold */
#define IMX9_ENET_RAFL_OFFSET 0x019c /* Receive FIFO Almost Full Threshold */
#define IMX9_ENET_TSEM_OFFSET 0x01a0 /* Transmit FIFO Section Empty Threshold */
#define IMX9_ENET_TAEM_OFFSET 0x01a4 /* Transmit FIFO Almost Empty Threshold */
#define IMX9_ENET_TAFL_OFFSET 0x01a8 /* Transmit FIFO Almost Full Threshold */
#define IMX9_ENET_TIPG_OFFSET 0x01ac /* Transmit Inter-Packet Gap */
#define IMX9_ENET_FTRL_OFFSET 0x01b0 /* Frame Truncation Length */
#define IMX9_ENET_TACC_OFFSET 0x01c0 /* Transmit Accelerator Function Configuration */
#define IMX9_ENET_RACC_OFFSET 0x01c4 /* Receive Accelerator Function Configuration */
#define IMX9_ENET_ATCR_OFFSET 0x0400 /* Timer Control Register */
#define IMX9_ENET_ATVR_OFFSET 0x0404 /* Timer Value Register */
#define IMX9_ENET_ATOFF_OFFSET 0x0408 /* Timer Offset Register */
#define IMX9_ENET_ATPER_OFFSET 0x040c /* Timer Period Register */
#define IMX9_ENET_ATCOR_OFFSET 0x0410 /* Timer Correction Register */
#define IMX9_ENET_ATINC_OFFSET 0x0414 /* Time-Stamping Clock Period Register */
#define IMX9_ENET_ATSTMP_OFFSET 0x0418 /* Timestamp of Last Transmitted Frame */
#define IMX9_ENET_TGSR_OFFSET 0x0604 /* Timer Global Status Register */
#define IMX9_ENET_TCSR0_OFFSET 0x0608 /* Timer Control Status Register */
#define IMX9_ENET_TCCR0_OFFSET 0x060c /* Timer Compare Capture Register */
#define IMX9_ENET_TCSR1_OFFSET 0x0610 /* Timer Control Status Register */
#define IMX9_ENET_TCCR1_OFFSET 0x0614 /* Timer Compare Capture Register */
#define IMX9_ENET_TCSR2_OFFSET 0x0618 /* Timer Control Status Register */
#define IMX9_ENET_TCCR2_OFFSET 0x061c /* Timer Compare Capture Register */
#define IMX9_ENET_TCSR3_OFFSET 0x0620 /* Timer Control Status Register */
#define IMX9_ENET_TCCR3_OFFSET 0x0624 /* Timer Compare Capture Register */
/* Register Addresses *******************************************************/
#define IMX9_ENET_EIR (IMX9_ENET_BASE+IMX9_ENET_EIR_OFFSET)
#define IMX9_ENET_EIMR (IMX9_ENET_BASE+IMX9_ENET_EIMR_OFFSET)
#define IMX9_ENET_RDAR (IMX9_ENET_BASE+IMX9_ENET_RDAR_OFFSET)
#define IMX9_ENET_TDAR (IMX9_ENET_BASE+IMX9_ENET_TDAR_OFFSET)
#define IMX9_ENET_ECR (IMX9_ENET_BASE+IMX9_ENET_ECR_OFFSET)
#define IMX9_ENET_MMFR (IMX9_ENET_BASE+IMX9_ENET_MMFR_OFFSET)
#define IMX9_ENET_MSCR (IMX9_ENET_BASE+IMX9_ENET_MSCR_OFFSET)
#define IMX9_ENET_MIBC (IMX9_ENET_BASE+IMX9_ENET_MIBC_OFFSET)
#define IMX9_ENET_RCR (IMX9_ENET_BASE+IMX9_ENET_RCR_OFFSET)
#define IMX9_ENET_TCR (IMX9_ENET_BASE+IMX9_ENET_TCR_OFFSET)
#define IMX9_ENET_PALR (IMX9_ENET_BASE+IMX9_ENET_PALR_OFFSET)
#define IMX9_ENET_PAUR (IMX9_ENET_BASE+IMX9_ENET_PAUR_OFFSET)
#define IMX9_ENET_OPD (IMX9_ENET_BASE+IMX9_ENET_OPD_OFFSET)
#define IMX9_ENET_IAUR (IMX9_ENET_BASE+IMX9_ENET_IAUR_OFFSET)
#define IMX9_ENET_IALR (IMX9_ENET_BASE+IMX9_ENET_IALR_OFFSET)
#define IMX9_ENET_GAUR (IMX9_ENET_BASE+IMX9_ENET_GAUR_OFFSET)
#define IMX9_ENET_GALR (IMX9_ENET_BASE+IMX9_ENET_GALR_OFFSET)
#define IMX9_ENET_TFWR (IMX9_ENET_BASE+IMX9_ENET_TFWR_OFFSET)
#define IMX9_ENET_RDSR (IMX9_ENET_BASE+IMX9_ENET_RDSR_OFFSET)
#define IMX9_ENET_TDSR (IMX9_ENET_BASE+IMX9_ENET_TDSR_OFFSET)
#define IMX9_ENET_MRBR (IMX9_ENET_BASE+IMX9_ENET_MRBR_OFFSET)
#define IMX9_ENET_RSFL (IMX9_ENET_BASE+IMX9_ENET_RSFL_OFFSET)
#define IMX9_ENET_RSEM (IMX9_ENET_BASE+IMX9_ENET_RSEM_OFFSET)
#define IMX9_ENET_RAEM (IMX9_ENET_BASE+IMX9_ENET_RAEM_OFFSET)
#define IMX9_ENET_RAFL (IMX9_ENET_BASE+IMX9_ENET_RAFL_OFFSET)
#define IMX9_ENET_TSEM (IMX9_ENET_BASE+IMX9_ENET_TSEM_OFFSET)
#define IMX9_ENET_TAEM (IMX9_ENET_BASE+IMX9_ENET_TAEM_OFFSET)
#define IMX9_ENET_TAFL (IMX9_ENET_BASE+IMX9_ENET_TAFL_OFFSET)
#define IMX9_ENET_TIPG (IMX9_ENET_BASE+IMX9_ENET_TIPG_OFFSET)
#define IMX9_ENET_FTRL (IMX9_ENET_BASE+IMX9_ENET_FTRL_OFFSET)
#define IMX9_ENET_TACC (IMX9_ENET_BASE+IMX9_ENET_TACC_OFFSET)
#define IMX9_ENET_RACC (IMX9_ENET_BASE+IMX9_ENET_RACC_OFFSET)
#define IMX9_ENET_ATCR (IMX9_ENET_BASE+IMX9_ENET_ATCR_OFFSET)
#define IMX9_ENET_ATVR (IMX9_ENET_BASE+IMX9_ENET_ATVR_OFFSET)
#define IMX9_ENET_ATOFF (IMX9_ENET_BASE+IMX9_ENET_ATOFF_OFFSET)
#define IMX9_ENET_ATPER (IMX9_ENET_BASE+IMX9_ENET_ATPER_OFFSET)
#define IMX9_ENET_ATCOR (IMX9_ENET_BASE+IMX9_ENET_ATCOR_OFFSET)
#define IMX9_ENET_ATINC (IMX9_ENET_BASE+IMX9_ENET_ATINC_OFFSET)
#define IMX9_ENET_ATSTMP (IMX9_ENET_BASE+IMX9_ENET_ATSTMP_OFFSET)
#define IMX9_ENET_TGSR (IMX9_ENET_BASE+IMX9_ENET_TGSR_OFFSET)
#define IMX9_ENET_TCSR0 (IMX9_ENET_BASE+IMX9_ENET_TCSR0_OFFSET)
#define IMX9_ENET_TCCR0 (IMX9_ENET_BASE+IMX9_ENET_TCCR0_OFFSET)
#define IMX9_ENET_TCSR1 (IMX9_ENET_BASE+IMX9_ENET_TCSR1_OFFSET)
#define IMX9_ENET_TCCR1 (IMX9_ENET_BASE+IMX9_ENET_TCCR1_OFFSET)
#define IMX9_ENET_TCSR2 (IMX9_ENET_BASE+IMX9_ENET_TCSR2_OFFSET)
#define IMX9_ENET_TCCR2 (IMX9_ENET_BASE+IMX9_ENET_TCCR2_OFFSET)
#define IMX9_ENET_TCSR3 (IMX9_ENET_BASE+IMX9_ENET_TCSR3_OFFSET)
#define IMX9_ENET_TCCR3 (IMX9_ENET_BASE+IMX9_ENET_TCCR3_OFFSET)
/* Register Bit Definitions *************************************************/
/* Interrupt Event Register, Interrupt Mask Register */
#define ENET_RXB1 (1 << 0) /* Receive buffer interrupt, class 1 */
#define ENET_RXF1 (1 << 1) /* Receive frame interrupt, class 1 */
#define ENET_TXB1 (1 << 2) /* Transmit buffer interrupt, class 1 */
#define ENET_TXF1 (1 << 3) /* Transmit frame interrupt, class 1 */
#define ENET_RXB2 (1 << 4) /* Receive buffer interrupt, class 2 */
#define ENET_RXF2 (1 << 5) /* Receive frame interrupt, class 2 */
#define ENET_TXB2 (1 << 6) /* Transmit buffer interrupt, class 2 */
#define ENET_TXF2 (1 << 7) /* Transmit frame interrupt, class 2 */
#define ENET_RXFLUSH_0 (1 << 12) /* RX DMA Ring 0 flush indication */
#define ENET_RXFLUSH_1 (1 << 13) /* RX DMA Ring 1 flush indication */
#define ENET_RXFLUSH_2 (1 << 14) /* RX DMA Ring 2 flush indication */
#define ENET_INT_TS_TIMER (1 << 15) /* Bit 15: Timestamp timer */
#define ENET_INT_TS_AVAIL (1 << 16) /* Bit 16: Transmit timestamp available */
#define ENET_INT_WAKEUP (1 << 17) /* Bit 17: Node wake-up request indication */
#define ENET_INT_PLR (1 << 18) /* Bit 18: Payload receive error */
#define ENET_INT_UN (1 << 19) /* Bit 19: Transmit FIFO underrun */
#define ENET_INT_RL (1 << 20) /* Bit 20: Collision Retry Limit */
#define ENET_INT_LC (1 << 21) /* Bit 21: Late Collision */
#define ENET_INT_EBERR (1 << 22) /* Bit 22: Ethernet Bus Error */
#define ENET_INT_MII (1 << 23) /* Bit 23: MII Interrupt */
#define ENET_INT_RXB (1 << 24) /* Bit 24: Receive Buffer Interrupt */
#define ENET_INT_RXF (1 << 25) /* Bit 25: Receive Frame Interrupt */
#define ENET_INT_TXB (1 << 26) /* Bit 26: Transmit Buffer Interrupt */
#define ENET_INT_TXF (1 << 27) /* Bit 27: Transmit Frame Interrupt */
#define ENET_INT_GRA (1 << 28) /* Bit 28: Graceful Stop Complete */
#define ENET_INT_BABT (1 << 29) /* Bit 29: Babbling Transmit Error */
#define ENET_INT_BABR (1 << 30) /* Bit 30: Babbling Receive Error */
/* Bit 31: Reserved */
/* Receive Descriptor Active Register */
/* Bits 0-23: Reserved */
#define ENET_RDAR (1 << 24) /* Bit 24: Receive descriptor active */
/* Bits 25-31: Reserved */
/* Transmit Descriptor Active Register */
/* Bits 0-23: Reserved */
#define ENET_TDAR (1 << 24) /* Bit 24: Transmit descriptor active */
/* Bits 25-31: Reserved */
/* Ethernet Control Register */
#define ENET_ECR_RESET (1 << 0) /* Bit 0: Ethernet MAC reset */
#define ENET_ECR_ETHEREN (1 << 1) /* Bit 1: Ethernet enable */
#define ENET_ECR_MAGICEN (1 << 2) /* Bit 2: Magic packet detection enable */
#define ENET_ECR_SLEEP (1 << 3) /* Bit 3: Sleep mode enable */
#define ENET_ECR_EN1588 (1 << 4) /* Bit 4: EN1588 enable */
#define ENET_ECR_SPEED (1 << 5) /* Bit 5: 10/100-Mbit/s or 1000-Mbit/s mode */
#define ENET_ECR_DBGEN (1 << 6) /* Bit 6: Debug enable */
/* Bit 7: Reserved, always write 0 */
#define ENET_ECR_DBSWP (1 << 8) /* Bit 8: Swap bytes; always write 1 after reset */
#define ENET_ECR_SVLANEN (1 << 9) /* Bit 9: S-VLAN enable */
#define ENET_ECR_VLANUSE2ND (1 << 10) /* Bit 10: VLAN use second tag */
#define ENET_ECR_SVLANDBL (1 << 11) /* Bit 11: S-VLAN double tag */
#define ENET_ECR_TXC_DLY (1 << 16) /* Bit 16: Transmit clock delay */
#define ENET_ECR_RXC_DLY (1 << 17) /* Bit 17: Receive clock delay */
/* Bits 12-15: Reserved, always write 0 */
#define ENET_ECR_RESV_MASK (0x3ffff << 18) /* Reserved, always write 0x1c00 */
/* MII Management Frame Register */
#define ENET_MMFR_DATA_SHIFT (0) /* Bits 0-15: Management frame data */
#define ENET_MMFR_DATA_MASK (0xffff << ENET_MMFR_DATA_SHIFT)
#define ENET_MMFR_TA_SHIFT (16) /* Bits 16-17: Turn around */
#define ENET_MMFR_TA_MASK (0x3 << ENET_MMFR_TA_SHIFT)
#define ENET_MMFR_RA_SHIFT (18) /* Bits 18-22: Register address */
#define ENET_MMFR_RA_MASK (0x1f << ENET_MMFR_RA_SHIFT)
#define ENET_MMFR_PA_SHIFT (23) /* Bits 23-27: PHY address */
#define ENET_MMFR_PA_MASK (0x1f << ENET_MMFR_PA_SHIFT)
#define ENET_MMFR_OP_SHIFT (28) /* Bits 28-29: Operation code */
#define ENET_MMFR_OP_MASK (0x3 << ENET_MMFR_OP_SHIFT)
# define ENET_MMFR_OP_WRNOTMII (0 << ENET_MMFR_OP_SHIFT) /* Write frame, not MII compliant */
# define ENET_MMFR_OP_WRMII (1 << ENET_MMFR_OP_SHIFT) /* Write frame, MII management frame */
# define ENET_MMFR_OP_RDMII (2 << ENET_MMFR_OP_SHIFT) /* Read frame, MII management frame */
# define ENET_MMFR_OP_RDNOTMII (3 << ENET_MMFR_OP_SHIFT) /* Read frame, not MII compliant */
#define ENET_MMFR_ST_SHIFT (30) /* Bits 30-31: Start of frame delimiter */
#define ENET_MMFR_ST_MASK (0x3 << ENET_MMFR_ST_SHIFT)
/* MII Speed Control Register */
/* Bit 0: Reserved */
#define ENET_MSCR_MII_SPEED_SHIFT (1) /* Bits 1-6: MII speed */
#define ENET_MSCR_MII_SPEED_MASK (0x3f << ENET_MSCR_MII_SPEED_SHIFT)
# define ENET_MSCR_MII_SPEED_25MHz (0x4) /* Optimum value for IPS bus 25 MHz clock */
# define ENET_MSCR_MII_SPEED_33MHz (0x6) /* Optimum value for IPS bus 33 MHz clock */
# define ENET_MSCR_MII_SPEED_40MHz (0x7) /* Optimum value for IPS bus 40 MHz clock */
# define ENET_MSCR_MII_SPEED_50MHz (0x9) /* Optimum value for IPS bus 50 MHz clock */
# define ENET_MSCR_MII_SPEED_66MHz (0xd) /* Optimum value for IPS bus 60 MHz clock */
#define ENET_MSCR_DIS_PRE (1 << 7) /* Bit 7: Disable preamble */
#define ENET_MSCR_HOLDTIME_SHIFT (8) /* Bits 8-10: Holdtime on MDIO output */
#define ENET_MSCR_HOLDTIME_MASK (0x7 << ENET_MSCR_HOLDTIME_SHIFT)
# define ENET_MSCR_HOLDTIME_1CYCLE (0 << ENET_MSCR_HOLDTIME_SHIFT) /* 1 internal module clock cycle */
# define ENET_MSCR_HOLDTIME_2CYCLES (1 << ENET_MSCR_HOLDTIME_SHIFT) /* 2 internal module clock cycles */
# define ENET_MSCR_HOLDTIME_3CYCLES (2 << ENET_MSCR_HOLDTIME_SHIFT) /* 3 internal module clock cycles */
# define ENET_MSCR_HOLDTIME_8CYCLES (7 << ENET_MSCR_HOLDTIME_SHIFT) /* 8 internal module clock cycles */
/* MIB Control Register */
/* Bits 0-28: Reserved */
#define ENET_MIBC_MIB_CLEAR (1 << 29) /* Bit 29: MIB clear */
#define ENET_MIBC_MIB_IDLE (1 << 30) /* Bit 30: MIB idle */
#define ENET_MIBC_MIB_DIS (1 << 31) /* Bit 31: Disable MIB logic */
/* Receive Control Register */
#define ENET_RCR_LOOP (1 << 0) /* Bit 0: Internal loopback */
#define ENET_RCR_DRT (1 << 1) /* Bit 1: Disable receive on transmit */
#define ENET_RCR_MII_MODE (1 << 2) /* Bit 2: Media independent interface mode */
#define ENET_RCR_PROM (1 << 3) /* Bit 3: Promiscuous mode */
#define ENET_RCR_BC_REJ (1 << 4) /* Bit 4: Broadcast frame reject */
#define ENET_RCR_FCE (1 << 5) /* Bit 5: Flow control enable */
#define ENET_RCR_RGMII_EN (1 << 6) /* Bit 6: RGMII mode enable */
/* Bit 7: Reserved */
#define ENET_RCR_RMII_MODE (1 << 8) /* Bit 8: RGMII mode enable */
#define ENET_RCR_RMII_10T (1 << 9) /* Bit 9: Enables 10-Mbps mode of the RMII */
/* Bits 10-11: Reserved */
#define ENET_RCR_PADEN (1 << 12) /* Bit 12: Enable frame padding remove on receive */
#define ENET_RCR_PAUFWD (1 << 13) /* Bit 13: Terminate/forward pause frames */
#define ENET_RCR_CRCFWD (1 << 14) /* Bit 14: Terminate/forward received CRC */
#define ENET_RCR_CFEN (1 << 15) /* Bit 15: MAC control frame enable */
#define ENET_RCR_MAX_FL_SHIFT (16) /* Bits 16-29: Maximum frame length */
#define ENET_RCR_MAX_FL_MASK (0x3fff << ENET_RCR_MAX_FL_SHIFT)
#define ENET_RCR_NLC (1 << 30) /* Bit 30: Payload length check disable */
#define ENET_RCR_GRS (1 << 31) /* Bit 31: Graceful receive stopped */
/* Transmit Control Register */
#define ENET_TCR_GTS (1 << 0) /* Bit 0: Graceful transmit stop */
/* Bit 1: Reserved */
#define ENET_TCR_FDEN (1 << 2) /* Bit 2: Full duplex enable */
#define ENET_TCR_TFC_PAUSE (1 << 3) /* Bit 3: Transmit frame control pause */
#define ENET_TCR_RFC_PAUSE (1 << 4) /* Bit 4: Receive frame control pause */
#define ENET_TCR_ADDSEL_SHIFT (5) /* Bits 5-7: Source MAC address select on transmit */
#define ENET_TCR_ADDSEL_MASK (0x7 << ENET_TCR_ADDSEL_SHIFT)
#define ENET_TCR_ADDSEL_PADDR12 (0 << ENET_TCR_ADDSEL_SHIFT)
#define ENET_TCR_ADDINS (1 << 8) /* Bit 8: Set MAC address on transmit */
#define ENET_TCR_CRCFWD (1 << 9) /* Bit 9: Forward frame from application with CRC */
/* Bits 10-31: Reserved, 10 must be written to 0 */
/* Physical Address Lower/Upper Register (32-bits of 48-address) */
/* Physical Address Upper Register */
#define ENET_PAUR_TYPE_SHIFT (0) /* Bits 0-15: Type field in PAUSE frame */
#define ENET_PAUR_TYPE_MASK (0xffff << ENET_PAUR_TYPE_MASK)
#define ENET_PAUR_PADDR2_SHIFT (16) /* Bits 16-31: Bytes 4 and 5 of the 6-byte address */
#define ENET_PAUR_PADDR2_MASK (0xffff << ENET_PAUR_PADDR2_SHIFT)
/* Opcode/Pause Duration Register */
#define ENET_OPD_PAUSE_DUR_SHIFT (0) /* Bits 0-15: Pause duration */
#define ENET_OPD_PAUSE_DUR_MASK (0xffff << ENET_OPD_PAUSE_DUR_SHIFT)
#define ENET_OPD_OPCODE_SHIFT (16) /* Bits 16-31: Opcode field in PAUSE frames */
#define ENET_OPD_OPCODE_MASK (0xffff << ENET_OPD_OPCODE_SHIFT)
/* Descriptor Individual Upper/Lower Address Register
* (64-bit address in two 32-bit registers)
*/
/* Descriptor Group Upper/Lower Address Register
* (64-bit address in two 32-bit registers)
*/
/* Transmit Interrupt Coalescing Register */
#define ENET_TXIC_ICTT_SHIFT (0) /* Bits 0-15: Interrupt coalescing timer threshold */
#define ENET_TXIC_ICTT_SHIFT_MASK (0xffff << ENET_TXIC_ICTT_SHIFT)
/* Bits 16-19: Reserved */
#define ENET_TXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */
#define ENET_TXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT)
#define ENET_TXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */
#define ENET_TXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */
/* Receive Interrupt Coalescing Register */
#define ENET_RXIC_ICTT_SHIFT (0) /* Bits 0-15: Interrupt coalescing timer threshold */
#define ENET_RXIC_ICTT_SHIFT_MASK (0xffff << ENET_TXIC_ICTT_SHIFT)
/* Bits 16-19: Reserved */
#define ENET_RXIC_ICFT_SHIFT (20) /* Bits 0-15: Interrupt coalescing timer threshold */
#define ENET_RXIC_ICFT_SHIFT_MASK (0xff << ENET_TXIC_ICFT_SHIFT)
#define ENET_RXIC_ICTT_ICCS (1 << 30) /* Bit 30: Interrupt Coalescing Timer Clock Source Select */
#define ENET_RXIC_ICTT_ICEN (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */
/* Transmit FIFO Watermark Register */
#define ENET_TFWR_TFWR_SHIFT (0) /* Bits 0-5: Transmit FIFO write */
/* Bits 6-7: Reserved */
#define ENET_TFWR_TFWR_MASK (0x3f << ENET_TFWR_TFWR_SHIFT)
#define ENET_TFWR_STRFWD (1 << 8) /* Bit 8: Store and forward enable */
/* Bits 9-31: Reserved */
/* Receive Descriptor Ring Start Register */
/* Bits 0-2: Reserved */
#define ENET_RDSR_SHIFT (3) /* Bits 3-31: Start of the receive buffer descriptor queue */
#define ENET_RDSR_MASK (0xfffffff8)
/* Transmit Buffer Descriptor Ring Start Register */
/* Bits 0-2: Reserved */
#define ENET_TDSR_SHIFT (3) /* Bits 3-31: Start of the transmit buffer descriptor queue */
#define ENET_TDSR_MASK (0xfffffff8)
/* Maximum Receive Buffer Size Register */
/* Bits 14-31: Reserved */
#define ENET_MRBR_SHIFT (4) /* Bits 4-13: Receive buffer size in bytes */
#define ENET_MRBR_MASK (0x3ff << ENET_MRBR_SHIFT)
/* Bits 0-3: Reserved */
/* Receive FIFO Section Full Threshold */
/* Bits 10-31: Reserved */
#define ENET_RSFL_SHIFT (0) /* Bits 0-9: Value of receive FIFO section full threshold */
#define ENET_RSFL_MASK (0x3ff << ENET_RSFL_SHIFT)
/* Receive FIFO Section Empty Threshold */
#define ENET_RSEM_RX_EMPTY_SHIFT (0) /* Bits 0-9: Value of the receive FIFO section empty threshold */
#define ENET_RSEM_RX_EMPTY_MASK (0x3ff << ENET_RSEM_RX_EMPTY_SHIFT)
/* Bits 10-15: Reserved */
#define ENET_RSEM_SEC_EMPTY_SHIFT (16) /* Bits 16-20: RX Status FIFO Section Empty Threshold */
#define ENET_RSEM_SEC_EMPTY_MASK (0x1f << ENET_RSEM_SEC_EMPTY_SHIFT)
/* Receive FIFO Almost Empty Threshold */
#define ENET_RAEM_SHIFT (0) /* Bits 0-9: Value of the receive FIFO almost empty threshold */
#define ENET_RAEM_MASK (0x3ff << ENET_RAEM_SHIFT)
/* Bits 10-31: Reserved */
/* Receive FIFO Almost Full Threshold */
#define ENET_RAFL_SHIFT (0) /* Bits 0-9: Value of the receive FIFO almost full threshold */
#define ENET_RAFL_MASK (0x3ff << ENET_RAFL_SHIFT)
/* Bits 10-31: Reserved */
/* Transmit FIFO Section Empty Threshold */
#define ENET_TSEM_SHIFT (0) /* Bits 0-9: Value of the transmit FIFO section empty threshold */
#define ENET_TSEM_MASK (0x3ff << ENET_TSEM_SHIFT)
/* Bits 10-31: Reserved */
/* Transmit FIFO Almost Empty Threshold */
#define ENET_TAEM_SHIFT (0) /* Bits 0-9: Value of the transmit FIFO section empty threshold */
#define ENET_TAEM_MASK (0x3ff << ENET_TAEM_SHIFT)
/* Bits 10-31: Reserved */
/* Transmit FIFO Almost Full Threshold */
#define ENET_TAFL_SHIFT (0) /* Bits 0-9: Value of the transmit FIFO section empty threshold */
#define ENET_TAFL_MASK (0x3ff << ENET_TAFL_SHIFT)
/* Bits 10-31: Reserved */
/* Transmit Inter-Packet Gap */
#define ENET_TIPG_SHIFT (0) /* Bits 0-4: Value of the transmit FIFO section empty threshold */
#define ENET_TIPG_MASK (0x1f << ENET_TIPG_SHIFT)
/* Bits 5-31: Reserved */
/* Frame Truncation Length */
#define ENET_FTRL_SHIFT (0) /* Bits 0-13: Value of the transmit FIFO section empty threshold */
#define ENET_FTRL_MASK (0x3fff << ENET_FTRL_SHIFT)
/* Bits 14-31: Reserved */
/* Transmit Accelerator Function Configuration */
#define ENET_TACC_SHIFT16 (1 << 0) /* Bit 0: TX FIFO shift-16 */
/* Bits 1-2: Reserved */
#define ENET_TACC_IPCHK (1 << 3) /* Bit 3: Enables insertion of IP header checksum */
#define ENET_TACC_PROCHK (1 << 4) /* Bit 4: Enables insertion of protocol checksum */
/* Bits 5-31: Reserved */
/* Receive Accelerator Function Configuration */
#define ENET_RACC_PADREM (1 << 0) /* Bit 0: Enable padding removal for short IP frames */
#define ENET_RACC_IPDIS (1 << 1) /* Bit 1: Enable discard of frames with wrong IPv4 header checksum */
#define ENET_RACC_PRODIS (1 << 2) /* Bit 2: Enable discard of frames with wrong protocol checksum */
/* Bits 3-5: Reserved */
#define ENET_RACC_LINEDIS (1 << 6) /* Bit 6: Enable discard of frames with MAC layer errors */
#define ENET_RACC_SHIFT16 (1 << 7) /* Bit 7: RX FIFO shift-16 */
/* Bits 8-31: Reserved */
/* Timer Control Register */
#define ENET_ATCR_EN (1 << 0) /* Bit 0: Enable timer */
/* Bit 1: Reserved */
#define ENET_ATCR_OFFEN (1 << 2) /* Bit 2: Enable one-shot offset event */
#define ENET_ATCR_OFFRST (1 << 3) /* Bit 3: Reset timer on offset event */
#define ENET_ATCR_PEREN (1 << 4) /* Bit 4: Enable periodical event */
/* Bits 5-6: Reserved */
#define ENET_ATCR_PINPER (1 << 7) /* Bit 7: Enables event signal output assertion on period event */
/* Bit 8: Reserved */
#define ENET_ATCR_RESTART (1 << 9) /* Bit 9: Reset timer */
/* Bit 10: Reserved */
#define ENET_ATCR_CAPTURE (1 << 11) /* Bit 11: Capture timer value */
/* Bit 12: Reserved */
#define ENET_ATCR_SLAVE (1 << 13) /* Bit 13: Enable timer slave mode */
/* Bits 14-31: Reserved */
/* Timer Value Register (32-bit timer value) */
/* Timer Offset Register (32-bit offset value) */
/* Timer Period Register (32-bit timer period) */
/* Timer Correction Register */
#define ENET_ATCOR_MASK (0x7fffffff) /* Bits 0-3: Correction counter wrap-around value */
/* Bit 31: Reserved */
/* Time-Stamping Clock Period Register */
#define ENET_ATINC_INC_SHIFT (0) /* Bits 0-6: Clock period of the timestamping clock (ts_clk) in nanoseconds */
#define ENET_ATINC_INC_MASK (0x7f << ENET_ATINC_INC_SHIFT)
/* Bit 7: Reserved */
#define ENET_ATINC_INC_CORR_SHIFT (8) /* Bits 8-14: Correction increment value */
#define ENET_ATINC_INC_CORR_MASK (0x7f << ENET_ATINC_INC_CORR_SHIFT)
/* Bits 15-31: Reserved */
/* Timestamp of Last Transmitted Frame (32-bit timestamp) */
/* Timer Global Status Register */
#define ENET_TGSR_TF0 (1 << 0) /* Bit 0: Copy of Timer Flag for channel 0 */
#define ENET_TGSR_TF1 (1 << 1) /* Bit 1: Copy of Timer Flag for channel 1 */
#define ENET_TGSR_TF2 (1 << 2) /* Bit 2: Copy of Timer Flag for channel 2 */
#define ENET_TGSR_TF3 (1 << 3) /* Bit 3: Copy of Timer Flag for channel 3 */
/* Bits 4-31: Reserved */
/* Timer Control Status Register n */
#define ENET_TCSR_TDRE (1 << 0) /* Bit 0: Timer DMA Request Enable */
/* Bit 1: Reserved */
#define ENET_TCSR_TMODE_SHIFT (2) /* Bits 2-5: Timer Mode */
#define ENET_TCSR_TMODE_MASK (0xf << ENET_TCSR_TMODE_SHIFT)
# define ENET_TCSR_TMODE_DISABLED (0 << ENET_TCSR_TMODE_SHIFT) /* Disabled */
# define ENET_TCSR_TMODE_ICRISING (1 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on rising edge */
# define ENET_TCSR_TMODE_ICFALLLING (2 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on falling edge */
# define ENET_TCSR_TMODE_ICBOTH (3 << ENET_TCSR_TMODE_SHIFT) /* Input Capture on both edges */
# define ENET_TCSR_TMODE_OCSW (4 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, S/W only */
# define ENET_TCSR_TMODE_OCTOGGLE (5 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, toggle on compare */
# define ENET_TCSR_TMODE_OCCLR (6 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, clear on compare */
# define ENET_TCSR_TMODE_OCSET (7 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, set on compare */
# define ENET_TCSR_TMODE_OCSETCLR (9 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, set on compare, clear on overflow */
# define ENET_TCSR_TMODE_OCCLRSET (10 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, clear on compare, set on overflow */
# define ENET_TCSR_TMODE_PCPULSEL (14 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse low on compare */
# define ENET_TCSR_TMODE_PCPULSEH (15 << ENET_TCSR_TMODE_SHIFT) /* Output Compare, pulse high on compare */
#define ENET_TCSR_TIE (1 << 6) /* Bit 6: Timer interrupt enable */
#define ENET_TCSR_TF (1 << 7) /* Bit 7: Timer Flag */
/* Bits 8-31: Reserved */
/* Timer Compare Capture Register (32-bit compare value) */
/* Buffer Descriptors *******************************************************/
/* Endian-independent descriptor offsets */
#define DESC_STATUS1_OFFSET (0)
#define DESC_LENGTH_OFFSET (2)
#define DESC_DATAPTR_OFFSET (4)
#define DESC_LEGACY_LEN (8)
#define DESC_STATUS2_OFFSET (8)
#define DESC_LENPROTO_OFFSET (12)
#define DESC_CHECKSUM_OFFSET (14)
#define DESC_BDU_OFFSET (16)
#define DESC_TIMESTAMP_OFFSET (20)
#define DESC_ENHANCED_LEN (32)
/* Legacy/Common TX Buffer Descriptor Bit Definitions. */
#define IMX9_USE_DBSWAP
# define TXDESC_TC (1 << 10) /* Common */
# define TXDESC_L (1 << 11) /* Common */
# define TXDESC_TO2 (1 << 12) /* Common */
# define TXDESC_W (1 << 13) /* Common */
# define TXDESC_TO1 (1 << 14) /* Common */
# define TXDESC_R (1 << 15) /* Common */
/* Enhanced TX Buffer Descriptor Bit Definitions */
# define TXDESC_TSE (1 << 8)
# define TXDESC_OE (1 << 9)
# define TXDESC_LCE (1 << 10)
# define TXDESC_FE (1 << 11)
# define TXDESC_EE (1 << 12)
# define TXDESC_UE (1 << 13)
# define TXDESC_TXE (1 << 15)
# define TDXESC_FTYPE_N (0 << 20)
# define TDXESC_FTYPE_A (1 << 20)
# define TDXESC_FTYPE_B (2 << 20)
# define TXDESC_UTLT (1 << 24)
# define TXDESC_IINS (1 << 27)
# define TXDESC_PINS (1 << 28)
# define TXDESC_TS (1 << 29)
# define TXDESC_INT (1 << 30)
# define TXDESC_BDU (1 << 31)
/* Legacy (and Common) RX Buffer Descriptor Bit Definitions */
# define RXDESC_TR (1 << 0)
# define RXDESC_OV (1 << 1)
# define RXDESC_CR (1 << 2)
# define RXDESC_NO (1 << 4)
# define RXDESC_LG (1 << 5)
# define RXDESC_MC (1 << 6)
# define RXDESC_BC (1 << 7)
# define RXDESC_M (1 << 8)
# define RXDESC_L (1 << 11)
# define RXDESC_R02 (1 << 12)
# define RXDESC_W (1 << 13)
# define RXDESC_R01 (1 << 14)
# define RXDESC_E (1 << 15)
/* Enhanced (only) RX Buffer Descriptor Bit Definitions */
# define RXDESC_FRAG (1 << 0)
# define RXDESC_IPV6 (1 << 1)
# define RXDESC_VLAN (1 << 2)
# define RXDESC_PCR (1 << 4)
# define RXDESC_ICE (1 << 5)
# define RXDESC_INT (1 << 23)
# define RXDESC_UC (1 << 24)
# define RXDESC_CE (1 << 25)
# define RXDESC_PE (1 << 26)
# define RXDESC_ME (1 << 31)
# define RXDESC_BDU (1 << 31)
#define RXDESC_STATUS1_ERRORS (RXDESC_TR | RXDESC_OV | RXDESC_CR | RXDESC_NO | RXDESC_LG)
#define RXDESC_STATUS2_ERRORS (RXDESC_CE | RXDESC_PE | RXDESC_ME)
#define TXDESC_STATUS2_ERRORS (TXDESC_TSE | TXDESC_OE | TXDESC_LCE | TXDESC_FE | TXDESC_EE | TXDESC_UE | TXDESC_TXE)
/* From ref manual TDSR/RDSR description
* For optimal performance the pointer should be 512-bit aligned, that is,
* evenly divisible by 64. NOTE: This is also cache-line size
*/
#define ENET_ALIGN 64
#define ENET_ALIGN_MASK (ENET_ALIGN - 1)
#define ENET_ALIGN_UP(n) (((n) + ENET_ALIGN_MASK) & ~ENET_ALIGN_MASK)
/****************************************************************************
* Public Types
****************************************************************************/
/* Buffer Descriptors *******************************************************/
/* Little endian descriptor order, with ECR[DBSWP] = 1 */
struct enet_desc_s
{
uint16_t length; /* Data length */
uint16_t status1; /* Control and status */
uint32_t data; /* Buffer address */
uint32_t status2; /* Extended status */
uint16_t checksum; /* Payload checksum */
uint16_t lenproto; /* Header length + Protocol type */
uint32_t bdu; /* BDU */
uint32_t timestamp; /* Time stamp */
uint32_t reserved1; /* unused */
uint32_t reserved2; /* unused */
};
/* This is a 64-byte descriptor pair used for TX. Two descriptors are used
* for each TX transmission to match descriptors used for a single
* transmission on a a single cache line
*/
struct enet_txdesc_s
{
struct enet_desc_s d1;
struct enet_desc_s d2;
};
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_ENET_H */

3215
arch/arm64/src/imx9/imx9_enet.c Normal file
View File

File diff suppressed because it is too large Load Diff

106
arch/arm64/src/imx9/imx9_enet.h Normal file
View File

@ -0,0 +1,106 @@
/****************************************************************************
* arch/arm64/src/imx9/imx9_enet.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM64_SRC_IMX9_IMX9_ENET_H
#define __ARCH_ARM64_SRC_IMX9_IMX9_ENET_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imx9_enet.h"
#ifdef CONFIG_IMX9_ENET
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Definitions for use with imx9_phy_boardinitialize */
#define EMAC_INTF 0
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Function: imx9_netinitialize
*
* Description:
* Initialize the Ethernet controller and driver
*
* Input Parameters:
* intf - In the case where there are multiple EMACs, this value
* identifies which EMAC is to be initialized.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
*
****************************************************************************/
int imx9_netinitialize(int intf);
/****************************************************************************
* Function: imx9_phy_boardinitialize
*
* Description:
* Some boards require specialized initialization of the PHY before it can
* be used. This may include such things as configuring GPIOs, resetting
* the PHY, etc. If CONFIG_IMX9_ENET_PHYINIT is defined in the
* configuration then the board specific logic must provide
* imx9_phyinitialize(); The i.MX RT Ethernet driver will call this
* function one time before it first uses the PHY.
*
* Input Parameters:
* intf - Always zero for now.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
****************************************************************************/
#ifdef CONFIG_IMX9_ENET_PHYINIT
int imx9_phy_boardinitialize(int intf);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_IMX9_ENET */
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_ENET_H */

15
boards/arm64/imx9/imx93-evk/configs/nsh/defconfig
View File

@ -22,7 +22,10 @@ CONFIG_DEBUG_FULLOPT=y
CONFIG_DEBUG_SYMBOLS=y
CONFIG_DEFAULT_TASK_STACKSIZE=8192
CONFIG_DEV_ZERO=y
CONFIG_ETH0_PHY_MULTI=y
CONFIG_EXAMPLES_HELLO=y
CONFIG_EXAMPLES_TCPBLASTER=y
CONFIG_EXAMPLES_UDPBLASTER=y
CONFIG_EXPERIMENTAL=y
CONFIG_FS_PROCFS=y
CONFIG_FS_ROMFS=y
@ -35,6 +38,9 @@ CONFIG_IDLETHREAD_STACKSIZE=8192
CONFIG_IMX9_DMA_ALLOC=y
CONFIG_IMX9_DMA_ALLOC_POOL_SIZE=81920
CONFIG_IMX9_EDMA=y
CONFIG_IMX9_ENET1_RGMII=y
CONFIG_IMX9_ENET=y
CONFIG_IMX9_ENET_USE_OTP_MAC=y
CONFIG_IMX9_FLEXIO1_PWM=y
CONFIG_IMX9_GPIO_IRQ=y
CONFIG_IMX9_LPI2C1=y
@ -52,6 +58,14 @@ CONFIG_IMX9_USBDEV_USBC1=y
CONFIG_INIT_ENTRYPOINT="nsh_main"
CONFIG_INTELHEX_BINARY=y
CONFIG_LPUART1_SERIAL_CONSOLE=y
CONFIG_NDEBUG=y
CONFIG_NET=y
CONFIG_NETDB_DNSCLIENT=y
CONFIG_NETDEV_PHY_IOCTL=y
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_TCP=y
CONFIG_NET_UDP=y
CONFIG_NSH_ARCHINIT=y
CONFIG_NSH_BUILTIN_APPS=y
CONFIG_NSH_FILEIOSIZE=512
@ -78,6 +92,7 @@ CONFIG_SYMTAB_ORDEREDBYNAME=y
CONFIG_SYSTEM_CDCACM=y
CONFIG_SYSTEM_I2CTOOL=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_PING=y
CONFIG_SYSTEM_SPITOOL=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_SYSTEM_TIME64=y

81
boards/arm64/imx9/imx93-evk/include/board.h
View File

@ -26,6 +26,8 @@
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/net/mii.h>
#include <nuttx/net/gmii.h>
/****************************************************************************
* Pre-processor Definitions
@ -121,6 +123,85 @@
PFD_CFG(IMX9_SYSPLL_BASE, 2, PFD_PARMS(6, 2, true)), \
}
/* Ethernet configuration */
#define BOARD_ENET1_PHY_LIST \
{ \
{ \
.name = GMII_RTL8211F_NAME, \
.id1 = GMII_PHYID1_RTL8211F, \
.id2 = GMII_PHYID2_RTL8211F, \
.status = GMII_RTL8211F_PHYSR_A43, \
.address_lo = 2, \
.address_high = 0xffff, \
.mbps10 = GMII_RTL8211F_PHYSR_10MBPS, \
.mbps100 = GMII_RTL8211F_PHYSR_100MBPS, \
.duplex = GMII_RTL8211F_PHYSR_DUPLEX, \
.clause = 22, \
.mbps1000 = GMII_RTL8211F_PHYSR_1000MBPS, \
.speed_mask = GMII_RTL8211F_PHYSR_SPEED_MASK, \
}, \
}
#endif /* CONFIG_IMX9_ENET1 */
#ifdef CONFIG_IMX9_ENET1
#define MUX_ENET1_MDIO IOMUX_CFG(IOMUXC_PAD_ENET2_MDIO_ENET1_MDIO, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, IOMUXC_MUX_SION_ON)
#define MUX_ENET1_MDC IOMUX_CFG(IOMUXC_PAD_ENET2_MDC_ENET1_MDC, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0)
#define MUX_ENET1_RX_DATA00 IOMUX_CFG(IOMUXC_PAD_ENET2_RD0_ENET1_RGMII_RD0, 0, 0)
#define MUX_ENET1_RX_DATA01 IOMUX_CFG(IOMUXC_PAD_ENET2_RD1_ENET1_RGMII_RD1, 0, 0)
#define MUX_ENET1_TX_DATA00 IOMUX_CFG(IOMUXC_PAD_ENET2_TD0_ENET1_RGMII_TD0, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0)
#define MUX_ENET1_TX_DATA01 IOMUX_CFG(IOMUXC_PAD_ENET2_TD1_ENET1_RGMII_TD1, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0)
#if defined(CONFIG_IMX9_ENET1_RGMII)
# define MUX_ENET1_RX_DATA02 IOMUX_CFG(IOMUXC_PAD_ENET2_RD2_ENET1_RGMII_RD2, 0, 0)
# define MUX_ENET1_RX_DATA03 IOMUX_CFG(IOMUXC_PAD_ENET2_RD3_ENET1_RGMII_RD3, 0, 0)
# define MUX_ENET1_TX_DATA02 IOMUX_CFG(IOMUXC_PAD_ENET2_TD2_ENET1_RGMII_TD2, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0)
# define MUX_ENET1_TX_DATA03 IOMUX_CFG(IOMUXC_PAD_ENET2_TD3_ENET1_RGMII_TD3, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0)
# define MUX_ENET1_RXC IOMUX_CFG(IOMUXC_PAD_ENET2_RXC_ENET1_RGMII_RXC, 0, 0)
# define MUX_ENET1_TX_CTL IOMUX_CFG(IOMUXC_PAD_ENET2_TX_CTL_ENET1_RGMII_TX_CTL, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0)
# define MUX_ENET1_RX_CTL IOMUX_CFG(IOMUXC_PAD_ENET2_RX_CTL_ENET1_RGMII_RX_CTL, 0, 0)
#elif defined(CONFIG_IMX9_ENET1_RMII)
/* Same pin as TX_CTL for RGMII */
# define MUX_ENET1_TX_EN IOMUX_CFG(IOMUXC_PAD_ENET2_TX_CTL_ENET1_RGMII_TX_CTL, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0)
/* Same pin as TX_DATA02 for RGMII */
# define MUX_ENET1_REF_CLK IOMUX_CFG(IOMUXC_PAD_ENET2_TD2_ENET1_RGMII_TD2, IOMUXC_PAD_FSEL_FAST | IOMUXC_PAD_DSE_X6, 0)
/* Same pin as RX_CTL for RGMII */
# define MUX_ENET1_CRS_DV IOMUX_CFG(IOMUXC_PAD_ENET2_RX_CTL_ENET1_RGMII_RX_CTL, 0, 0)
#else
#error ENET1 supports only RMII and RGMII
#endif
#define BOARD_ENET1_PHY_LIST \
{ \
{ \
GMII_RTL8211F_NAME, \
GMII_PHYID1_RTL8211F, \
GMII_PHYID2_RTL8211F, \
GMII_RTL8211F_PHYSR_A43, \
2, \
0xffff, \
GMII_RTL8211F_PHYSR_10MBPS, \
GMII_RTL8211F_PHYSR_100MBPS, \
GMII_RTL8211F_PHYSR_DUPLEX, \
22, \
GMII_RTL8211F_PHYSR_1000MBPS, \
GMII_RTL8211F_PHYSR_SPEED_MASK, \
}, \
}
/****************************************************************************
* Public Data
****************************************************************************/