Board should specify multipliers, not bit settings
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1109 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
parent
56f57b5f7a
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ccd2d19e65
@ -81,24 +81,36 @@
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#ifndef CONFIG_STR71X_UART0
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# define APB1EN_UART0 STR71X_APB1_UART0
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#else
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# ifndef CONFIG_STR71X_GPIO0
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# error "CONFIG_STR71X_UART0 requires CONFIG_STR71X_GPIO0"
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# endif
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# define APB1EN_UART0 (0)
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#endif
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#ifndef CONFIG_STR71X_UART1
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# define APB1EN_UART1 STR71X_APB1_UART1
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#else
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# ifndef CONFIG_STR71X_GPIO0
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# error "CONFIG_STR71X_UART1 requires CONFIG_STR71X_GPIO0"
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# endif
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# define APB1EN_UART1 (0)
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#endif
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#ifndef CONFIG_STR71X_UART2
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# define APB1EN_UART2 STR71X_APB1_UART2
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#else
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# ifndef CONFIG_STR71X_GPIO0
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# error "CONFIG_STR71X_UART2 requires CONFIG_STR71X_GPIO0"
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# endif
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# define APB1EN_UART2 (0)
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#endif
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#ifndef CONFIG_STR71X_UART3
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# define APB1EN_UART3 STR71X_APB1_UART3
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#else
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# ifndef CONFIG_STR71X_GPIO0
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# error "CONFIG_STR71X_UART3 requires CONFIG_STR71X_GPIO0"
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# endif
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# define APB1EN_UART3 (0)
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#endif
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@ -206,6 +218,103 @@
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APB2EN_ADC12|APB2EN_CKOUT|APB2EN_TIM0|APB2EN_TIM1|\
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APB2EN_TIM2|APB2EN_TIM3|APB2EN_RTC|APB2EN_EIC)
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#if STR71X_PLL1OUT_MUL == 12
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# define PLL1MUL STR71X_RCCUPLL1CR_MUL12
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#elif STR71X_PLL1OUT_MUL == 16
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# define PLL1MUL STR71X_RCCUPLL1CR_MUL16
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#elif STR71X_PLL1OUT_MUL == 20
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# define PLL1MUL STR71X_RCCUPLL1CR_MUL20
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#else STR71X_PLL1OUT_MUL == 24
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# define PLL1MUL STR71X_RCCUPLL1CR_MUL24
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#else
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# error "Unsupporetd value for STR71X_PLL1OUT_MUL"
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#endif
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#if STR71X_PLL1OUT_DIV == 1
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# define PLL1DIV STR71X_RCCUPLL1CR_DIV1
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#elif STR71X_PLL1OUT_DIV == 2
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# define PLL1DIV STR71X_RCCUPLL1CR_DIV2
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#elif STR71X_PLL1OUT_DIV == 3
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# define PLL1DIV STR71X_RCCUPLL1CR_DIV3
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#elif STR71X_PLL1OUT_DIV == 4
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# define PLL1DIV STR71X_RCCUPLL1CR_DIV4
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#elif STR71X_PLL1OUT_DIV == 5
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# define PLL1DIV STR71X_RCCUPLL1CR_DIV5
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#elif STR71X_PLL1OUT_DIV == 6
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# define PLL1DIV STR71X_RCCUPLL1CR_DIV6
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#elif STR71X_PLL1OUT_DIV == 7
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# define PLL1DIV STR71X_RCCUPLL1CR_DIV7
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#else
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# error "Unsupported value for STR71X_PLL1OUT_DIV"
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#endif
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#if STR71X_APB1_DIV == 1
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# define APB1DIV STR71X_PCUPDIVR_APB1DIV1
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#elif STR71X_APB1_DIV == 2
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# define APB1DIV STR71X_PCUPDIVR_APB1DIV2
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#elif STR71X_APB1_DIV == 4
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# define APB1DIV STR71X_PCUPDIVR_APB1DIV4
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#elif STR71X_APB1_DIV == 8
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# define APB1DIV STR71X_PCUPDIVR_APB1DIV8
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#else
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# error "Unsupported value for STR71X_APB1_DIV"
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#endif
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#if STR71X_APB2_DIV == 1
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# define APB2DIV STR71X_PCUPDIVR_APB2DIV1
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#elif STR71X_APB2_DIV == 2
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# define APB2DIV STR71X_PCUPDIVR_APB2DIV2
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#elif STR71X_APB2_DIV == 4
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# define APB2DIV STR71X_PCUPDIVR_APB2DIV4
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#elif STR71X_APB2_DIV == 8
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# define APB2DIV STR71X_PCUPDIVR_APB2DIV8
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#else
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# error "Unsupported value for STR71X_APB2_DIV"
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#endif
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#if STR71X_MCLK_DIV == 1
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# define MCLKDIV STR71X_PCUMDIVR_DIV1
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#elif STR71X_MCLK_DIV == 2
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# define MCLKDIV STR71X_PCUMDIVR_DIV2
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#elif STR71X_MCLK_DIV == 4
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# define MCLKDIV STR71X_PCUMDIVR_DIV4
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#elif STR71X_MCLK_DIV == 8
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# define MCLKDIV STR71X_PCUMDIVR_DIV8
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#else
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# error "Unsupported value for STR71X_MCLK_DIV"
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#endif
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#if STR71X_PLL2OUT_MUL == 12
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# define PLL2MUL STR71X_PCUPPL2CR_MUL12
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#elif STR71X_PLL2OUT_MUL == 16
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# define PLL2MUL STR71X_PCUPPL2CR_MUL16
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#elif STR71X_PLL2OUT_MUL == 20
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# define PLL2MUL STR71X_PCUPPL2CR_MUL20
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#else STR71X_PLL2OUT_MUL == 28
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# define PLL2MUL STR71X_PCUPPL2CR_MUL28
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#else
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# error "Unsupporetd value for STR71X_PLL2OUT_MUL"
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#endif
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#if STR71X_PLL2OUT_DIV == 1
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# define PLL2DIV STR71X_PCUPPL2CR_DIV1
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#elif STR71X_PLL2OUT_DIV == 2
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# define PLL2DIV STR71X_PCUPPL2CR_DIV2
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#elif STR71X_PLL2OUT_DIV == 3
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# define PLL2DIV STR71X_PCUPPL2CR_DIV3
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#elif STR71X_PLL2OUT_DIV == 4
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# define PLL2DIV STR71X_PCUPPL2CR_DIV4
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#elif STR71X_PLL2OUT_DIV == 5
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# define PLL2DIV STR71X_PCUPPL2CR_DIV5
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#elif STR71X_PLL2OUT_DIV == 6
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# define PLL2DIV STR71X_PCUPPL2CR_DIV6
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#elif STR71X_PLL2OUT_DIV == 7
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# define PLL2DIV STR71X_PCUPPL2CR_DIV7
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#else
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# error "Unsupported value for STR71X_PLL2OUT_DIV"
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#endif
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/********************************************************************************
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* Private Types
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********************************************************************************/
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@ -246,14 +355,14 @@ void str71x_prccuinit(void)
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reg16 = getreg16(STR71X_PCU_PDIVR);
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reg16 &= ~(STR71X_PCUPDIVR_FACT1MASK|STR71X_PCUPDIVR_FACT2MASK);
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reg16 |= (STR71X_APB1_DIV|STR71X_APB2_DIV
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reg16 |= (APB1DIV|APB2DIV);
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putreg16(reg16, STR71X_PCU_PDIVR);
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/* Configure the main system clock (MCLK) divider with value from board.h */
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reg16 = getreg16(STR71X_PCU_MDIVR);
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reg16 &= ~STR71X_PCUMDIVR_FACTMASK;
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reg16 |= STR71X_MCLK_DIV
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reg16 |= MCLKDIV;
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purreg16(reg16 , STR71X_PCU_MDIVR);
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/* Turn off the PLL1 by setting bits DX[2:0] */
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@ -266,9 +375,9 @@ void str71x_prccuinit(void)
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*/
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#if STR71X_PLL1_CLK2 > 3000000
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putreg32(STR71X_PLL1OUT_MUL|STR71X_PLL1OUT_DIV, STR71X_RCCU_PLL1CR);
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putreg32(PLL1MUL|PLL1DIV, STR71X_RCCU_PLL1CR);
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#else
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putreg32(STR71X_PLL1OUT_MUL|STR71X_PLL1OUT_DIV|STR71X_RCCUPLL1CR_FREFRANGE, STR71X_RCCU_PLL1CR);
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putreg32(PLL1MUL|PLL1DIV|STR71X_RCCUPLL1CR_FREFRANGE, STR71X_RCCU_PLL1CR);
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#endif
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/* Wait for the PLL to lock */
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@ -307,7 +416,7 @@ void str71x_prccuinit(void)
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#if defined(CONFIG_STR71X_HDLC) || (defined(CONFIG_STR71X_USB) && defined(STR71X_USBIN_PLL2))
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reg16 = getreg16(STR71X_PCU_PLL2CR);
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reg16 &= ~(STR71X_PCUPPL2CR_MXMASK|STR71X_PCUPPL2CR_DXMASK);
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reg16 |= (STR71X_PLL2OUT_MUL|STR71X_PLL2OUT_DIV);
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reg16 |= (PLL2MUL|PLL2DIV);
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/* Set the PLL2 FRQRNG bit according to the PLL2 input frequency */
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@ -103,12 +103,12 @@
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* Main system clock: MCLK = RCLK = 32MHz
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*/
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#undef STR71X_PLL1IN_DIV2 /* Don't divide main OSC by two */
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#define STR71X_PLL1OUT_MUL STR71X_RCCUPLL1CR_MUL16 /* PLL1OUT = 16 * CLK2 */
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#define STR71X_PLL1OUT_DIV STR71X_RCCUPLL1CR_DIV2 /* PLL1OUT = CLK2 / 2 */
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#define STR71X_APB1_DIV STR71X_PCUPDIVR_APB1DIV1 /* PCLK1 = RCLK */
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#define STR71X_APB2_DIV STR71X_PCUPDIVR_APB1DIV1 /* PCLK2 = RCLK */
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#define STR71X_MCLK_DIV STR71X_PCUMDIVR_DIV1 /* MCLK = RCLK */
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#undef STR71X_PLL1IN_DIV2 /* Don't divide main OSC by two */
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#define STR71X_PLL1OUT_MUL 16 /* PLL1OUT = 16 * CLK2 */
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#define STR71X_PLL1OUT_DIV 2 /* PLL1OUT = CLK2 / 2 */
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#define STR71X_APB1_DIV 1 /* PCLK1 = RCLK */
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#define STR71X_APB2_DIV 1 /* PCLK2 = RCLK */
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#define STR71X_MCLK_DIV 1 /* MCLK = RCLK */
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/* PLL2 Setup -- only needed for HDLC or USB
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*
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@ -117,20 +117,20 @@
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* USB clock = 12 * HCLK / 1 = 48 MHz
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*/
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#undef STR71X_USBIN_PLL2 /* USB input is USB clock */
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#define STR71X_PLL2OUT_MUL STR71X_PCUPPL2CR_MUL12 /* PLL2OUT = 12 * HCLK */
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#define STR71X_PLL2OUT_DIV STR71X_PCUPPL2CR_DIV1 /* PLL2OUT = HCLK / 1 */
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#undef STR71X_USBIN_PLL2 /* USB input is USB clock */
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#define STR71X_PLL2OUT_MUL 12 /* PLL2OUT = 12 * HCLK */
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#define STR71X_PLL2OUT_DIV 1 /* PLL2OUT = HCLK / 1 */
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/* LED definitions **********************************************************/
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 1
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#define LED_IRQSENABLED 2
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#define LED_STACKCREATED 3
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#define LED_INIRQ 4
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#define LED_SIGNAL 5
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#define LED_ASSERTION 6
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#define LED_PANIC 7
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#define LED_STARTED 0
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#define LED_HEAPALLOCATE 1
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#define LED_IRQSENABLED 2
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#define LED_STACKCREATED 3
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#define LED_INIRQ 4
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#define LED_SIGNAL 5
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#define LED_ASSERTION 6
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#define LED_PANIC 7
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/****************************************************************************
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* Inline Functions
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