STM32F7: Add SPI driver. DMA not yet supported.
This commit is contained in:
David Sidrane
Gregory Nutt
parent
189b0d004f
commit
ccfcb12ef7
@ -1613,6 +1613,25 @@ config STM32F7_SERIALBRK_BSDCOMPAT
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endmenu # U[S]ART Configuration
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menu "SPI Configuration"
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depends on STM32F7_SPI
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config STM32F7_SPI_INTERRUPTS
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bool "Interrupt driver SPI"
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default n
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---help---
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Select to enable interrupt driven SPI support. Non-interrupt-driven,
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poll-waiting is recommended if the interrupt rate would be to high in
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the interrupt driven case.
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config STM32F7_SPI_DMA
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bool "SPI DMA"
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default n
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---help---
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Use DMA to improve SPI transfer performance. Cannot be used with STM32F7_SPI_INTERRUPT.
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endmenu # "SPI Configuration"
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config STM32F7_CUSTOM_CLOCKCONFIG
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bool "Custom clock configuration"
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default n
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@ -1628,6 +1647,18 @@ config STM32F7_DTCM_PROCFS
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will provide statistics about DTCM memory use similar to what you
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would get from mallinfo() for the user heap.
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config STM32F7_DMACAPABLE
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bool "Workaround non-DMA capable memory"
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depends on ARCH_DMA
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default y if !STM32_CCMEXCLUDE
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default n if STM32_CCMEXCLUDE
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---help---
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This option enables the DMA interface stm32_dmacapable that can be
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used to check if it is possible to do DMA from the selected address.
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Drivers then may use this information to determine if they should
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attempt the DMA or fall back to a different transfer method.
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if STM32F7_ETHMAC
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menu "Ethernet MAC configuration"
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@ -145,6 +145,10 @@ CHIP_CSRCS += stm32_exti_alarm.c
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endif
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endif
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ifeq ($(CONFIG_STM32F7_SPI),y)
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CHIP_CSRCS += stm32_spi.c
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endif
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ifeq ($(CONFIG_STM32F7_ETHMAC),y)
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CHIP_CSRCS += stm32_ethernet.c
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endif
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258
arch/arm/src/stm32f7/chip/stm32_spi.h
Normal file
258
arch/arm/src/stm32f7/chip/stm32_spi.h
Normal file
@ -0,0 +1,258 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32_spi.h
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Authors: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H
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#define __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Maximum allowed speed as per data sheet for all SPIs (both pclk1 and pclk2)*/
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#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
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# define STM32_SPI_CLK_MAX 50000000UL
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#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
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# define STM32_SPI_CLK_MAX 54000000UL
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#endif
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/* Register Offsets *****************************************************************/
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#define STM32_SPI_CR1_OFFSET 0x0000 /* SPI Control Register 1 (16-bit) */
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#define STM32_SPI_CR2_OFFSET 0x0004 /* SPI control register 2 (16-bit) */
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#define STM32_SPI_SR_OFFSET 0x0008 /* SPI status register (16-bit) */
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#define STM32_SPI_DR_OFFSET 0x000c /* SPI data register (16-bit) */
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#define STM32_SPI_CRCPR_OFFSET 0x0010 /* SPI CRC polynomial register (16-bit) */
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#define STM32_SPI_RXCRCR_OFFSET 0x0014 /* SPI Rx CRC register (16-bit) */
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#define STM32_SPI_TXCRCR_OFFSET 0x0018 /* SPI Tx CRC register (16-bit) */
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#define STM32_SPI_I2SCFGR_OFFSET 0x001c /* I2S configuration register */
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#define STM32_SPI_I2SPR_OFFSET 0x0020 /* I2S prescaler register */
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/* Register Addresses ***************************************************************/
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#if STM32F7_NSPI > 0
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# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
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# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
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# define STM32_SPI1_SR (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
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# define STM32_SPI1_DR (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
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# define STM32_SPI1_CRCPR (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
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# define STM32_SPI1_RXCRCR (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
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# define STM32_SPI1_TXCRCR (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
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#endif
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#if STM32F7_NSPI > 1
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# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
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# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
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# define STM32_SPI2_SR (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
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# define STM32_SPI2_DR (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
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# define STM32_SPI2_CRCPR (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
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# define STM32_SPI2_RXCRCR (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
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# define STM32_SPI2_TXCRCR (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
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# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET)
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# define STM32_SPI2_I2SPR (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET)
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#endif
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#if STM32F7_NSPI > 2
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# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
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# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
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# define STM32_SPI3_SR (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
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# define STM32_SPI3_DR (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET)
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# define STM32_SPI3_CRCPR (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET)
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# define STM32_SPI3_RXCRCR (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
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# define STM32_SPI3_TXCRCR (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
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# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET)
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# define STM32_SPI3_I2SPR (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET)
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#endif
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#if STM32F7_NSPI > 3
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# define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET)
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# define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET)
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# define STM32_SPI4_SR (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET)
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# define STM32_SPI4_DR (STM32_SPI4_BASE+STM32_SPI_DR_OFFSET)
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# define STM32_SPI4_CRCPR (STM32_SPI4_BASE+STM32_SPI_CRCPR_OFFSET)
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# define STM32_SPI4_RXCRCR (STM32_SPI4_BASE+STM32_SPI_RXCRCR_OFFSET)
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# define STM32_SPI4_TXCRCR (STM32_SPI4_BASE+STM32_SPI_TXCRCR_OFFSET)
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# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET)
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# define STM32_SPI4_I2SPR (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET)
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#endif
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#if STM32F7_NSPI > 4
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# define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET)
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# define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET)
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# define STM32_SPI5_SR (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET)
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# define STM32_SPI5_DR (STM32_SPI5_BASE+STM32_SPI_DR_OFFSET)
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# define STM32_SPI5_CRCPR (STM32_SPI5_BASE+STM32_SPI_CRCPR_OFFSET)
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# define STM32_SPI5_RXCRCR (STM32_SPI5_BASE+STM32_SPI_RXCRCR_OFFSET)
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# define STM32_SPI5_TXCRCR (STM32_SPI5_BASE+STM32_SPI_TXCRCR_OFFSET)
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# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET)
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# define STM32_SPI5_I2SPR (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET)
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#endif
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#if STM32F7_NSPI > 5
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# define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET)
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# define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET)
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# define STM32_SPI6_SR (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET)
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# define STM32_SPI6_DR (STM32_SPI6_BASE+STM32_SPI_DR_OFFSET)
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# define STM32_SPI6_CRCPR (STM32_SPI6_BASE+STM32_SPI_CRCPR_OFFSET)
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# define STM32_SPI6_RXCRCR (STM32_SPI6_BASE+STM32_SPI_RXCRCR_OFFSET)
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# define STM32_SPI6_TXCRCR (STM32_SPI6_BASE+STM32_SPI_TXCRCR_OFFSET)
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# define STM32_SPI6_I2SCFGR (STM32_SPI6_BASE+STM32_SPI_I2SCFGR_OFFSET)
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# define STM32_SPI6_I2SPR (STM32_SPI6_BASE+STM32_SPI_I2SPR_OFFSET)
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#endif
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/* Register Bitfield Definitions ****************************************************/
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/* SPI Control Register 1 */
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#define SPI_CR1_CPHA (1 << 0) /* Bit 0: Clock Phase */
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#define SPI_CR1_CPOL (1 << 1) /* Bit 1: Clock Polarity */
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#define SPI_CR1_MSTR (1 << 2) /* Bit 2: Master Selection */
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#define SPI_CR1_BR_SHIFT (3) /* Bits 5:3 Baud Rate Control */
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#define SPI_CR1_BR_MASK (7 << SPI_CR1_BR_SHIFT)
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# define SPI_CR1_FPCLCKd2 (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
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# define SPI_CR1_FPCLCKd4 (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
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# define SPI_CR1_FPCLCKd8 (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
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# define SPI_CR1_FPCLCKd16 (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
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# define SPI_CR1_FPCLCKd32 (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
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# define SPI_CR1_FPCLCKd64 (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
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# define SPI_CR1_FPCLCKd128 (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
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# define SPI_CR1_FPCLCKd256 (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
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#define SPI_CR1_SPE (1 << 6) /* Bit 6: SPI Enable */
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#define SPI_CR1_LSBFIRST (1 << 7) /* Bit 7: Frame Format */
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#define SPI_CR1_SSI (1 << 8) /* Bit 8: Internal slave select */
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#define SPI_CR1_SSM (1 << 9) /* Bit 9: Software slave management */
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#define SPI_CR1_RXONLY (1 << 10) /* Bit 10: Receive only */
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#define SPI_CR1_CRCL (1 << 11) /* Bit 11: CRC length */
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#define SPI_CR1_CRCNEXT (1 << 12) /* Bit 12: Transmit CRC next */
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#define SPI_CR1_CRCEN (1 << 13) /* Bit 13: Hardware CRC calculation enable */
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#define SPI_CR1_BIDIOE (1 << 14) /* Bit 14: Output enable in bidirectional mode */
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#define SPI_CR1_BIDIMODE (1 << 15) /* Bit 15: Bidirectional data mode enable */
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/* SPI Control Register 2 */
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#define SPI_CR2_RXDMAEN (1 << 0) /* Bit 0: Rx Buffer DMA Enable */
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#define SPI_CR2_TXDMAEN (1 << 1) /* Bit 1: Tx Buffer DMA Enable */
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#define SPI_CR2_SSOE (1 << 2) /* Bit 2: SS Output Enable */
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#define SPI_CR2_NSSP (1 << 3) /* Bit 3 NSSP: NSS pulse management */
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#define SPI_CR2_FRF (1 << 4) /* Bit 4: Frame format */
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#define SPI_CR2_ERRIE (1 << 5) /* Bit 5: Error interrupt enable */
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#define SPI_CR2_RXNEIE (1 << 6) /* Bit 6: RX buffer not empty interrupt enable */
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#define SPI_CR2_TXEIE (1 << 7) /* Bit 7: Tx buffer empty interrupt enable */
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#define SPI_CR2_DS_SHIFT (8) /* Bits 8-11: Data size */
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#define SPI_CR2_DS_MASK (0xf << SPI_CR2_DS_SHIFT)
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# define SPI_CR2_DS_VAL(bits) (((bits)-1) << SPI_CR2_DS_SHIFT)
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# define SPI_CR2_DS_4BIT SPI_CR2_DS_VAL(4)
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# define SPI_CR2_DS_5BIT SPI_CR2_DS_VAL(5)
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# define SPI_CR2_DS_6BIT SPI_CR2_DS_VAL(6)
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# define SPI_CR2_DS_7BIT SPI_CR2_DS_VAL(7)
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# define SPI_CR2_DS_8BIT SPI_CR2_DS_VAL(8)
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# define SPI_CR2_DS_9BIT SPI_CR2_DS_VAL(9)
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# define SPI_CR2_DS_10BIT SPI_CR2_DS_VAL(10)
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# define SPI_CR2_DS_11BIT SPI_CR2_DS_VAL(11)
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# define SPI_CR2_DS_12BIT SPI_CR2_DS_VAL(12)
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# define SPI_CR2_DS_13BIT SPI_CR2_DS_VAL(13)
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# define SPI_CR2_DS_14BIT SPI_CR2_DS_VAL(14)
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# define SPI_CR2_DS_15BIT SPI_CR2_DS_VAL(15)
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# define SPI_CR2_DS_16BIT SPI_CR2_DS_VAL(16)
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#define SPI_CR2_FRXTH (1 << 12) /* Bit 12: FIFO reception threshold */
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#define SPI_CR2_LDMARX (1 << 13) /* Bit 13: Last DMA transfer for receptione */
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#define SPI_CR2_LDMATX (1 << 14) /* Bit 14: Last DMA transfer for transmission */
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/* SPI status register */
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#define SPI_SR_RXNE (1 << 0) /* Bit 0: Receive buffer not empty */
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#define SPI_SR_TXE (1 << 1) /* Bit 1: Transmit buffer empty */
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#define SPI_SR_CHSIDE (1 << 2) /* Bit 2: Channel side (i2s) */
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#define SPI_SR_UDR (1 << 3) /* Bit 3: Underrun flag (i2s) */
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#define SPI_SR_CRCERR (1 << 4) /* Bit 4: CRC error flag */
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#define SPI_SR_MODF (1 << 5) /* Bit 5: Mode fault */
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#define SPI_SR_OVR (1 << 6) /* Bit 6: Overrun flag */
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#define SPI_SR_BSY (1 << 7) /* Bit 7: Busy flag */
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#define SPI_SR_FRE (1 << 8) /* Bit 8: Frame format error */
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#define SPI_SR_FRLVL_SHIFT (9) /* Bits 9-10: FIFO reception level */
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#define SPI_SR_FRLVL_MASK (0x3 << SPI_SR_FRLVL_SHIFT)
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# define SPI_SR_FRLVL_EMPTY (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
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# define SPI_SR_FRLVL_QUARTER (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
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# define SPI_SR_FRLVL_HALF (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
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# define SPI_SR_FRLVL_FULL (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
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#define SPI_SR_FTLVL_SHIFT (11) /* Bits 11-12: FIFO transmission level */
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#define SPI_SR_FTLVL_MASK (0x3 << SPI_SR_FTLVL_SHIFT)
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# define SPI_SR_FTLVL_EMPTY (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
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# define SPI_SR_FTLVL_QUARTER (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
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# define SPI_SR_FTLVL_HALF (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
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# define SPI_SR_FTLVL_FULL (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
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/* I2S configuration register */
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#define SPI_I2SCFGR_CHLEN (1 << 0) /* Bit 0: Channel length (number of bits per audio channel) */
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#define SPI_I2SCFGR_DATLEN_SHIFT (1) /* Bit 1-2: Data length to be transferred */
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#define SPI_I2SCFGR_DATLEN_MASK (3 << SPI_I2SCFGR_DATLEN_SHIFT)
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# define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */
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# define SPI_I2SCFGR_DATLEN_8BIT (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */
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# define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */
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#define SPI_I2SCFGR_CKPOL (1 << 3) /* Bit 3: Steady state clock polarity */
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#define SPI_I2SCFGR_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */
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#define SPI_I2SCFGR_I2SSTD_MASK (3 << SPI_I2SCFGR_I2SSTD_SHIFT)
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# define SPI_I2SCFGR_I2SSTD_PHILLIPS (00 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */
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# define SPI_I2SCFGR_I2SSTD_MSB (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */
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# define SPI_I2SCFGR_I2SSTD_LSB (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */
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# define SPI_I2SCFGR_I2SSTD_PCM (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */
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#define SPI_I2SCFGR_PCMSYNC (1 << 7) /* Bit 7: PCM frame synchronization */
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#define SPI_I2SCFGR_I2SCFG_SHIFT (8) /* Bit 8-9: I2S configuration mode */
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#define SPI_I2SCFGR_I2SCFG_MASK (3 << SPI_I2SCFGR_I2SCFG_SHIFT)
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# define SPI_I2SCFGR_I2SCFG_STX (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */
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# define SPI_I2SCFGR_I2SCFG_SRX (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */
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# define SPI_I2SCFGR_I2SCFG_MTX (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */
|
||||
# define SPI_I2SCFGR_I2SCFG_MRX (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */
|
||||
#define SPI_I2SCFGR_I2SE (1 << 10) /* Bit 10: I2S Enable */
|
||||
#define SPI_I2SCFGR_I2SMOD (1 << 11) /* Bit 11: I2S mode selection */
|
||||
#define SPI_I2SCFGR_ASTRTEN (1 << 12) /* Bit 12: Asynchronous start enable */
|
||||
|
||||
/* I2S prescaler register */
|
||||
|
||||
#define SPI_I2SPR_I2SDIV_SHIFT (0) /* Bit 0-7: I2S Linear prescaler */
|
||||
#define SPI_I2SPR_I2SDIV_MASK (0xff << SPI_I2SPR_I2SDIV_SHIFT)
|
||||
#define SPI_I2SPR_ODD (1 << 8) /* Bit 8: Odd factor for the prescaler */
|
||||
#define SPI_I2SPR_MCKOE (1 << 9) /* Bit 9: Master clock output enable */
|
||||
|
||||
#endif /* __ARCH_ARM_STC_STM32F7_CHIP_STM32_SPI_H */
|
||||
1832
arch/arm/src/stm32f7/stm32_spi.c
Normal file
1832
arch/arm/src/stm32f7/stm32_spi.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -2,7 +2,8 @@
|
||||
* arch/arm/src/stm32f7/stm32_spi.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@ -33,8 +34,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_STC_STM32F7_STM32_SPI_H
|
||||
#define __ARCH_ARM_STC_STM32F7_STM32_SPI_H
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_SPI_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_STM32_SPI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@ -45,7 +46,7 @@
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
//#include "chip/stm32_spi.h"
|
||||
#include "chip/stm32_spi.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
@ -110,37 +111,37 @@ FAR struct spi_dev_s *stm32_spibus_initialize(int bus);
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32_SPI1
|
||||
#ifdef CONFIG_STM32F7_SPI1
|
||||
void stm32_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
int stm32_spi1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI2
|
||||
#ifdef CONFIG_STM32F7_SPI2
|
||||
void stm32_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
int stm32_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI3
|
||||
#ifdef CONFIG_STM32F7_SPI3
|
||||
void stm32_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
int stm32_spi3cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI4
|
||||
#ifdef CONFIG_STM32F7_SPI4
|
||||
void stm32_spi4select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
int stm32_spi4cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI5
|
||||
#ifdef CONFIG_STM32F7_SPI5
|
||||
void stm32_spi5select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
uint8_t stm32_spi5status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
int stm32_spi5cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI6
|
||||
#ifdef CONFIG_STM32F7_SPI6
|
||||
void stm32_spi6select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
uint8_t stm32_spi6status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
int stm32_spi6cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
@ -167,32 +168,32 @@ int stm32_spi6cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SPI_CALLBACK
|
||||
#ifdef CONFIG_STM32_SPI1
|
||||
#ifdef CONFIG_STM32F7_SPI1
|
||||
int stm32_spi1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI2
|
||||
#ifdef CONFIG_STM32F7_SPI2
|
||||
int stm32_spi2register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI3
|
||||
#ifdef CONFIG_STM32F7_SPI3
|
||||
int stm32_spi3register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI4
|
||||
#ifdef CONFIG_STM32F7_SPI4
|
||||
int stm32_spi4register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI5
|
||||
#ifdef CONFIG_STM32F7_SPI5
|
||||
int stm32_spi5register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_SPI6
|
||||
#ifdef CONFIG_STM32F7_SPI6
|
||||
int stm32_spi6register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
@ -204,5 +205,5 @@ int stm32_spi6register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_STC_STM32F7_STM32_SPI_H */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_SPI_H */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user