STM32F0: Fix I2C frequency table
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@ -1037,88 +1037,45 @@ static void stm32f0_i2c_setclock(FAR struct stm32f0_i2c_priv_s *priv, uint32_t f
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if (frequency == 10000)
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{
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#if 1
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/* 10 KHz values from I2C timing tool with clock 80mhz */
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/* 10 KHz values from I2C timing tool with clock 8mhz */
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presc = 0x0b; /* PRESC - (+1) prescale I2CCLK */
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scl_l_period = 0xff; /* SCLL - SCL low period in master mode */
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scl_h_period = 0xba; /* SCLH - SCL high period in master mode */
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h_time = 0x00; /* SDADEL - (+1) data hold time after SCL falling edge */
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s_time = 0x01; /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
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#else
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/* 10 KHz values from datasheet with clock 8mhz */
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presc = 0x03; /* PRESC - (+1) prescale I2CCLK */
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presc = 0x01; /* PRESC - (+1) prescale I2CCLK */
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scl_l_period = 0xc7; /* SCLL - SCL low period in master mode */
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scl_h_period = 0xc3; /* SCLH - SCL high period in master mode */
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h_time = 0x02; /* SDADEL - (+1) data hold time after SCL falling edge */
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s_time = 0x04; /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
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#endif
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}
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else if (frequency == 100000)
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{
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#if 1
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/* 100 KHz values from I2C timing tool with clock 80mhz */
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/* 100 KHz values from I2C timing tool with clock 8mhz */
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presc = 0x01; /* PRESC - (+1) prescale I2CCLK */
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scl_l_period = 0xe7; /* SCLL - SCL low period in master mode */
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scl_h_period = 0x9b; /* SCLH - SCL high period in master mode */
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h_time = 0x00; /* SDADEL - (+1) data hold time after SCL falling edge */
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s_time = 0x0d; /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
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#else
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/* 100 KHz values from datasheet with clock 8mhz */
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presc = 0x01;
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scl_l_period = 0x13;
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scl_h_period = 0x0f;
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h_time = 0x02;
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s_time = 0x04;
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#endif
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scl_l_period = 0x13; /* SCLL - SCL low period in master mode */
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scl_h_period = 0x0f; /* SCLH - SCL high period in master mode */
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h_time = 0x02; /* SDADEL - (+1) data hold time after SCL falling edge */
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s_time = 0x04; /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
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}
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else if (frequency == 400000)
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{
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#if 1
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/* 400 KHz values from I2C timing tool for clock of 80mhz */
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/* 400 KHz values from I2C timing tool for clock of 8mhz */
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presc = 0x01; /* PRESC - (+1) prescale I2CCLK */
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scl_l_period = 0x43; /* SCLL - SCL low period in master mode */
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scl_h_period = 0x13; /* SCLH - SCL high period in master mode */
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h_time = 0x00; /* SDADEL - (+1) data hold time after SCL falling edge */
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s_time = 0x07; /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
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#else
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/* 400 KHz values from datasheet for clock of 8mhz */
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presc = 0x00;
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scl_l_period = 0x09;
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scl_h_period = 0x03;
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h_time = 0x01;
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s_time = 0x03;
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#endif
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presc = 0x00; /* PRESC - (+1) prescale I2CCLK */
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scl_l_period = 0x09; /* SCLL - SCL low period in master mode */
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scl_h_period = 0x03; /* SCLH - SCL high period in master mode */
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h_time = 0x01; /* SDADEL - (+1) data hold time after SCL falling edge */
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s_time = 0x03; /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
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}
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else
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{
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#if 1
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/* 1000 KHhz values from I2C timing tool for clock of 80mhz */
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/* 1000 KHhz values from I2C timing tool for clock of 8mhz */
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presc = 0x01; /* PRESC - (+1) prescale I2CCLK */
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scl_l_period = 0x14; /* SCLL - SCL low period in master mode */
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scl_h_period = 0x13; /* SCLH - SCL high period in master mode */
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presc = 0x00; /* PRESC - (+1) prescale I2CCLK */
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scl_l_period = 0x06; /* SCLL - SCL low period in master mode */
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scl_h_period = 0x03; /* SCLH - SCL high period in master mode */
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h_time = 0x00; /* SDADEL - (+1) data hold time after SCL falling edge */
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s_time = 0x05; /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
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s_time = 0x01; /* SCLDEL - (+1) data setup time from SDA edge to SCL rising edge */
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frequency = 1000000;
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#else
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/* 500 KHhz values from datasheet for clock of 8mhz */
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presc = 0x00;
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scl_l_period = 0x06;
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scl_h_period = 0x03;
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h_time = 0x00;
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s_time = 0x01;
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frequency = 500000;
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#endif
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}
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uint32_t timingr =
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