GPDMA driver for the LPC43xx. The GPDMA block is basically the same as the LPC17xx. Only the clock configuration is different and LPC43xx has four different DMA request sources, where LPC17xx has only two.
This commit is contained in:
parent
241176abc3
commit
cd119ad544
@ -70,12 +70,12 @@
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#define LPC43_GPDMA_CONTROL_CHOFFSET 0x000c /* DMA Channel Control Register */
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#define LPC43_GPDMA_CONFIG_CHOFFSET 0x0010 /* DMA Channel Configuration Register */
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#define LPC43_GPDMA_CHOFFSET(n) (0x0100 ((n) << 5))
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#define LPC43_GPDMA_CHOFFSET(n) (0x0100 + ((n) << 5))
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#define LPC43_GPDMA_SRCADDR_OFFSET(n) (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_SRCADDR_CHOFFSET)
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#define LPC43_GPDMA_DESTADDR_OFFSET(n) (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_DESTADDR_CHOFFSET)
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#define LPC43_GPDMA_LLI_OFFSET(n) (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_LLI_CHOFFSET)
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#define LPC43_GPDMA_CONTROL_OFFSET(n) (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_CONTROL_CHOFFSET)
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#define LPC43_GPDMA_CONFIG_OFFSET(n) (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_CONFIG_CHOFFSET)
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#define LPC43_GPDMA_CONFIG_OFFSET_(n) (LPC43_GPDMA_CHOFFSET(n)+LPC43_GPDMA_CONFIG_CHOFFSET)
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#define LPC43_GPDMA_SRCADDR0_OFFSET 0x0100 /* DMA Channel 0 Source Address Register */
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#define LPC43_GPDMA_DESTADDR0_OFFSET 0x0104 /* DMA Channel 0 Destination Address Register */
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@ -149,7 +149,7 @@
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#define LPC43_GPDMA_DESTADDR(n) (LPC43_DMA_BASE+LPC43_GPDMA_DESTADDR_OFFSET(n))
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#define LPC43_GPDMA_LLI(n) (LPC43_DMA_BASE+LPC43_GPDMA_LLI_OFFSET(n))
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#define LPC43_GPDMA_CONTROL(n) (LPC43_DMA_BASE+LPC43_GPDMA_CONTROL_OFFSET(n))
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#define LPC43_GPDMA_CONFIG(n) (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG_OFFSET(n))
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#define LPC43_GPDMA_CONFIG_(n) (LPC43_DMA_BASE+LPC43_GPDMA_CONFIG_OFFSET_(n))
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#define LPC43_GPDMA_SRCADDR0 (LPC43_DMA_BASE+LPC43_GPDMA_SRCADDR0_OFFSET)
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#define LPC43_GPDMA_DESTADDR0 (LPC43_DMA_BASE+LPC43_GPDMA_DESTADDR0_OFFSET)
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@ -203,6 +203,9 @@
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/* Common macros for DMA channel and source bit settings */
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#define DMACH_ALL (0xff)
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#define LPC43_NDMACH 8 /* Eight DMA channels */
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#define LPC43_NDMAREQ (16) /* The number of DMA requests */
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#define GPDMA_CHANNEL(n) (1 << (n)) /* Bits 0-7 correspond to DMA channel 0-7 */
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#define GPDMA_SOURCE(n) (1 << (n)) /* Bits 0-15 correspond to DMA source 0-15 */
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#define GPDMA_REQUEST(n) (1 << (n)) /* Bits 0-15 correspond to DMA request 0-15 */
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@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/lpc43xx/lpc43_gpdma.c
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*
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* Copyright (C) 2012 Gregory Nutt. All rights reserved.
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@ -52,11 +52,218 @@
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#include "chip.h"
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#include "lpc43_syscon.h"
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#include "lpc43_ccu.h"
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#include "lpc43_creg.h"
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#include "lpc43_gpdma.h"
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#ifdef CONFIG_LPC43_GPDMA
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* This structure represents the state of one DMA channel */
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struct lpc43_dmach_s
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{
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uint8_t chn; /* The DMA channel number */
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bool inuse; /* True: The channel is in use */
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bool inprogress; /* True: DMA is in progress on this channel */
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uint16_t nxfrs; /* Number of bytes to transfers */
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dma_callback_t callback; /* DMA completion callback function */
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void *arg; /* Argument to pass to the callback function */
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};
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/* This structure represents the state of the LPC43 DMA block */
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struct lpc43_gpdma_s
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{
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sem_t exclsem; /* For exclusive access to the DMA channel list */
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/* This is the state of each DMA channel */
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struct lpc43_dmach_s dmach[LPC43_NDMACH];
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* The state of the LPC43 DMA block */
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static struct lpc43_gpdma_s g_gpdma;
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* If the following value is zero, then there is no DMA in progress. This
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* value is needed in the IDLE loop to determine if the IDLE loop should
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* go into lower power power consumption modes. According to the LPC43xx
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* User Manual: "The DMA controller can continue to work in Sleep mode, and
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* has access to the peripheral SRAMs and all peripheral registers. The
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* flash memory and the Main SRAM are not available in Sleep mode, they are
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* disabled in order to save power."
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*/
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volatile uint8_t g_dma_inprogress;
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: lpc43_dmainprogress
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*
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* Description:
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* Another DMA has started. Increment the g_dma_inprogress counter.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void lpc43_dmainprogress(struct lpc43_dmach_s *dmach)
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{
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irqstate_t flags;
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/* Increment the DMA in progress counter */
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flags = enter_critical_section();
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DEBUGASSERT(!dmach->inprogress && g_dma_inprogress < LPC43_NDMACH);
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g_dma_inprogress++;
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dmach->inprogress = true;
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leave_critical_section(flags);
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}
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/****************************************************************************
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* Name: lpc43_dmadone
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*
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* Description:
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* A DMA has completed. Decrement the g_dma_inprogress counter.
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*
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* This function is called only from lpc43_dmastop which, in turn, will be
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* called either by the user directly, by the user indirectly via
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* lpc43_dmafree(), or from gpdma_interrupt when the transfer completes.
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*
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* NOTE: In the first two cases, we must be able to handle the case where
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* there is no DMA in progress and gracefully ignore the call.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static void lpc43_dmadone(struct lpc43_dmach_s *dmach)
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{
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irqstate_t flags;
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/* Increment the DMA in progress counter */
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flags = enter_critical_section();
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if (dmach->inprogress)
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{
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DEBUGASSERT(g_dma_inprogress > 0);
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dmach->inprogress = false;
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g_dma_inprogress--;
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}
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leave_critical_section(flags);
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}
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/****************************************************************************
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* Name: gpdma_interrupt
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*
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* Description:
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* The common GPDMA interrupt handler.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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static int gpdma_interrupt(int irq, FAR void *context)
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{
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struct lpc43_dmach_s *dmach;
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uint32_t regval;
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uint32_t chbit;
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int result;
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int i;
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/* Check each DMA channel */
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for (i = 0; i < LPC43_NDMACH; i++)
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{
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chbit = GPDMA_CHANNEL((uint32_t)i);
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/* Is there an interrupt pending for this channel? If the bit for
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* this channel is set, that indicates that a specific DMA channel
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* interrupt request is active. The request can be generated from
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* either the error or terminal count interrupt requests.
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*/
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regval = getreg32(LPC43_GPDMA_INTSTAT);
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if ((regval & chbit) != 0)
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{
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/* Yes.. Is this channel assigned? Is there a callback function? */
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dmach = &g_gpdma.dmach[i];
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if (dmach->inuse && dmach->callback)
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{
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/* Yes.. did an error occur? */
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regval = getreg32(LPC43_GPDMA_INTERRSTAT);
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if ((regval & chbit) != 0)
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{
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/* Yes.. report error status */
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result = -EIO;
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}
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/* Then this must be a terminal transfer event */
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else
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{
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/* Let's make sure it is the terminal transfer event. */
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regval = getreg32(LPC43_GPDMA_INTTCSTAT);
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if ((regval & chbit) != 0)
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{
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result = OK;
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}
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/* This should not happen */
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else
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{
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result = -EINVAL;
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}
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}
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/* Perform the callback */
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dmach->callback((DMA_HANDLE)dmach, dmach->arg, result);
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}
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/* Disable this channel, mask any further interrupts for
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* this channel, and clear any pending interrupts.
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*/
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lpc43_dmastop((DMA_HANDLE)dmach);
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}
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}
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return OK;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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@ -68,12 +275,101 @@
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* Initialize the GPDMA subsystem.
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*
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* Returned Value:
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* Zero on success; A negated errno value on failure.
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*
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****************************************************************************/
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void weak_function up_dmainitialize(void)
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{
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uint32_t regval;
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int ret;
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int i;
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/* Enable clocking to the GPDMA block */
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regval = getreg32(LPC43_CCU1_M4_DMA_CFG);
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regval |= CCU_CLK_CFG_RUN;
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putreg32(regval, LPC43_CCU1_M4_DMA_CFG);
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/* Reset all channel configurations */
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for (i = 0; i < LPC43_NDMACH; i++)
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{
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putreg32(0, LPC43_GPDMA_CONFIG_(i));
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}
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/* Clear all DMA interrupts */
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putreg32(DMACH_ALL, LPC43_GPDMA_INTTCCLEAR);
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putreg32(DMACH_ALL, LPC43_GPDMA_INTERRCLR);
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/* Initialize the DMA state structure */
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sem_init(&g_gpdma.exclsem, 0, 1);
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for (i = 0; i < LPC43_NDMACH; i++)
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{
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g_gpdma.dmach[i].chn = i; /* Channel number */
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g_gpdma.dmach[i].inuse = false; /* Channel is not in-use */
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}
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/* Attach and enable the common interrupt handler */
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ret = irq_attach(LPC43M4_IRQ_DMA, gpdma_interrupt);
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if (ret == OK)
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{
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up_enable_irq(LPC43M4_IRQ_DMA);
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}
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/* Enable the DMA controller (for little endian operation) */
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putreg32(GPDMA_CONFIG_ENA, LPC43_GPDMA_CONFIG);
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}
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/****************************************************************************
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* Name: lpc43_dmaconfigure
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*
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* Description:
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* Configure a DMA request. Each DMA request may have four different DMA
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* request sources. This associates one of the sources with a DMA request.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void lpc43_dmainitilaize(void)
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void lpc43_dmaconfigure(uint8_t dmarequest, uint8_t dmasrc)
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{
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uint32_t regval;
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DEBUGASSERT(dmarequest < LPC43_NDMAREQ);
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/* Set or clear the DMASEL bit corresponding to the request number */
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regval = getreg32(LPC43_CREG_DMAMUX);
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switch (dmasrc)
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{
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case 0:
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regval &= ~(3 << dmarequest);
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break;
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case 1:
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regval &= ~(3 << dmarequest);
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regval |= (1 << dmarequest);
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break;
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case 2:
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regval &= ~(3 << dmarequest);
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regval |= (2 << dmarequest);
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break;
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case 3:
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regval |= (3 << dmarequest);
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break;
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}
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putreg32(regval, LPC43_CREG_DMAMUX);
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}
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/****************************************************************************
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@ -92,7 +388,37 @@ void lpc43_dmainitilaize(void)
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DMA_HANDLE lpc43_dmachannel(void)
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{
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return NULL;
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struct lpc43_dmach_s *dmach = NULL;
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int ret;
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int i;
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/* Get exclusive access to the GPDMA state structure */
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do
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{
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ret = sem_wait(&g_gpdma.exclsem);
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DEBUGASSERT(ret == 0 || errno == EINTR);
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}
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while (ret < 0);
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/* Find an available DMA channel */
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for (i = 0; i < LPC43_NDMACH; i++)
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{
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if (!g_gpdma.dmach[i].inuse)
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{
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/* Found one! */
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dmach = &g_gpdma.dmach[i];
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g_gpdma.dmach[i].inuse = true;
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break;
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}
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}
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/* Return what we found (or not) */
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sem_post(&g_gpdma.exclsem);
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return (DMA_HANDLE)dmach;
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}
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/****************************************************************************
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@ -110,6 +436,19 @@ DMA_HANDLE lpc43_dmachannel(void)
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void lpc43_dmafree(DMA_HANDLE handle)
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{
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struct lpc43_dmach_s *dmach = (DMA_HANDLE)handle;
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DEBUGASSERT(dmach && dmach->inuse);
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/* Make sure that the DMA channel was properly stopped */
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lpc43_dmastop(handle);
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/* Mark the channel available. This is an atomic operation and needs no
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* special protection.
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*/
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dmach->inuse = false;
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}
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/****************************************************************************
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@ -123,7 +462,87 @@ void lpc43_dmafree(DMA_HANDLE handle)
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int lpc43_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
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uint32_t srcaddr, uint32_t destaddr, size_t nbytes)
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{
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return -ENOSYS;
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struct lpc43_dmach_s *dmach = (DMA_HANDLE)handle;
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uint32_t chbit;
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uint32_t regval;
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uint32_t base;
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DEBUGASSERT(dmach && dmach->inuse && nbytes < 4096);
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chbit = GPDMA_CHANNEL((uint32_t)dmach->chn);
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base = LPC43_GPDMA_CHANNEL((uint32_t)dmach->chn);
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/* Put the channel in a known state. Zero disables everything */
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putreg32(0, base + LPC43_GPDMA_CONTROL_CHOFFSET);
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putreg32(0, base + LPC43_GPDMA_CONFIG_CHOFFSET);
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/* "Programming a DMA channel
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*
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* 1. "Choose a free DMA channel with the priority needed. DMA channel 0
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* has the highest priority and DMA channel 7 the lowest priority.
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*/
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regval = getreg32(LPC43_GPDMA_ENBLDCHNS);
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if ((regval & chbit) != 0)
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{
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/* There is an active DMA on this channel! */
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return -EBUSY;
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}
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/* 2. "Clear any pending interrupts on the channel to be used by writing
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* to the DMACIntTCClear and DMACIntErrClear register. The previous
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* channel operation might have left interrupt active.
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*/
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putreg32(chbit, LPC43_GPDMA_INTTCCLEAR);
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putreg32(chbit, LPC43_GPDMA_INTERRCLR);
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/* 3. "Write the source address into the DMACCxSrcAddr register. */
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putreg32(srcaddr, base + LPC43_GPDMA_SRCADDR_CHOFFSET);
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/* 4. "Write the destination address into the DMACCxDestAddr register. */
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putreg32(destaddr, base + LPC43_GPDMA_DESTADDR_CHOFFSET);
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/* 5. "Write the address of the next LLI into the DMACCxLLI register. If
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* the transfer comprises of a single packet of data then 0 must be
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* written into this register.
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*/
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putreg32(0, base + LPC43_GPDMA_LLI_CHOFFSET);
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/* 6. "Write the control information into the DMACCxControl register."
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*
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* The caller provides all CONTROL register fields except for the transfer
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* size which is passed as a separate parameter and for the terminal count
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* interrupt enable bit which is controlled by the driver.
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*/
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regval = control & ~(GPDMA_CONTROL_XFRSIZE_MASK | GPDMA_CONTROL_IE);
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regval |= ((uint32_t)nbytes << GPDMA_CONTROL_XFRSIZE_SHIFT);
|
||||
putreg32(regval, base + LPC43_GPDMA_CONTROL_CHOFFSET);
|
||||
|
||||
/* Save the number of transfer to perform for lpc43_dmastart */
|
||||
|
||||
dmach->nxfrs = (uint16_t)nbytes;
|
||||
|
||||
/* 7. "Write the channel configuration information into the DMACCxConfig
|
||||
* register. If the enable bit is set then the DMA channel is
|
||||
* automatically enabled."
|
||||
*
|
||||
* Only the SRCPER, DSTPER, and FCNTRL fields of the CONFIG register
|
||||
* are provided by the caller. Little endian is assumed.
|
||||
*/
|
||||
|
||||
regval = config & (GPDMA_CONFIG_SRCPER_MASK |
|
||||
GPDMA_CONFIG_DESTPER_MASK |
|
||||
GPDMA_CONFIG_FCNTRL_MASK);
|
||||
putreg32(regval, base + LPC43_GPDMA_CONFIG_CHOFFSET);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -136,7 +555,53 @@ int lpc43_dmarxsetup(DMA_HANDLE handle, uint32_t control, uint32_t config,
|
||||
|
||||
int lpc43_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
|
||||
{
|
||||
return -ENOSYS;
|
||||
struct lpc43_dmach_s *dmach = (DMA_HANDLE)handle;
|
||||
uint32_t regval;
|
||||
uint32_t chbit;
|
||||
uint32_t base;
|
||||
|
||||
DEBUGASSERT(dmach && dmach->inuse && callback);
|
||||
|
||||
/* Save the callback information */
|
||||
|
||||
dmach->callback = callback;
|
||||
dmach->arg = arg;
|
||||
|
||||
/* Increment the count of DMAs in-progress. This count will be
|
||||
* decremented when lpc43_dmastop() is called, either by the user,
|
||||
* indirectly via lpc43_dmafree(), or from gpdma_interrupt when the
|
||||
* transfer completes.
|
||||
*/
|
||||
|
||||
lpc43_dmainprogress(dmach);
|
||||
|
||||
/* Clear any pending DMA interrupts */
|
||||
|
||||
chbit = GPDMA_CHANNEL((uint32_t)dmach->chn);
|
||||
putreg32(chbit, LPC43_GPDMA_INTTCCLEAR);
|
||||
putreg32(chbit, LPC43_GPDMA_INTERRCLR);
|
||||
|
||||
/* Enable terminal count interrupt. Note that we need to restore the
|
||||
* number transfers. That is because the value has a different meaning
|
||||
* when it is read.
|
||||
*/
|
||||
|
||||
base = LPC43_GPDMA_CHANNEL((uint32_t)dmach->chn);
|
||||
regval = getreg32(base + LPC43_GPDMA_CONTROL_CHOFFSET);
|
||||
regval &= ~GPDMA_CONTROL_XFRSIZE_MASK;
|
||||
regval |= (GPDMA_CONTROL_IE | ((uint32_t)dmach->nxfrs << GPDMA_CONTROL_XFRSIZE_SHIFT));
|
||||
putreg32(regval, base + LPC43_GPDMA_CONTROL_CHOFFSET);
|
||||
|
||||
/* Enable the channel and unmask terminal count and error interrupts.
|
||||
* According to the user manual, zero masks and one unmasks (hence,
|
||||
* these are really enables).
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LPC43_GPDMA_CONFIG_CHOFFSET);
|
||||
regval |= (GPDMA_CONFIG_ENA | GPDMA_CONFIG_IE | GPDMA_CONFIG_ITC);
|
||||
putreg32(regval, base + LPC43_GPDMA_CONFIG_CHOFFSET);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -147,10 +612,40 @@ int lpc43_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg)
|
||||
* reset and lpc43_dmasetup() must be called before lpc43_dmastart() can be
|
||||
* called again
|
||||
*
|
||||
* This function will be called either by the user directly, by the user
|
||||
* indirectly via lpc43_dmafree(), or from gpdma_interrupt when the
|
||||
* transfer completes.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void lpc43_dmastop(DMA_HANDLE handle)
|
||||
{
|
||||
struct lpc43_dmach_s *dmach = (DMA_HANDLE)handle;
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t chbit;
|
||||
|
||||
DEBUGASSERT(dmach && dmach->inuse);
|
||||
|
||||
/* Disable this channel and mask any further interrupts from the channel.
|
||||
* this channel. The channel is disabled by clearning the channel
|
||||
* enable bit. Any outstanding data in the FIFOs is lost.
|
||||
*/
|
||||
|
||||
regaddr = LPC43_GPDMA_CONFIG_((uint32_t)dmach->chn);
|
||||
regval = getreg32(regaddr);
|
||||
regval &= ~(GPDMA_CONFIG_ENA | GPDMA_CONFIG_IE | GPDMA_CONFIG_ITC);
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
/* Clear any pending interrupts for this channel */
|
||||
|
||||
chbit = GPDMA_CHANNEL((uint32_t)dmach->chn);
|
||||
putreg32(chbit, LPC43_GPDMA_INTTCCLEAR);
|
||||
putreg32(chbit, LPC43_GPDMA_INTERRCLR);
|
||||
|
||||
/* Decrement the count of DMAs in progress */
|
||||
|
||||
lpc43_dmadone(dmach);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -164,6 +659,34 @@ void lpc43_dmastop(DMA_HANDLE handle)
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
void lpc43_dmasample(DMA_HANDLE handle, struct lpc43_dmaregs_s *regs)
|
||||
{
|
||||
struct lpc43_dmach_s *dmach = (DMA_HANDLE)handle;
|
||||
uint32_t base;
|
||||
|
||||
DEBUGASSERT(dmach);
|
||||
|
||||
/* Sample the global DMA registers */
|
||||
|
||||
regs->gbl.intst = getreg32(LPC43_GPDMA_INTSTAT);
|
||||
regs->gbl.inttcstat = getreg32(LPC43_GPDMA_INTTCSTAT);
|
||||
regs->gbl.interrstat = getreg32(LPC43_GPDMA_INTERRSTAT);
|
||||
regs->gbl.rawinttcstat = getreg32(LPC43_GPDMA_RAWINTTCSTAT);
|
||||
regs->gbl.rawinterrstat = getreg32(LPC43_GPDMA_RAWINTERRSTAT);
|
||||
regs->gbl.enbldchns = getreg32(LPC43_GPDMA_ENBLDCHNS);
|
||||
regs->gbl.softbreq = getreg32(LPC43_GPDMA_SOFTBREQ);
|
||||
regs->gbl.softsreq = getreg32(LPC43_GPDMA_SOFTSREQ);
|
||||
regs->gbl.softlbreq = getreg32(LPC43_GPDMA_SOFTLBREQ);
|
||||
regs->gbl.softlsreq = getreg32(LPC43_GPDMA_SOFTLSREQ);
|
||||
regs->gbl.config = getreg32(LPC43_GPDMA_CONFIG);
|
||||
regs->gbl.sync = getreg32(LPC43_GPDMA_SYNC);
|
||||
|
||||
/* Sample the DMA channel registers */
|
||||
|
||||
base = LPC43_GPDMA_CHANNEL((uint32_t)dmach->chn);
|
||||
regs->ch.srcaddr = getreg32(base + LPC43_GPDMA_SRCADDR_CHOFFSET);
|
||||
regs->ch.destaddr = getreg32(base + LPC43_GPDMA_DESTADDR_CHOFFSET);
|
||||
regs->ch.lli = getreg32(base + LPC43_GPDMA_LLI_CHOFFSET);
|
||||
regs->ch.control = getreg32(base + LPC43_GPDMA_CONTROL_CHOFFSET);
|
||||
regs->ch.config = getreg32(base + LPC43_GPDMA_CONFIG_CHOFFSET);
|
||||
}
|
||||
#endif /* CONFIG_DEBUG_DMA */
|
||||
|
||||
@ -178,6 +701,55 @@ void lpc43_dmasample(DMA_HANDLE handle, struct lpc43_dmaregs_s *regs)
|
||||
#ifdef CONFIG_DEBUG_DMA
|
||||
void lpc43_dmadump(DMA_HANDLE handle, const struct lpc43_dmaregs_s *regs, const char *msg)
|
||||
{
|
||||
struct lpc43_dmach_s *dmach = (DMA_HANDLE)handle;
|
||||
uint32_t base;
|
||||
|
||||
DEBUGASSERT(dmach);
|
||||
|
||||
/* Dump the sampled global DMA registers */
|
||||
|
||||
dmainfo("Global GPDMA Registers: %s\n", msg);
|
||||
dmainfo(" INTST[%08x]: %08x\n",
|
||||
LPC43_GPDMA_INTSTAT, regs->gbl.intst);
|
||||
dmainfo(" INTTCSTAT[%08x]: %08x\n",
|
||||
LPC43_GPDMA_INTTCSTAT, regs->gbl.inttcstat);
|
||||
dmainfo(" INTERRSTAT[%08x]: %08x\n",
|
||||
LPC43_GPDMA_INTERRSTAT, regs->gbl.interrstat);
|
||||
dmainfo(" RAWINTTCSTAT[%08x]: %08x\n",
|
||||
LPC43_GPDMA_RAWINTTCSTAT, regs->gbl.rawinttcstat);
|
||||
dmainfo(" RAWINTERRSTAT[%08x]: %08x\n",
|
||||
LPC43_GPDMA_RAWINTERRSTAT, regs->gbl.rawinterrstat);
|
||||
dmainfo(" ENBLDCHNS[%08x]: %08x\n",
|
||||
LPC43_GPDMA_ENBLDCHNS, regs->gbl.enbldchns);
|
||||
dmainfo(" SOFTBREQ[%08x]: %08x\n",
|
||||
LPC43_GPDMA_SOFTBREQ, regs->gbl.softbreq);
|
||||
dmainfo(" SOFTSREQ[%08x]: %08x\n",
|
||||
LPC43_GPDMA_SOFTSREQ, regs->gbl.softsreq);
|
||||
dmainfo(" SOFTLBREQ[%08x]: %08x\n",
|
||||
LPC43_GPDMA_SOFTLBREQ, regs->gbl.softlbreq);
|
||||
dmainfo(" SOFTLSREQ[%08x]: %08x\n",
|
||||
LPC43_GPDMA_SOFTLSREQ, regs->gbl.softlsreq);
|
||||
dmainfo(" CONFIG[%08x]: %08x\n",
|
||||
LPC43_GPDMA_CONFIG, regs->gbl.config);
|
||||
dmainfo(" SYNC[%08x]: %08x\n",
|
||||
LPC43_GPDMA_SYNC, regs->gbl.sync);
|
||||
|
||||
/* Dump the DMA channel registers */
|
||||
|
||||
base = LPC43_GPDMA_CHANNEL((uint32_t)dmach->chn);
|
||||
|
||||
dmainfo("Channel GPDMA Registers: %d\n", dmach->chn);
|
||||
|
||||
dmainfo(" SRCADDR[%08x]: %08x\n",
|
||||
base + LPC43_GPDMA_SRCADDR_CHOFFSET, regs->ch.srcaddr);
|
||||
dmainfo(" DESTADDR[%08x]: %08x\n",
|
||||
base + LPC43_GPDMA_DESTADDR_CHOFFSET, regs->ch.destaddr);
|
||||
dmainfo(" LLI[%08x]: %08x\n",
|
||||
base + LPC43_GPDMA_LLI_CHOFFSET, regs->ch.lli);
|
||||
dmainfo(" CONTROL[%08x]: %08x\n",
|
||||
base + LPC43_GPDMA_CONTROL_CHOFFSET, regs->ch.control);
|
||||
dmainfo(" CONFIG[%08x]: %08x\n",
|
||||
base + LPC43_GPDMA_CONFIG_CHOFFSET, regs->ch.config);
|
||||
}
|
||||
#endif /* CONFIG_DEBUG_DMA */
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user