stm32_hrtim: ADC triggering and DAC synch events
This commit is contained in:
parent
96e639262a
commit
cd30545cd9
@ -238,6 +238,8 @@ struct stm32_hrtim_timcmn_s
|
||||
* that drives the timer module.
|
||||
*/
|
||||
uint8_t mode; /* Timer mode */
|
||||
uint8_t dac:2; /* DAC triggering */
|
||||
uint8_t reserved:6;
|
||||
#ifdef HRTIM_HAVE_INTERRUPTS
|
||||
uint16_t irq; /* interrupts configuration */
|
||||
#endif
|
||||
@ -370,6 +372,24 @@ struct stm32_hrtim_eev_s
|
||||
};
|
||||
#endif
|
||||
|
||||
/* Structure describes HRTIM ADC triggering configuration */
|
||||
|
||||
struct stm32_hrtim_adc_s
|
||||
{
|
||||
#ifdef CONFIG_STM32_HRTIM_ADC_TRG1
|
||||
uint32_t trg1;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_HRTIM_ADC_TRG2
|
||||
uint32_t trg2;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_HRTIM_ADC_TRG3
|
||||
uint32_t trg3;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_HRTIM_ADC_TRG4
|
||||
uint32_t trg4;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* This structure describes the configuration of HRTIM device */
|
||||
|
||||
struct stm32_hrtim_s
|
||||
@ -392,10 +412,13 @@ struct stm32_hrtim_s
|
||||
struct stm32_hrtim_tim_s *time; /* HRTIM Timer E */
|
||||
#endif
|
||||
#ifdef HRTIM_HAVE_FAULTS
|
||||
struct stm32_hrtim_faults_s *flt;
|
||||
struct stm32_hrtim_faults_s *flt; /* Faults configuration */
|
||||
#endif
|
||||
#ifdef HRTIM_HAVE_EEV
|
||||
struct stm32_hrtim_eev_s *eev;
|
||||
struct stm32_hrtim_eev_s *eev; /* External Events configuration */
|
||||
#endif
|
||||
#ifdef HRTIM_HAVE_ADC
|
||||
struct stm32_hrtim_adc_s *adc; /* ADC triggering configuration */
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_HRTIM_CMN_IRQ
|
||||
uint32_t irq; /* Common interrupts configuration */
|
||||
@ -459,6 +482,9 @@ static int hrtim_outputs_enable(FAR struct hrtim_dev_s *dev, uint16_t outputs,
|
||||
#ifdef HRTIM_HAVE_ADC
|
||||
static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv);
|
||||
#endif
|
||||
#ifdef HRTIM_HAVE_DAC
|
||||
static int hrtim_dac_config(FAR struct stm32_hrtim_s *priv);
|
||||
#endif
|
||||
#ifdef HRTIM_HAVE_FAULTS
|
||||
static int hrtim_faults_config(FAR struct stm32_hrtim_s *priv);
|
||||
static int hrtim_flt_cfg(FAR struct stm32_hrtim_s *priv, uint8_t index);
|
||||
@ -523,6 +549,9 @@ static struct stm32_hrtim_tim_s g_master =
|
||||
.base = STM32_HRTIM1_MASTER_BASE,
|
||||
.pclk = HRTIM_CLOCK/HRTIM_MASTER_PRESCALER,
|
||||
.mode = HRTIM_MASTER_MODE,
|
||||
#ifdef CONFIG_STM32_HRTIM_MASTER_DAC
|
||||
.dac = HRTIM_MASTER_DAC,
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_HRTIM_MASTER_IRQ
|
||||
.irq = HRTIM_IRQ_MASTER
|
||||
#endif
|
||||
@ -588,6 +617,9 @@ static struct stm32_hrtim_tim_s g_tima =
|
||||
.base = STM32_HRTIM1_TIMERA_BASE,
|
||||
.pclk = HRTIM_CLOCK/HRTIM_TIMA_PRESCALER,
|
||||
.mode = HRTIM_TIMA_MODE,
|
||||
#ifdef CONFIG_STM32_HRTIM_TIMA_DAC
|
||||
.dac = HRTIM_TIMA_DAC,
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_HRTIM_MASTER_IRQ
|
||||
.irq = HRTIM_IRQ_TIMA,
|
||||
#endif
|
||||
@ -758,6 +790,24 @@ struct stm32_hrtim_eev_s g_eev =
|
||||
};
|
||||
#endif
|
||||
|
||||
/* ADC triggering data */
|
||||
|
||||
struct stm32_hrtim_adc_s g_adc =
|
||||
{
|
||||
#ifdef CONFIG_STM32_HRTIM_ADC_TRG1
|
||||
.trg1 = HRTIM_ADC_TRG1,
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_HRTIM_ADC_TRG2
|
||||
.trg2 = HRTIM_ADC_TRG2,
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_HRTIM_ADC_TRG3
|
||||
.trg3 = HRTIM_ADC_TRG3,
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_HRTIM_ADC_TRG4
|
||||
.trg4 = HRTIM_ADC_TRG4
|
||||
#endif
|
||||
};
|
||||
|
||||
/* HRTIM1 private data */
|
||||
|
||||
static struct stm32_hrtim_s g_hrtim1priv =
|
||||
@ -780,13 +830,16 @@ static struct stm32_hrtim_s g_hrtim1priv =
|
||||
.time = &g_time,
|
||||
#endif
|
||||
#ifdef HRTIM_HAVE_FAULTS
|
||||
.flt = &g_flt,
|
||||
.flt = &g_flt,
|
||||
#endif
|
||||
#ifdef HRTIM_HAVE_EEV
|
||||
.eev = &g_eev,
|
||||
.eev = &g_eev,
|
||||
#endif
|
||||
#ifdef HRTIM_HAVE_ADC
|
||||
.adc = &g_adc,
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_HRTIM_CMN_IRQ
|
||||
.irq = HRTIM_IRQ_COMMON,
|
||||
.irq = HRTIM_IRQ_COMMON,
|
||||
#endif
|
||||
};
|
||||
|
||||
@ -1816,7 +1869,107 @@ static int hrtim_outputs_enable(FAR struct hrtim_dev_s *dev, uint16_t outputs,
|
||||
#ifdef HRTIM_HAVE_ADC
|
||||
static int hrtim_adc_config(FAR struct stm32_hrtim_s *priv)
|
||||
{
|
||||
#warning "hrtim_adc_config: missing logic"
|
||||
|
||||
#ifdef CONFIG_STM32_HRTIM_ADC_TRG1
|
||||
hrtim_putreg(priv, STM32_HRTIM_CMN_ADC1R_OFFSET, priv->adc->trg1);
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_HRTIM_ADC_TRG2
|
||||
hrtim_putreg(priv, STM32_HRTIM_CMN_ADC2R_OFFSET, priv->adc->trg2);
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_HRTIM_ADC_TRG3
|
||||
hrtim_putreg(priv, STM32_HRTIM_CMN_ADC3R_OFFSET, priv->adc->trg3);
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_HRTIM_ADC_TRG4
|
||||
hrtim_putreg(priv, STM32_HRTIM_CMN_ADC4R_OFFSET, priv->adc->trg4);
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef HRTIM_HAVE_DAC
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hrtim_tim_dac_cfg
|
||||
*
|
||||
* Description:
|
||||
* Configure single HRTIM Timer DAC synchronization event
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - A reference to the HRTIM structure
|
||||
* timer - Timer index
|
||||
* dac - DAC synchronisation event configuration
|
||||
*
|
||||
* Returned Value:
|
||||
* 0 on success, a negated errno value on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int hrtim_tim_dac_cfg(FAS struct stm32_hrtim_s *priv, uint8_t timer,
|
||||
uint8_t dac)
|
||||
{
|
||||
FAR struct stm32_hrtim_tim_s *tim;
|
||||
uint32_t regval = 0;
|
||||
|
||||
tim = hrtim_tim_get(priv, timer);
|
||||
|
||||
regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET);
|
||||
|
||||
regval |= (dac << HRTIM_CMNCR_DACSYNC_SHIFT);
|
||||
|
||||
hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: hrtim_dac_config
|
||||
*
|
||||
* Description:
|
||||
* Configure HRTIM DAC triggers
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - A reference to the HRTIM structure
|
||||
*
|
||||
* Returned Value:
|
||||
* 0 on success, a negated errno value on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int hrtim_dac_config(FAR struct stm32_hrtim_s *priv)
|
||||
{
|
||||
FAR struct stm32_hrtim_slave_priv_s *slave_priv;
|
||||
|
||||
#ifdef CONFIG_STM32_HRTIM_MASTER_DAC
|
||||
slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->master->priv;
|
||||
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_MASTER, dac);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_HRTIM_TIMA_DAC
|
||||
slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->tima->priv;
|
||||
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMA, dac);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_HRTIM_TIMB_DAC
|
||||
slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timb->priv;
|
||||
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMB, dac);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_HRTIM_TIMC_DAC
|
||||
slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timc->priv;
|
||||
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMC, dac);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_HRTIM_TIMD_DAC
|
||||
slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->timd->priv;
|
||||
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIMD, dac);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_HRTIM_TIME_DAC
|
||||
slave_priv = (struct stm32_hrtim_slave_priv_s*)priv->time->priv;
|
||||
hrtim_tim_dac_cfg(priv, HRTIM_TIMER_TIME, dac);
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
@ -2704,7 +2857,13 @@ static int hrtim_tim_update_set(FAR struct stm32_hrtim_s *priv, uint8_t timer,
|
||||
|
||||
regval = hrtim_tim_getreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET);
|
||||
|
||||
/* TODO: update configuration */
|
||||
/* TODO: Configure update events */
|
||||
|
||||
/* TODO: Configure update gating */
|
||||
|
||||
/* Write register */
|
||||
|
||||
hrtim_tim_putreg(priv, timer, STM32_HRTIM_TIM_CR_OFFSET, regval);
|
||||
|
||||
return OK;
|
||||
}
|
||||
@ -2857,6 +3016,17 @@ static int stm32_hrtimconfig(FAR struct stm32_hrtim_s *priv)
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure DAC synchronization */
|
||||
|
||||
#ifdef HRTIM_HAVE_DAC
|
||||
ret = hrtim_dac_config(priv);
|
||||
if (ret != OK)
|
||||
{
|
||||
tmrerr("ERROR: HRTIM ADC configuration failed!\n");
|
||||
goto errout;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure Faults */
|
||||
|
||||
#ifdef HRTIM_HAVE_FAULTS
|
||||
|
@ -111,6 +111,11 @@
|
||||
# defined HRTIM_HAVE_INTERRUPTS
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32_HRTIM_ADC_TRG1) || defined(CONFIG_STM32_HRTIM_ADC_TRG2) || \
|
||||
defined(CONFIG_STM32_HRTIM_ADC_TRG3) || defined(CONFIG_STM32_HRTIM_ADC_TRG4)
|
||||
# define HRTIM_HAVE_ADC
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
@ -459,7 +464,7 @@ enum stm32_hrtim_dacsync_e
|
||||
|
||||
/* HRTIM Deadtime Locks */
|
||||
|
||||
enum stm32_deadtime_lock_e
|
||||
enum stm32_hrtim_deadtime_lock_e
|
||||
{
|
||||
HRTIM_DT_VALUE_LOCK = (1 << 0), /* Lock Deadtime value */
|
||||
HRTIM_DT_SIGN_LOCK = (1 << 1) /* Lock Deadtime sign */
|
||||
@ -467,7 +472,7 @@ enum stm32_deadtime_lock_e
|
||||
|
||||
/* HRTIM Deadtime types */
|
||||
|
||||
enum stm32_deadtime_edge_e
|
||||
enum stm32_hrtim_deadtime_edge_e
|
||||
{
|
||||
HRTIM_DT_RISING = 0,
|
||||
HRTIM_DT_FALLING = 1
|
||||
@ -475,7 +480,7 @@ enum stm32_deadtime_edge_e
|
||||
|
||||
/* Chopper start pulsewidth */
|
||||
|
||||
enum stm32_chopper_start_e
|
||||
enum stm32_hrtim_chopper_start_e
|
||||
{
|
||||
HRTIM_CHP_START_16,
|
||||
HRTIM_CHP_START_32,
|
||||
@ -496,7 +501,7 @@ enum stm32_chopper_start_e
|
||||
|
||||
/* Chopper duty cycle */
|
||||
|
||||
enum stm32_chopper_duty_e
|
||||
enum stm32_hrtim_chopper_duty_e
|
||||
{
|
||||
HRTIM_CHP_DUTY_0,
|
||||
HRTIM_CHP_DUTY_1,
|
||||
@ -510,7 +515,7 @@ enum stm32_chopper_duty_e
|
||||
|
||||
/* Chopper carrier frequency */
|
||||
|
||||
enum stm32_chopper_freq_e
|
||||
enum stm32_hrtim_chopper_freq_e
|
||||
{
|
||||
HRTIM_CHP_FREQ_d16,
|
||||
HRTIM_CHP_FREQ_d32,
|
||||
@ -530,6 +535,152 @@ enum stm32_chopper_freq_e
|
||||
HRTIM_CHP_FREQ_d256
|
||||
};
|
||||
|
||||
/* HRTIM ADC Trigger 1/3 */
|
||||
|
||||
enum stm32_hrtim_adc_trq13_e
|
||||
{
|
||||
HRTIM_ADCTRG13_MC1 = (1 << 0),
|
||||
HRTIM_ADCTRG13_MC2 = (1 << 1),
|
||||
HRTIM_ADCTRG13_MC3 = (1 << 2),
|
||||
HRTIM_ADCTRG13_MC4 = (1 << 3),
|
||||
HRTIM_ADCTRG13_MPER = (1 << 4),
|
||||
|
||||
HRTIM_ADCTRG13_EEV1 = (1 << 5),
|
||||
HRTIM_ADCTRG13_EEV2 = (1 << 6),
|
||||
HRTIM_ADCTRG13_EEV3 = (1 << 7),
|
||||
HRTIM_ADCTRG13_EEV4 = (1 << 8),
|
||||
HRTIM_ADCTRG13_EEV5 = (1 << 9),
|
||||
|
||||
HRTIM_ADCTRG13_AC2 = (1 << 10),
|
||||
HRTIM_ADCTRG13_AC3 = (1 << 11),
|
||||
HRTIM_ADCTRG13_AC4 = (1 << 12),
|
||||
HRTIM_ADCTRG13_APER = (1 << 13),
|
||||
HRTIM_ADCTRG13_ARST = (1 << 14),
|
||||
|
||||
HRTIM_ADCTRG13_BC2 = (1 << 15),
|
||||
HRTIM_ADCTRG13_BC3 = (1 << 16),
|
||||
HRTIM_ADCTRG13_BC4 = (1 << 17),
|
||||
HRTIM_ADCTRG13_BPER = (1 << 18),
|
||||
HRTIM_ADCTRG13_BRST = (1 << 19),
|
||||
|
||||
HRTIM_ADCTRG13_CC2 = (1 << 20),
|
||||
HRTIM_ADCTRG13_CC3 = (1 << 21),
|
||||
HRTIM_ADCTRG13_CC4 = (1 << 22),
|
||||
HRTIM_ADCTRG13_CPER = (1 << 23),
|
||||
|
||||
HRTIM_ADCTRG13_DC2 = (1 << 24),
|
||||
HRTIM_ADCTRG13_DC3 = (1 << 25),
|
||||
HRTIM_ADCTRG13_DC4 = (1 << 26),
|
||||
HRTIM_ADCTRG13_DPER = (1 << 27),
|
||||
|
||||
HRTIM_ADCTRG13_EC2 = (1 << 28),
|
||||
HRTIM_ADCTRG13_EC3 = (1 << 29),
|
||||
HRTIM_ADCTRG13_EC4 = (1 << 30),
|
||||
HRTIM_ADCTRG13_ERST = (1 << 31),
|
||||
};
|
||||
|
||||
/* HRTIM ADC Trigger 2/4 */
|
||||
|
||||
enum stm32_hrtim_adc_trq24_e
|
||||
{
|
||||
HRTIM_ADCTRG24_MC1 = (1 << 0),
|
||||
HRTIM_ADCTRG24_MC2 = (1 << 1),
|
||||
HRTIM_ADCTRG24_MC3 = (1 << 2),
|
||||
HRTIM_ADCTRG24_MC4 = (1 << 3),
|
||||
HRTIM_ADCTRG24_MPER = (1 << 4),
|
||||
|
||||
HRTIM_ADCTRG24_EEV6 = (1 << 5),
|
||||
HRTIM_ADCTRG24_EEV7 = (1 << 6),
|
||||
HRTIM_ADCTRG24_EEV8 = (1 << 7),
|
||||
HRTIM_ADCTRG24_EEV9 = (1 << 8),
|
||||
HRTIM_ADCTRG24_EEV10 = (1 << 9),
|
||||
|
||||
HRTIM_ADCTRG24_AC2 = (1 << 10),
|
||||
HRTIM_ADCTRG24_AC3 = (1 << 11),
|
||||
HRTIM_ADCTRG24_AC4 = (1 << 12),
|
||||
HRTIM_ADCTRG24_APER = (1 << 13),
|
||||
|
||||
HRTIM_ADCTRG24_BC2 = (1 << 14),
|
||||
HRTIM_ADCTRG24_BC3 = (1 << 15),
|
||||
HRTIM_ADCTRG24_BC4 = (1 << 16),
|
||||
HRTIM_ADCTRG24_BPER = (1 << 17),
|
||||
|
||||
HRTIM_ADCTRG24_CC2 = (1 << 18),
|
||||
HRTIM_ADCTRG24_CC3 = (1 << 19),
|
||||
HRTIM_ADCTRG24_CC4 = (1 << 20),
|
||||
HRTIM_ADCTRG24_CPER = (1 << 21),
|
||||
HRTIM_ADCTRG24_CRST = (1 << 22),
|
||||
|
||||
HRTIM_ADCTRG24_DC2 = (1 << 23),
|
||||
HRTIM_ADCTRG24_DC3 = (1 << 24),
|
||||
HRTIM_ADCTRG24_DC4 = (1 << 25),
|
||||
HRTIM_ADCTRG24_DPER = (1 << 26),
|
||||
HRTIM_ADCTRG24_DRST = (1 << 27),
|
||||
|
||||
HRTIM_ADCTRG24_EC2 = (1 << 28),
|
||||
HRTIM_ADCTRG24_EC3 = (1 << 29),
|
||||
HRTIM_ADCTRG24_EC4 = (1 << 30),
|
||||
HRTIM_ADCTRG24_ERST = (1 << 31),
|
||||
};
|
||||
|
||||
/* HRTIM DAC synchronization */
|
||||
|
||||
enum stm32_hrtim_dac_e
|
||||
{
|
||||
HRTIM_DAC_SYNC_DIS = 0,
|
||||
HRTIM_DAC_SYNC_1 = 1,
|
||||
HRTIM_DAC_SYNC_2 = 2,
|
||||
HRTIM_DAC_SYNC_3 = 3
|
||||
};
|
||||
|
||||
|
||||
/* HRTIM Master Timer interrupts */
|
||||
|
||||
enum stm32_irq_master_e
|
||||
{
|
||||
HRTIM_IRQ_MCMP1 = (1 << 0), /* Master Compare 1 Interrupt */
|
||||
HRTIM_IRQ_MCMP2 = (1 << 1), /* Master Compare 2 Interrupt */
|
||||
HRTIM_IRQ_MCMP3 = (1 << 2), /* Master Compare 3 Interrupt */
|
||||
HRTIM_IRQ_MCMP4 = (1 << 3), /* Master Compare 4 Interrupt */
|
||||
HRTIM_IRQ_MREP = (1 << 4), /* Master Repetition Interrupt */
|
||||
HRTIM_IRQ_MSYNC = (1 << 5), /* Sync Input Interrupt */
|
||||
HRTIM_IRQ_MUPD = (1 << 6) /* Master Update Interrupt */
|
||||
};
|
||||
|
||||
/* HRTIM Slave Timer interrupts */
|
||||
|
||||
enum stm32_irq_slave_e
|
||||
{
|
||||
HRTIM_IRQ_CMP1 = (1 << 0), /* Slave Compare 1 Interrupt */
|
||||
HRTIM_IRQ_CMP2 = (1 << 1), /* Slave Compare 2 Interrupt */
|
||||
HRTIM_IRQ_CMP3 = (1 << 2), /* Slave Compare 3 Interrupt */
|
||||
HRTIM_IRQ_CMP4 = (1 << 3), /* Slave Compare 4 Interrupt */
|
||||
HRTIM_IRQ_REP = (1 << 4), /* Slave Repetition Interrupt */
|
||||
HRTIM_IRQ_UPD = (1 << 6), /* Slave Update Interrupt */
|
||||
HRTIM_IRQ_CPT1 = (1 << 7), /* Slave Capture 1 Interrupt */
|
||||
HRTIM_IRQ_CPT2 = (1 << 8), /* Slave Capture 2 Interrupt */
|
||||
HRTIM_IRQ_SETX1 = (1 << 9), /* Slave Output 1 Set Interrupt */
|
||||
HRTIM_IRQ_RSTX1 = (1 << 10), /* Slave Output 1 Reset Interrupt */
|
||||
HRTIM_IRQ_SETX2 = (1 << 11), /* Slave Output 2 Set Interrupt */
|
||||
HRTIM_IRQ_RSTX2 = (1 << 12), /* Slave Output 2 Reset Interrupt */
|
||||
HRTIM_IRQ_RST = (1 << 13), /* Slave Reset/roll-over Interrupt */
|
||||
HRTIM_IRQ_DLYPRT = (1 << 14) /* Slave Delayed Protection Interrupt */
|
||||
};
|
||||
|
||||
/* HRTIM Common Interrupts */
|
||||
|
||||
enum stm32_irq_cmn_e
|
||||
{
|
||||
HRTIM_IRQ_FLT1 = (1 << 0), /* Fault 1 Interrupt */
|
||||
HRTIM_IRQ_FLT2 = (1 << 1), /* Fault 2 Interrupt */
|
||||
HRTIM_IRQ_FLT3 = (1 << 2), /* Fault 3 Interrupt */
|
||||
HRTIM_IRQ_FLT4 = (1 << 3), /* Fault 4 Interrupt */
|
||||
HRTIM_IRQ_FLT5 = (1 << 4), /* Fault 5 Interrupt */
|
||||
HRTIM_IRQ_SYSFLT = (1 << 5), /* System Fault Interrupt */
|
||||
HRTIM_IRQ_DLLRDY = (1 << 16), /* DLL Ready Interrupt */
|
||||
HRTIM_IRQ_BMPER = (1 << 17) /* Burst Mode Period Interrupt */
|
||||
};
|
||||
|
||||
/* HRTIM vtable */
|
||||
struct hrtim_dev_s;
|
||||
struct stm32_hrtim_ops_s
|
||||
|
Loading…
Reference in New Issue
Block a user