Merged in elbeinformatik/nuttx/NX-PR (pull request #448)
Bug fixes for STM32F769 Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
Titus von Boxberg
Gregory Nutt
commit
cd3ca1140e
@ -4692,7 +4692,8 @@ config STM32F7_LTDC_BACKCOLOR
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default 0x0
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---help---
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This is the background color that will be used as the LTDC
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background layer color. It is an RGB888 format value.
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background layer color. It is an RGB888 format value,
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which gets written unmodified to register LTDC_BCCR.
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config STM32F7_LTDC_DITHER
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bool "Dither support"
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@ -4817,6 +4818,15 @@ config FB_TRANSPARENCY
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ltdc L8 format.
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endif
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config STM32F7_LTDC_REGDEBUG
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bool "Enable LTDC register value debug messages"
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default n
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---help---
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This gives additional messages for LTDC related register values.
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Additionally, you have to select "Low-level LCD Debug Features"
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to enable the debug messages.
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endmenu
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endif # STM32F7_LTDC
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@ -194,7 +194,7 @@
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# define LTDC_GCR_DRW(n) ((uint32_t)(n) << LTDC_GCR_DRW_SHIFT)
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#define LTDC_GCR_DEN (1 << 16) /* Bit 16: Dither Enable */
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#define LTDC_GCR_PCPOL (1 << 28) /* Bit 28: Pixel Clock Polarity */
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#define LTDC_GCR_DEPOL (1 << 29) /* Bit 29: Data Enable Polarity */
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#define LTDC_GCR_DEPOL (1 << 29) /* Bit 29: Not(Data Enable) Polarity */
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#define LTDC_GCR_VSPOL (1 << 30) /* Bit 30: Vertical Sync Polarity */
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#define LTDC_GCR_HSPOL (1 << 31) /* Bit 31: Horizontal Sync Polarity */
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@ -60,8 +60,8 @@
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#define STM32_FMC_BASE34 0x80000000 /* 0x80000000-0x8fffffff: 512Mb FMC bank3&4 block */
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# define STM32_FMC_BANK3 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
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# define STM32_FMC_BANK4 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD */
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#define STM32_FMC_BASE5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb FMC */
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#define STM32_FMC_BASE6 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb FMC */
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#define STM32_FMC_BASE5 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb FMC SDRAM Bank 1 */
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#define STM32_FMC_BASE6 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb FMC SDRAM Bank 2 */
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#define STM32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M7 block */
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#define STM32_REGION_MASK 0xf0000000
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@ -70,20 +70,21 @@
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* CONFIG_RAM_END : End address (+1) of SRAM (F1 family only, the
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* : F4 family uses the a priori end of SRAM)
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*
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* In addition to internal SRAM, SRAM may also be available through the FMC.
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* In order to use FMC SRAM, the following additional things need to be
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* In addition to internal SRAM, external RAM may also be available through the FMC.
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* In order to use FMC RAM, the following additional things need to be
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* present in the NuttX configuration file:
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*
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* CONFIG_STM32F7_FMC=y : Enables the FMC
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* CONFIG_STM32F7_FMC_SRAM=y : Indicates that SRAM is available via the
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* FMC (as opposed to an LCD or FLASH).
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* CONFIG_HEAP2_BASE : The base address of the SRAM in the FMC
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* address space
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* CONFIG_HEAP2_SIZE : The size of the SRAM in the FMC
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* address space
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* CONFIG_MM_REGIONS : Must be set to a large enough value to
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* include the FMC SRAM (as determined by
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* the rules provided below)
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* CONFIG_STM32F7_FMC=y : Enables the FMC
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* CONFIG_STM32F7_FMC_S[D]RAM=y : SRAM and/or SDRAM is available via the FMC.
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* Either of these autoselects CONFIG_ARCH_HAVE_HEAP2
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* which is what we are interested in here.
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* CONFIG_HEAP2_BASE : The base address of the external RAM in the FMC
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* address space
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* CONFIG_HEAP2_SIZE : The size of the external RAM in the FMC
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* address space
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* CONFIG_MM_REGIONS : Must be set to a large enough value to
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* include the FMC external RAM (as determined by
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* the rules provided below)
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*/
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/* Set the start and end of SRAM1 and SRAM2 */
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@ -108,21 +109,31 @@
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# undef HAVE_DTCM
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#endif
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/* We can't possibly have FMC SRAM if the FMC is not enabled */
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/* We can't possibly have FMC external RAM if the FMC is not enabled */
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#ifndef CONFIG_STM32F7_FMC
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# undef CONFIG_STM32F7_FMC_SRAM
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# ifdef CONFIG_ARCH_HAVE_HEAP2
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# error CONFIG_ARCH_HAVE_HEAP2 but not CONFIG_STM32F7_FMC! Kconfig flawed?
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# endif
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# undef CONFIG_ARCH_HAVE_HEAP2
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#endif
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/* If FMC SRAM is going to be used as heap, then verify that the starting
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/* If FMC external RAM is going to be used as heap, then verify that the starting
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* address and size of the external SRAM region has been provided in the
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* configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE).
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*/
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#ifdef CONFIG_STM32F7_FMC_SRAM
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#ifdef CONFIG_ARCH_HAVE_HEAP2
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# if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE)
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# error CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided
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# undef CONFIG_STM32F7_FMC_SRAM
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# undef CONFIG_ARCH_HAVE_HEAP2
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# endif
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#endif
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#ifdef CONFIG_ARCH_HAVE_HEAP2
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# if CONFIG_HEAP2_BASE == 0 || CONFIG_HEAP2_SIZE == 0
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# warning "CONFIG_HEAP2_BASE or CONFIG_HEAP2_SIZE are zero. No HEAP2 enabled!"
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# undef CONFIG_ARCH_HAVE_HEAP2
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# endif
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#endif
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@ -130,21 +141,21 @@
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*
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* Configuration 1. System SRAM1 (only)
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* CONFIG_MM_REGIONS == 1
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* CONFIG_STM32F7_FMC_SRAM NOT defined
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* CONFIG_ARCH_HAVE_HEAP2 NOT defined
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* Configuration 2. System SRAM1 and SRAM2
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* CONFIG_MM_REGIONS == 2
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* CONFIG_STM32F7_FMC_SRAM NOT defined
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* CONFIG_ARCH_HAVE_HEAP2 NOT defined
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* Configuration 3. System SRAM1 and SRAM2 and DTCM
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* CONFIG_MM_REGIONS == 3
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* CONFIG_STM32F7_FMC_SRAM undefined
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* CONFIG_ARCH_HAVE_HEAP2 undefined
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* HAVE_DTCM defined
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* Configuration 4. System SRAM1 and SRAM2 and FMC SRAM
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* Configuration 4. System SRAM1 and SRAM2 and FMC RAM
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* CONFIG_MM_REGIONS == 3
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* CONFIG_STM32F7_FMC_SRAM defined
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* CONFIG_ARCH_HAVE_HEAP2 defined
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* HAVE_DTCM undefined
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* Configuration 5. System SRAM1 and SRAM2 and DTCM and FMC SRAM
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* Configuration 5. System SRAM1 and SRAM2 and DTCM and FMC RAM
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* CONFIG_MM_REGIONS == 4
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* CONFIG_STM32F7_FMC_SRAM defined
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* CONFIG_ARCH_HAVE_HEAP2 defined
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* HAVE_DTCM defined
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*
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* Let's make sure that all definitions are consistent before doing
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@ -152,9 +163,9 @@
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*/
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#if CONFIG_MM_REGIONS < 2
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# ifdef CONFIG_STM32F7_FMC_SRAM
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# warning "FMC SRAM excluded from the heap"
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# undef CONFIG_STM32F7_FMC_SRAM
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# ifdef CONFIG_ARCH_HAVE_HEAP2
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# warning "FMC external RAM excluded from the heap"
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# undef CONFIG_ARCH_HAVE_HEAP2
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# endif
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# ifdef HAVE_DTCM
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# warning "DTCM excluded from the heap"
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@ -162,29 +173,29 @@
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# endif
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# warning "SRAM2 excluded from the heap"
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#elif CONFIG_MM_REGIONS < 3
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# ifdef CONFIG_STM32F7_FMC_SRAM
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# warning "FMC SRAM excluded from the heap"
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# undef CONFIG_STM32F7_FMC_SRAM
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# ifdef CONFIG_ARCH_HAVE_HEAP2
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# warning "FMC external RAM excluded from the heap"
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# undef CONFIG_ARCH_HAVE_HEAP2
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# endif
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# ifdef HAVE_DTCM
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# warning "DTCM excluded from the heap"
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# undef HAVE_DTCM
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# endif
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#elif CONFIG_MM_REGIONS < 4
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# if defined(CONFIG_STM32F7_FMC_SRAM) && defined(HAVE_DTCM)
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# warning "CONFIG_MM_REGIONS == 3 but have both FMC SRAM and DTCM. DTCM excluded from the heap."
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# if defined(CONFIG_ARCH_HAVE_HEAP2) && defined(HAVE_DTCM)
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# warning "CONFIG_MM_REGIONS == 3 but have both FMC external RAM and DTCM. DTCM excluded from the heap."
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# undef HAVE_DTCM
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# elif !defined(CONFIG_STM32F7_FMC_SRAM) && !defined(HAVE_DTCM)
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# elif !defined(CONFIG_ARCH_HAVE_HEAP2) && !defined(HAVE_DTCM)
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# error "CONFIG_MM_REGIONS == 3 but I do not know what some of the region(s) are"
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# undef CONFIG_MM_REGIONS
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# define CONFIG_MM_REGIONS 2
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# endif
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#elif CONFIG_MM_REGIONS < 5
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# if !defined(CONFIG_STM32F7_FMC_SRAM) && !defined(HAVE_DTCM)
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# if !defined(CONFIG_ARCH_HAVE_HEAP2) && !defined(HAVE_DTCM)
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# error "CONFIG_MM_REGIONS == 4 but I do not know what some of the region(s) are"
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# undef CONFIG_MM_REGIONS
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# define CONFIG_MM_REGIONS 2
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# elif !defined(CONFIG_STM32F7_FMC_SRAM) || !defined(HAVE_DTCM)
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# elif !defined(CONFIG_ARCH_HAVE_HEAP2) || !defined(HAVE_DTCM)
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# error "CONFIG_MM_REGIONS == 4 but I do not know what some of the region(s) are"
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# undef CONFIG_MM_REGIONS
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# define CONFIG_MM_REGIONS 3
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@ -192,9 +203,9 @@
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#else
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# error "CONFIG_MM_REGIONS > 4 but I do not know what some of the region(s) are"
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# undef CONFIG_MM_REGIONS
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# if defined(CONFIG_STM32F7_FMC_SRAM) && defined(HAVE_DTCM)
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# if defined(CONFIG_ARCH_HAVE_HEAP2) && defined(HAVE_DTCM)
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# define CONFIG_MM_REGIONS 4
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# elif defined(CONFIG_STM32F7_FMC_SRAM) || defined(HAVE_DTCM)
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# elif defined(CONFIG_ARCH_HAVE_HEAP2) || defined(HAVE_DTCM)
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# define CONFIG_MM_REGIONS 3
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# else
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# define CONFIG_MM_REGIONS 2
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@ -405,10 +416,10 @@ void up_addregion(void)
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kumm_addregion((FAR void *)DTCM_START, DTCM_END-DTCM_START);
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#endif
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#ifdef CONFIG_STM32F7_FMC_SRAM
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#ifdef CONFIG_ARCH_HAVE_HEAP2
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#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
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/* Allow user-mode access to the FMC SRAM user heap memory */
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/* Allow user-mode access to the FMC RAM user heap memory */
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stm32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
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@ -418,7 +429,7 @@ void up_addregion(void)
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up_heap_color((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
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/* Add the external FMC SRAM user heap region. */
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/* Add the external FMC RAM user heap region. */
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kumm_addregion((FAR void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
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#endif
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@ -111,33 +111,22 @@
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#define STM32_LTDC_AWCR_AAW LTDC_AWCR_AAW(STM32_LTDC_LxWHPCR_WHSPPOS)
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/* LTDC_TWCR register */
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#define STM32_LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH(BOARD_LTDC_VSYNC + \
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BOARD_LTDC_VBP + \
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STM32_LTDC_HEIGHT + BOARD_LTDC_VFP - 1)
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#define STM32_LTDC_TOTALHEIGHT (BOARD_LTDC_VSYNC + \
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BOARD_LTDC_VBP + \
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STM32_LTDC_HEIGHT + BOARD_LTDC_VFP - 1)
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#define STM32_LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH(STM32_LTDC_TOTALHEIGHT)
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#define STM32_LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW(BOARD_LTDC_HSYNC + \
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BOARD_LTDC_HBP + \
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STM32_LTDC_WIDTH + BOARD_LTDC_HFP - 1)
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/* Global GCR register */
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/* Synchronisation and Polarity */
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/* Global GCR register: Synchronisation Polarity */
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#define STM32_LTDC_GCR_PCPOL BOARD_LTDC_GCR_PCPOL
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#define STM32_LTDC_GCR_DEPOL BOARD_LTDC_GCR_DEPOL
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#define STM32_LTDC_GCR_VSPOL BOARD_LTDC_GCR_VSPOL
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#define STM32_LTDC_GCR_HSPOL BOARD_LTDC_GCR_HSPOL
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/* Dither */
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#define STM32_LTDC_GCR_DEN BOARD_LTDC_GCR_DEN
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#define STM32_LTDC_GCR_DBW LTDC_GCR_GBW(BOARD_LTDC_GCR_DBW)
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#define STM32_LTDC_GCR_DGW LTDC_GCR_DGW(BOARD_LTDC_GCR_DGW)
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#define STN32_LTDC_GCR_DRW LTDC_GCR_DBW(BOARD_LTDC_GCR_DRW)
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/* LIPCR register */
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#define STM32_LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS(STM32_LTDC_TWCR_TOTALW)
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#define STM32_LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS(STM32_LTDC_TOTALHEIGHT)
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/* Configuration ************************************************************/
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@ -974,17 +963,15 @@ static void stm32_ltdc_periphconfig(void)
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stm32_ltdc_gpioconfig();
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#endif
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/* Configure APB2 LTDC clock external */
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/* APB2 LTDC clock is expected to be externally preconfigured */
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reginfo("configured RCC_APB2ENR=%08x\n", getreg32(STM32_RCC_APB2ENR));
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/* Configure the SAI PLL external to provide the LCD_CLK */
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/* SAI PLL is expected to be externally preconfigured to provide the LCD_CLK */
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reginfo("configured RCC_PLLSAI=%08x\n", getreg32(STM32_RCC_PLLSAICFGR));
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/* Configure dedicated clock external */
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reginfo("configured RCC_DCKCFGR=%08x\n", getreg32(STM32_RCC_DCKCFGR));
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/* Dedicated clocks are expected to be externally preconfigured */
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reginfo("configured RCC_DCKCFGR1=%08x\n", getreg32(STM32_RCC_DCKCFGR1));
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reginfo("configured RCC_DCKCFGR2=%08x\n", getreg32(STM32_RCC_DCKCFGR2));
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/* Configure LTDC_SSCR */
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@ -1014,9 +1001,10 @@ static void stm32_ltdc_periphconfig(void)
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putreg32(regval, STM32_LTDC_TWCR);
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reginfo("configured LTDC_TWCR=%08x\n", getreg32(STM32_LTDC_TWCR));
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/* Configure LTDC_GCR */
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regval = (STM32_LTDC_GCR_PCPOL | STM32_LTDC_GCR_DEPOL
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/* Configure signal polarities */
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regval = getreg32(STM32_LTDC_GCR);
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regval &= ~(LTDC_GCR_PCPOL | LTDC_GCR_DEPOL | LTDC_GCR_VSPOL | LTDC_GCR_HSPOL);
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regval |= (STM32_LTDC_GCR_PCPOL | STM32_LTDC_GCR_DEPOL
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| STM32_LTDC_GCR_VSPOL | STM32_LTDC_GCR_HSPOL);
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reginfo("set LTDC_GCR=%08x\n", regval);
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putreg32(regval, STM32_LTDC_GCR);
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@ -1073,8 +1061,7 @@ static void stm32_ltdc_dither(bool enable,
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regval &= ~LTDC_GCR_DEN;
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}
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regval &= ~(!LTDC_GCR_DEN | LTDC_GCR_DRW(0) |
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LTDC_GCR_DGW(0) | LTDC_GCR_DBW(0));
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regval &= ~(LTDC_GCR_DBW_MASK | LTDC_GCR_DGW_MASK | LTDC_GCR_DRW_MASK);
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regval |= (LTDC_GCR_DRW(red) | LTDC_GCR_DGW(green) | LTDC_GCR_DBW(blue));
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reginfo("set LTDC_GCR=%08x\n", regval);
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@ -3441,6 +3428,21 @@ FAR struct ltdc_layer_s *stm32_ltdcgetlayer(int lid)
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}
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#endif /* CONFIG_STM32F7_LTDC_INTERFACE */
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/****************************************************************************
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* Name: stm32_ltdcreset
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*
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* Description:
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* Reset LTDC via APB2RSTR
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*
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*
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****************************************************************************/
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void stm32_ltdcreset(void)
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{
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*((uint32_t *)(STM32_RCC_APB2RSTR)) |= RCC_APB2RSTR_LTDCRST;
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*((uint32_t *)(STM32_RCC_APB2RSTR)) &= ~RCC_APB2RSTR_LTDCRST;
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}
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/****************************************************************************
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* Name: stm32_ltdcinitialize
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*
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24
arch/arm/src/stm32f7/stm32_ltdc.h
Executable file → Normal file
24
arch/arm/src/stm32f7/stm32_ltdc.h
Executable file → Normal file
@ -106,9 +106,29 @@ struct stm32_ltdc_s
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* include/nuttx/video/fb.h.
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*/
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int stm32_ltdcinitialize(void);
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/****************************************************************************
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* Name: stm32_ltdcreset
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*
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* Description:
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* Reset LTDC via APB2RSTR
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*
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*
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****************************************************************************/
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void stm32_ltdcreset(void);
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/****************************************************************************
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* Name: stm32_ltdcinitialize
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*
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* Description:
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* Initialize the ltdc controller
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*
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* Return:
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* OK
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*
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****************************************************************************/
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int stm32_ltdcinitialize(void);
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FAR struct fb_vtable_s *stm32_ltdcgetvplane(int vplane);
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void stm32_ltdcuninitialize(void);
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void stm32_ltdcuninitialize(void);
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/************************************************************************************
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* Name: stm32_ltdcgetlayer
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@ -644,6 +644,12 @@ static inline void rcc_enableapb2(void)
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regval |= RCC_APB2ENR_LTDCEN;
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#endif
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#ifdef CONFIG_STM32F7_DSIHOST
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/* LTDC clock enable */
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|
||||
regval |= RCC_APB2ENR_DSIEN;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */
|
||||
}
|
||||
|
||||
@ -877,7 +883,7 @@ static void stm32_stdclockconfig(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
#if defined(CONFIG_STM32F7_LTDC) || defined(CONFIG_STM32F7_PLLI2S)
|
||||
#if defined(CONFIG_STM32F7_PLLI2S) || (STM32_RCC_DCKCFGR1_SAI1SRC == RCC_DCKCFGR1_SAI1SEL(1)) || (STM32_RCC_DCKCFGR1_SAI2SRC == RCC_DCKCFGR1_SAI2SEL(1))
|
||||
|
||||
/* Configure PLLI2S */
|
||||
|
||||
@ -892,6 +898,19 @@ static void stm32_stdclockconfig(void)
|
||||
| STM32_RCC_PLLSAICFGR_PLLSAIR);
|
||||
putreg32(regval, STM32_RCC_PLLI2SCFGR);
|
||||
|
||||
/* Enable PLLI2S */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLI2SON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLLI2S is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
regval = getreg32(STM32_RCC_DCKCFGR2);
|
||||
regval &= ~( RCC_DCKCFGR2_USART1SEL_MASK
|
||||
| RCC_DCKCFGR2_USART2SEL_MASK
|
||||
@ -931,19 +950,6 @@ static void stm32_stdclockconfig(void)
|
||||
|
||||
putreg32(regval, STM32_RCC_DCKCFGR2);
|
||||
|
||||
/* Enable PLLI2S */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_PLLI2SON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait until the PLLI2S is ready */
|
||||
|
||||
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLI2SRDY) == 0)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK)
|
||||
/* Low speed internal clock source LSI */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user