arch/arm/src/samd2l2/chip: Adds a complete ADC header file for SAMD21 and a partially complete ADC header file for the SAML21.
This commit is contained in:
Alexander Vasiliev
Gregory Nutt
parent
1f7df92b7a
commit
cdd42f6e5d
277
arch/arm/src/samd2l2/chip/samd_adc.h
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277
arch/arm/src/samd2l2/chip/samd_adc.h
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/********************************************************************************************
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* arch/arm/src/samd2l2/chip/samd_adc.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Alexander Vasiljev <alexvasiljev@gmail.com>
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*
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* References:
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* "Microchip SAM D21 Family Datasheet", Rev D - 9/2018
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_ADC_H
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#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_ADC_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#ifdef CONFIG_ARCH_FAMILY_SAMD21
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/********************************************************************************************
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* Pre-processor Definitions
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********************************************************************************************/
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/* ADC register offsets ********************************************************************/
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#define SAM_ADC_CTRLA_OFFSET 0x0000 /* Control A Register */
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#define SAM_ADC_REFCTL_OFFSET 0x0001 /* Reference Control Register */
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#define SAM_ADC_AVGCTRL_OFFSET 0x0002 /* Average Control Register */
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#define SAM_ADC_SAMPCTRL_OFFSET 0x0003 /* Sampling Time Control Register */
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#define SAM_ADC_CTRLB_OFFSET 0x0004 /* Control B Register */
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#define SAM_ADC_WINCTRL_OFFSET 0x0008 /* Window Monitor Control Register */
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#define SAM_ADC_SWTRIG_OFFSET 0x000C /* Software Trigger Register */
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#define SAM_ADC_INPUTCTRL_OFFSET 0x0010 /* Input Control Register */
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#define SAM_ADC_EVCTRL_OFFSET 0x0014 /* Event Control Register */
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#define SAM_ADC_INTENCLR_OFFSET 0x0016 /* Interrupt Enable Clear Register */
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#define SAM_ADC_INTENSET_OFFSET 0x0017 /* Interrupt Enable Set Register */
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#define SAM_ADC_INTFLAG_OFFSET 0x0018 /* Interrupt Flag Status and Clear Register */
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#define SAM_ADC_STATUS_OFFSET 0x0019 /* Status Register */
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#define SAM_ADC_RESULT_OFFSET 0x001A /* Result Register */
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#define SAM_ADC_WINLT_OFFSET 0x001C /* Window Monitor Lower Threshold Register */
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#define SAM_ADC_WINUT_OFFSET 0x0020 /* Window Monitor Upper Threshold Register */
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#define SAM_ADC_GAINCORR_OFFSET 0x0024 /* Gain Correction Register */
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#define SAM_ADC_OFFSETCORR_OFFSET 0x0026 /* Offset Correction Register */
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#define SAM_ADC_CALIB_OFFSET 0x0028 /* Calibration Register */
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#define SAM_ADC_DBGCTRL_OFFSET 0x002A /* Debug Control Register */
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/* ADC register addresses ******************************************************************/
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#define SAM_ADC_CTRLA (SAM_ADC_BASE + SAM_ADC_CTRLA_OFFSET)
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#define SAM_ADC_REFCTL (SAM_ADC_BASE + SAM_ADC_REFCTL_OFFSET)
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#define SAM_ADC_AVGCTRL (SAM_ADC_BASE + SAM_ADC_AVGCTRL_OFFSET)
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#define SAM_ADC_SAMPCTRL (SAM_ADC_BASE + SAM_ADC_SAMPCTRL_OFFSET)
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#define SAM_ADC_CTRLB (SAM_ADC_BASE + SAM_ADC_CTRLB_OFFSET)
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#define SAM_ADC_WINCTRL (SAM_ADC_BASE + SAM_ADC_WINCTRL_OFFSET)
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#define SAM_ADC_SWTRIG (SAM_ADC_BASE + SAM_ADC_SWTRIG_OFFSET)
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#define SAM_ADC_INPUTCTRL (SAM_ADC_BASE + SAM_ADC_INPUTCTRL_OFFSET)
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#define SAM_ADC_EVCTRL (SAM_ADC_BASE + SAM_ADC_EVCTRL_OFFSET)
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#define SAM_ADC_INTENCLR (SAM_ADC_BASE + SAM_ADC_INTENCLR_OFFSET)
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#define SAM_ADC_INTENSET (SAM_ADC_BASE + SAM_ADC_INTENSET_OFFSET)
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#define SAM_ADC_INTFLAG (SAM_ADC_BASE + SAM_ADC_INTFLAG_OFFSET)
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#define SAM_ADC_STATUS (SAM_ADC_BASE + SAM_ADC_STATUS_OFFSET)
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#define SAM_ADC_RESULT (SAM_ADC_BASE + SAM_ADC_RESULT_OFFSET)
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#define SAM_ADC_WINLT (SAM_ADC_BASE + SAM_ADC_WINLT_OFFSET)
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#define SAM_ADC_WINUT (SAM_ADC_BASE + SAM_ADC_WINUT_OFFSET)
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#define SAM_ADC_GAINCORR (SAM_ADC_BASE + SAM_ADC_GAINCORR_OFFSET)
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#define SAM_ADC_OFFSETCORR (SAM_ADC_BASE + SAM_ADC_OFFSETCORR_OFFSET)
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#define SAM_ADC_CALIB (SAM_ADC_BASE + SAM_ADC_CALIB_OFFSET)
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#define SAM_ADC_ADC_DBGCTRL (SAM_ADC_BASE + SAM_ADC_DBGCTRL_OFFSET)
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/* ADC register bit definitions ************************************************************/
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/* Control A Register */
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#define ADC_CTRLA_SWRST (1 << 0) /* Bit 0: Software reset */
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#define ADC_CTRLA_ENABLE (1 << 1) /* Bit 1: Enable ADC controller */
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#define ADC_CTRLA_RUNSTDBY (1 << 2) /* Bit 2: Run in standby */
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/* Reference Control Register */
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#define ADC_REFCTRL_REFSEL_OFFSET (0) /* Bit 3:0: Reference selection */
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#define ADC_REFCTRL_REFSEL_MASK (0x0F << ADC_REFCTRL_REFSEL_OFFSET)
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# define ADC_REFCTRL_REFSEL_INT1V (0 << ADC_REFCTRL_REFSEL_OFFSET) /* 1.0V voltage reference */
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# define ADC_REFCTRL_REFSEL_INTVCC0 (1 << ADC_REFCTRL_REFSEL_OFFSET) /* 1/1.48 VDDANA */
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# define ADC_REFCTRL_REFSEL_INTVCC1 (2 << ADC_REFCTRL_REFSEL_OFFSET) /* 1/2 VDDANA (only for VDDANA > 2.0V) */
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# define ADC_REFCTRL_REFSEL_VREFA (3 << ADC_REFCTRL_REFSEL_OFFSET) /* External reference */
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# define ADC_REFCTRL_REFSEL_VREFB (4 << ADC_REFCTRL_REFSEL_OFFSET) /* External reference */
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#define ADC_REFCTRL_REFCOMP (1 << 7) /* Bit 7: Reference buffer offset compensation enable */
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/* Average Control Register */
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#define ADC_AVGCTRL_SAMPLENUM_OFFSET (0) /* Bit 3:0: Number of samples to be collected */
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#define ADC_AVGCTRL_SAMPLENUM_MASK (0x0F << ADC_AVGCTRL_SAMPLENUM_OFFSET)
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# define ADC_AVGCTRL_SAMPLENUM_1 (0x00 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
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# define ADC_AVGCTRL_SAMPLENUM_2 (0x01 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
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# define ADC_AVGCTRL_SAMPLENUM_4 (0x02 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
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# define ADC_AVGCTRL_SAMPLENUM_8 (0x03 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
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# define ADC_AVGCTRL_SAMPLENUM_16 (0x04 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
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# define ADC_AVGCTRL_SAMPLENUM_32 (0x05 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
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# define ADC_AVGCTRL_SAMPLENUM_64 (0x06 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
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# define ADC_AVGCTRL_SAMPLENUM_128 (0x07 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
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# define ADC_AVGCTRL_SAMPLENUM_256 (0x08 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
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# define ADC_AVGCTRL_SAMPLENUM_512 (0x09 << ADC_AVGCTRL_SAMPLENUM_OFFSET)
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# define ADC_AVGCTRL_SAMPLENUM_1024 (0x0A << ADC_AVGCTRL_SAMPLENUM_OFFSET)
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#define ADC_AVGCTRL_ADJRES_OFFSET (1 << 4) /* Bit 4:6: Adjusting result/division coefficient */
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#define ADC_AVGCTRL_ADJRES_MASK (7 << ADC_AVGCTRL_ADJRES_OFFSET)
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/* Sampling Time Control Register */
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#define ADC_SAMPCTRL_SAMPLEN_OFFSET (0) /* Bit 5:0:Sampling time length */
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#define ADC_SAMPCTRL_SAMPLEN_MASK (0x3F << ADC_SAMPCTRL_SAMPLEN_OFFSET)
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/* Control B Register */
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#define ADC_CTRLB_DIFFMODE (1 << 0) /* Bit 0: Differenstial mode */
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#define ADC_CTRLB_LEFTADJ (1 << 1) /* Bit 1: Left-adjusted result */
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#define ADC_CTRLB_FREERUN (1 << 2) /* Bit 2: Free running mode */
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#define ADC_CTRLB_CORREN (1 << 3) /* Bit 3: Digital correction logic enabled */
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#define ADC_CTRLB_RESSEL_OFFSET (4) /* Bit 5:4: Conversion result resolution */
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#define ADC_CTRLB_RESSEL_MASK (3 << ADC_CTRLB_RESSEL_OFFSET)
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# define ADC_CTRLB_RESSEL_12BIT (0 << ADC_CTRLB_RESSEL_OFFSET) /* 12-bit result */
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# define ADC_CTRLB_RESSEL_16BIT (1 << ADC_CTRLB_RESSEL_OFFSET) /* For averaging mode output */
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# define ADC_CTRLB_RESSEL_10BIT (2 << ADC_CTRLB_RESSEL_OFFSET) /* 10-bit result */
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# define ADC_CTRLB_RESSEL_8BIT (3 << ADC_CTRLB_RESSEL_OFFSET) /* 8-bit result */
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#define ADC_CTRLB_PRESCALER_OFFSET (8) /* Bit 10:8: Prescaler configuration */
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#define ADC_CTRLB_PRESCALER_MASK (7 << ADC_CTRLB_PRESCALER_OFFSET)
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# define ADC_CTRLB_PRESCALER_DIV4 (0 << ADC_CTRLB_PRESCALER_OFFSET)
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# define ADC_CTRLB_PRESCALER_DIV8 (1 << ADC_CTRLB_PRESCALER_OFFSET)
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# define ADC_CTRLB_PRESCALER_DIV16 (2 << ADC_CTRLB_PRESCALER_OFFSET)
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# define ADC_CTRLB_PRESCALER_DIV32 (3 << ADC_CTRLB_PRESCALER_OFFSET)
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# define ADC_CTRLB_PRESCALER_DIV64 (4 << ADC_CTRLB_PRESCALER_OFFSET)
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# define ADC_CTRLB_PRESCALER_DIV128 (5 << ADC_CTRLB_PRESCALER_OFFSET)
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# define ADC_CTRLB_PRESCALER_DIV256 (6 << ADC_CTRLB_PRESCALER_OFFSET)
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# define ADC_CTRLB_PRESCALER_DIV512 (7 << ADC_CTRLB_PRESCALER_OFFSET)
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/* Window Monitor Control Register */
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#define ADC_WINCTRL_WINMODE_OFFSET (0) /* Bit 2:0: Window monitor mode */
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#define ADC_WINCTRL_WINMODE_MASK (7)
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# define ADC_WINCTRL_WINMODE_DISABLE (0 << ADC_WINCTRL_WINMODE_OFFSET) /* No window mode */
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# define ADC_WINCTRL_WINMODE_MODE1 (1 << ADC_WINCTRL_WINMODE_OFFSET) /* Mode 1: result > winlt */
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# define ADC_WINCTRL_WINMODE_MODE2 (2 << ADC_WINCTRL_WINMODE_OFFSET) /* Mode 2: result < winut */
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# define ADC_WINCTRL_WINMODE_MODE3 (3 << ADC_WINCTRL_WINMODE_OFFSET) /* Mode 3: winlt < result < winut */
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# define ADC_WINCTRL_WINMODE_MODE4 (4 << ADC_WINCTRL_WINMODE_OFFSET) /* Mode 4: !(winlt < result < winut) */
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/* Software Trigger Register */
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#define ADC_SWTRIG_FLUSH (1 << 0) /* Bit 0: Adc conversion flush */
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#define ADC_SWTRIG_START (1 << 1) /* Bit 1: Adc start conversion */
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/* Input Control Register */
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#define ADC_INPUTCTRL_MUXPOS_OFFSET (0) /* Bit 4:0: Positive mux input selection */
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#define ADC_INPUTCTRL_MUXPOS_MASK (0x1F << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN0 (0 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN1 (1 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN2 (2 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN3 (3 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN4 (4 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN5 (5 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN6 (6 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN7 (7 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN8 (8 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN9 (9 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN10 (10 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN11 (11 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN12 (12 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN13 (13 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN14 (14 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN15 (15 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN16 (16 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN17 (17 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN18 (18 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_AIN19 (19 << ADC_INPUTCTRL_MUXPOS_OFFSET)
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# define ADC_INPUTCTRL_MUXPOS_BANDGAP (0x19 << ADC_INPUTCTRL_MUXPOS_OFFSET) /* Bandgap voltage */
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# define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (0x1A << ADC_INPUTCTRL_MUXPOS_OFFSET) /* 1/4 scaled core voltage */
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# define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (0x1B << ADC_INPUTCTRL_MUXPOS_OFFSET) /* 1/4 scaled I/) supplly */
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# define ADC_INPUTCTRL_MUXPOS_DAC (0x1C << ADC_INPUTCTRL_MUXPOS_OFFSET) /* DAC output */
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#define ADC_INPUTCTRL_MUXNEG_OFFSET (8) /* Bit 12:8: Negative mux input selection */
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#define ADC_INPUTCTRL_MUXNEG_MASK (0x1F << ADC_INPUTCTRL_MUXNEG_OFFSET)
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# define ADC_INPUTCTRL_MUXNEG_AIN0 (0 << ADC_INPUTCTRL_MUXNEG_OFFSET)
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# define ADC_INPUTCTRL_MUXNEG_AIN1 (1 << ADC_INPUTCTRL_MUXNEG_OFFSET)
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# define ADC_INPUTCTRL_MUXNEG_AIN2 (2 << ADC_INPUTCTRL_MUXNEG_OFFSET)
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# define ADC_INPUTCTRL_MUXNEG_AIN3 (3 << ADC_INPUTCTRL_MUXNEG_OFFSET)
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# define ADC_INPUTCTRL_MUXNEG_AIN4 (4 << ADC_INPUTCTRL_MUXNEG_OFFSET)
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# define ADC_INPUTCTRL_MUXNEG_AIN5 (5 << ADC_INPUTCTRL_MUXNEG_OFFSET)
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# define ADC_INPUTCTRL_MUXNEG_AIN6 (6 << ADC_INPUTCTRL_MUXNEG_OFFSET)
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# define ADC_INPUTCTRL_MUXNEG_AIN7 (7 << ADC_INPUTCTRL_MUXNEG_OFFSET)
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# define ADC_INPUTCTRL_MUXNEG_GND (0x18 << ADC_INPUTCTRL_MUXNEG_OFFSET) /* Internal ground */
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# define ADC_INPUTCTRL_MUXNEG_IOGND (0x19 << ADC_INPUTCTRL_MUXNEG_OFFSET) /* I/O ground */
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#define ADC_INPUTCTRL_INPUTSCAN_OFFSET (16) /* Bit 19:16: Number of input channels included in scan */
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#define ADC_INPUTCTRL_INPUTSCAN_MASK (0x0F << ADC_INPUTCTRL_INPUTSCAN_OFFSET)
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#define ADC_INPUTCTRL_INPUTOFFSET_OFFSET (20) /* Bit 23:20: Positive mux setting offset */
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#define ADC_INPUTCTRL_INPUTOFFSET_MASK (0x0F << ADC_INPUTCTRL_INPUTOFFSET_OFFSET)
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#define ADC_INPUTCTRL_GAIN_OFFSET (24) /* Bit 27:24: Gain factor selection */
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#define ADC_INPUTCTRL_GAIN_MASK (0x0F) << ADC_INPUTCTRL_GAIN_OFFSET
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# define ADC_INPUTCTRL_GAIN_1X (0 << ADC_INPUTCTRL_GAIN_OFFSET)
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# define ADC_INPUTCTRL_GAIN_2X (1 << ADC_INPUTCTRL_GAIN_OFFSET)
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# define ADC_INPUTCTRL_GAIN_4X (2 << ADC_INPUTCTRL_GAIN_OFFSET)
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# define ADC_INPUTCTRL_GAIN_8X (3 << ADC_INPUTCTRL_GAIN_OFFSET)
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# define ADC_INPUTCTRL_GAIN_16X (4 << ADC_INPUTCTRL_GAIN_OFFSET)
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# define ADC_INPUTCTRL_GAIN_DIV2 (15 << ADC_INPUTCTRL_GAIN_OFFSET)
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/* Event Control Register */
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#define ADC_EVCTRL_STARTEI (1 << 0) /* Bit 0: Start conversion event in */
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#define ADC_EVCTRL_SYNCEI (1 << 1) /* Bit 1: Synchronization event in */
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#define ADC_EVCTRL_RESRDYEO (1 << 4) /* Bit 4: Result ready event out */
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#define ADC_EVCTRL_WINMONEO (1 << 5) /* Bit 5: Window monitor event out */
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/* Common bit definitions for Interrupt Enable Clear Register, Interrupt Enable Set
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* Register, and Interrupt Flag Status and Clear Register
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*/
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#define ADC_INT_RESRDY (1 << 0) /* Bit 0: Result ready */
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#define ADC_INT_OVERRUN (1 << 1) /* Bit 1: Overrun */
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#define ADC_INT_WINMON (1 << 2) /* Bit 2: Window monitor */
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#define ADC_INT_SYNCRDY (1 << 3) /* Bit 3: Synchronization ready */
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/* Status Register */
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#define ADC_STATUS_SYNCBUSY (1 << 7) /* Bit 7: Synchronization buzy */
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/* Calibration Register */
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#define ADC_CALIB_LINEARITY_OFFSET (0) /* Bit 7:0: Linearity calibration value */
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#define ADC_CALIB_LINEARITY_MASK (0xFF)
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#define ADC_CALIB_BIAS_OFFSET (8) /* Bit 10:8: Bias calibration value */
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#define ADC_CALIB_BIAS_MASK (7 << ADC_CALIB_BIAS_OFFSET)
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/* Debug Control Register */
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#define ADC_DBGCTRL_DBGRUN (1) /* Bit 0: Debug run */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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/********************************************************************************************
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* Public Data
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********************************************************************************************/
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/********************************************************************************************
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* Public Functions
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********************************************************************************************/
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#endif /* CONFIG_ARCH_FAMILY_SAMD21 */
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#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAMD_ADC_H */
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106
arch/arm/src/samd2l2/chip/saml_adc.h
Normal file
106
arch/arm/src/samd2l2/chip/saml_adc.h
Normal file
@ -0,0 +1,106 @@
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/********************************************************************************************
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* arch/arm/src/samd2l2/chip/saml_adc.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Alexander Vasiljev <alexvasiljev@gmail.com>
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*
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* References:
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* "Microchip SAM L21 Family Datasheet", Rev A - 02/2017
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_ADC_H
|
||||
#define __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_ADC_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#ifdef CONFIG_ARCH_FAMILY_SAML21
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
/* ADC register offsets ********************************************************************/
|
||||
|
||||
#define SAM_ADC_CTRLA_OFFSET 0x0000 /* Control A Register */
|
||||
#define SAM_ADC_CTRLB_OFFSET 0x0001 /* Control B Register */
|
||||
#define SAM_ADC_REFCTL_OFFSET 0x0002 /* Reference Control Register */
|
||||
#define SAM_ADC_EVCTRL_OFFSET 0x0003 /* Event Control Register */
|
||||
#define SAM_ADC_INTENCLR_OFFSET 0x0004 /* Interrupt Enable Clear Register */
|
||||
#define SAM_ADC_INTENSET_OFFSET 0x0005 /* Interrupt Enable Set Register */
|
||||
#define SAM_ADC_INTFLAG_OFFSET 0x0006 /* Interrupt Flag Status and Clear Register */
|
||||
#define SAM_ADC_SEQSTATUS_OFFSET 0x0007 /* Sequence Status Register */
|
||||
#define SAM_ADC_INPUTCTRL_OFFSET 0x0008 /* Input Control Register */
|
||||
#define SAM_ADC_CTRLC_OFFSET 0x000A /* Control C Register */
|
||||
#define SAM_ADC_AVGCTRL_OFFSET 0x000C /* Average Control Register */
|
||||
#define SAM_ADC_SAMPCTRL_OFFSET 0x000D /* Sampling Time Control Register */
|
||||
#define SAM_ADC_WINLT_OFFSET 0x000E /* Window Monitor Lower Threshold Register */
|
||||
#define SAM_ADC_WINUT_OFFSET 0x0010 /* Window Monitor Upper Threshold Register */
|
||||
#define SAM_ADC_GAINCORR_OFFSET 0x0012 /* Gain Correction Register */
|
||||
#define SAM_ADC_OFFSETCORR_OFFSET 0x0014 /* Offset Correction Register */
|
||||
#define SAM_ADC_SWTRIG_OFFSET 0x0018 /* Software Trigger Register */
|
||||
#define SAM_ADC_DBGCTRL_OFFSET 0x001C /* Debug Control Register */
|
||||
#define SAM_ADC_SYNCBUSY_OFFSET 0x0020 /* Synchronization Busy Register */
|
||||
#define SAM_ADC_RESULT_OFFSET 0x0024 /* Result Register */
|
||||
#define SAM_ADC_SEQCTRL_OFFSET 0x0028 /* Sequence Control Register */
|
||||
#define SAM_ADC_CALIB_OFFSET 0x002C /* Calibration Register */
|
||||
|
||||
/* ADC register addresses ******************************************************************/
|
||||
|
||||
#define SAM_ADC_CTRLA (SAM_ADC_BASE + SAM_ADC_CTRLA_OFFSET)
|
||||
#define SAM_ADC_CTRLB (SAM_ADC_BASE + SAM_ADC_CTRLB_OFFSET)
|
||||
#define SAM_ADC_REFCTL (SAM_ADC_BASE + SAM_ADC_REFCTL_OFFSET)
|
||||
#define SAM_ADC_EVCTRL (SAM_ADC_BASE + SAM_ADC_EVCTRL_OFFSET)
|
||||
#define SAM_ADC_INTENCLR (SAM_ADC_BASE + SAM_ADC_INTENCLR_OFFSET)
|
||||
#define SAM_ADC_INTENSET (SAM_ADC_BASE + SAM_ADC_INTENSET_OFFSET)
|
||||
#define SAM_ADC_INTFLAG (SAM_ADC_BASE + SAM_ADC_INTFLAG_OFFSET)
|
||||
#define SAM_ADC_SEQSTATUS (SAM_ADC_BASE + SAM_ADC_SEQSTATUS_OFFSET)
|
||||
#define SAM_ADC_INPUTCTRL (SAM_ADC_BASE + SAM_ADC_INPUTCTRL_OFFSET)
|
||||
#define SAM_ADC_CTRLC (SAM_ADC_BASE + SAM_ADC_CTRLC_OFFSET)
|
||||
#define SAM_ADC_AVGCTRL (SAM_ADC_BASE + SAM_ADC_AVGCTRL_OFFSET)
|
||||
#define SAM_ADC_SAMPCTRL (SAM_ADC_BASE + SAM_ADC_SAMPCTRL_OFFSET)
|
||||
#define SAM_ADC_WINLT (SAM_ADC_BASE + SAM_ADC_WINLT_OFFSET)
|
||||
#define SAM_ADC_WINUT (SAM_ADC_BASE + SAM_ADC_WINUT_OFFSET)
|
||||
#define SAM_ADC_GAINCORR (SAM_ADC_BASE + SAM_ADC_GAINCORR_OFFSET)
|
||||
#define SAM_ADC_OFFSETCORR (SAM_ADC_BASE + SAM_ADC_OFFSETCORR_OFFSET)
|
||||
#define SAM_ADC_SWTRIG (SAM_ADC_BASE + SAM_ADC_SWTRIG_OFFSET)
|
||||
#define SAM_ADC_DBGCTRL (SAM_ADC_BASE + SAM_ADC_DBGCTRL_OFFSET)
|
||||
#define SAM_ADC_SYNCBUSY (SAM_ADC_BASE + SAM_ADC_SYNCBUSY_OFFSET)
|
||||
#define SAM_ADC_RESULT (SAM_ADC_BASE + SAM_ADC_RESULT_OFFSET)
|
||||
#define SAM_ADC_SEQCTRL (SAM_ADC_BASE + SAM_ADC_SEQCTRL_OFFSET)
|
||||
#define SAM_ADC_CALIB (SAM_ADC_BASE + SAM_ADC_CALIB_OFFSET)
|
||||
|
||||
#endif /* CONFIG_ARCH_FAMILY_SAML21 */
|
||||
#endif /* __ARCH_ARM_SRC_SAMD2L2_CHIP_SAML_ADC_H */
|
||||
76
arch/arm/src/samd2l2/sam_adc.h
Normal file
76
arch/arm/src/samd2l2/sam_adc.h
Normal file
@ -0,0 +1,76 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/samd2l2/sam_adc.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
* Author: Alexander Vasiljev <alexvasiljev@gmail.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAMD2L2_SAM_ADC_H
|
||||
#define __ARCH_ARM_SRC_SAMD2L2_SAM_ADC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "sam_config.h"
|
||||
#include "sam_port.h"
|
||||
|
||||
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
|
||||
# include "chip/samd_adc.h"
|
||||
#elif defined(CONFIG_ARCH_FAMILY_SAML21)
|
||||
# include "chip/saml_adc.h"
|
||||
#else
|
||||
# error Unrecognized SAMD/L architecture
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ARCH_ARM_SRC_SAMD2L2_SAM_ADC_H */
|
||||
Loading…
Reference in New Issue
Block a user