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arch/armv7-ar: add isb after CACHE and TLB operations.

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zhangyuan21 2022-11-02 09:52:34 +08:00 committed by Xiang Xiao
parent 8be4bca3eb
commit cdeddcb028
4 changed files with 10 additions and 0 deletions
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2
arch/arm/src/armv7-a/arm_cpuhead.S
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@ -211,6 +211,7 @@ __cpu3_start:
mcr CP15_BPIALL(r0) /* Invalidate entire branch prediction array */
mcr CP15_ICIALLU(r0) /* Invalidate I-cache */
#endif
isb
/* Load the page table address.
*
@ -369,6 +370,7 @@ __cpu3_start:
/* Then write the configured control register */
mcr CP15_SCTLR(r0) /* Write control reg */
isb
.rept 12 /* Cortex A8 wants lots of NOPs here */
nop
.endr

4
arch/arm/src/armv7-a/arm_head.S
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@ -208,6 +208,7 @@ __cpu0_start:
bic r0, r0, #(SCTLR_M | SCTLR_C)
bic r0, r0, #(SCTLR_I)
mcr CP15_SCTLR(r0)
isb
/* Clear the 16K level 1 page table */
@ -364,6 +365,8 @@ __cpu0_start:
mcr CP15_ICIALLU(r0) /* Invalidate I-cache */
#endif
isb
/* Load the page table address.
*
* NOTES:
@ -523,6 +526,7 @@ __cpu0_start:
/* Then write the configured control register */
mcr CP15_SCTLR(r0) /* Write control reg */
isb
.rept 12 /* Cortex A8 wants lots of NOPs here */
nop
.endr

2
arch/arm/src/armv7-a/arm_pghead.S
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@ -320,6 +320,7 @@ __start:
mcr CP15_TLBIALL(r0,c5)
mcr CP15_BPIALL(r0) /* Invalidate entire branch prediction array */
mcr CP15_ICIALLU(r0) /* Invalidate I-cache */
isb
/* Load the page table address.
*
@ -467,6 +468,7 @@ __start:
/* Then write the configured control register */
mcr CP15_SCTLR(r0) /* Write control reg */
isb
.rept 12 /* Cortex A8 wants lots of NOPs here */
nop
.endr

2
arch/arm/src/armv7-r/arm_head.S
View File

@ -161,6 +161,7 @@ __start:
mcr CP15_BPIALL(r0) /* Invalidate entire branch prediction array */
mcr CP15_ICIALLU(r0) /* Invalidate I-cache */
mcr CP15_DCIALLU(r0) /* Invalidate D-cache */
isb
/* Configure the system control register (see sctrl.h) */
@ -313,6 +314,7 @@ __start:
/* Then write the configured control register */
mcr CP15_SCTLR(r0) /* Write control reg */
isb
.rept 12 /* Some CPUs want want lots of NOPs here */
nop
.endr