arch/arm/src/samv7: add DMA and TC trigger support to AFEC driver
This commit adds DMA and TC support to SAMV7 AFEC driver. The AFEC (ADC) can now be triggered by Timer/counter at chosen frewuency and samples can be transfered via DMA with configurable number of samples. Timer/counter trigger is now set as a default option with the possibility to change it to software generated trigger. DMA is inspired by SAMA5 driver and also uses ping pong buffers. Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This commit is contained in:
Michal Lenc
Xiang Xiao
parent
6f2e23ad0c
commit
ce53ea5da6
@ -314,10 +314,16 @@ config SAMV7_ADC
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bool "12-bit ADC Controller (ADC)"
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default n
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config SAMV7_AFEC0
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config SAMV7_AFEC_TIOATRIG
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bool
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default n
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menuconfig SAMV7_AFEC0
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bool "Analog Front End 0 (AFEC0)"
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default n
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select SAMV7_AFEC
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---help---
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Support for AFEC0 (ADC) driver.
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if SAMV7_AFEC0
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@ -332,12 +338,65 @@ config SAMV7_AFEC0_RES
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3 OSR16
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4 OSR64
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5 OSR256
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endif
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config SAMV7_AFEC1
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config SAMV7_AFEC_DMA
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bool "DMA Support"
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default n
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depends on SAMV7_XDMAC
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---help---
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Enables transfer of converted data over DMA.
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config SAMV7_AFEC_DMASAMPLES
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int "Number of DMA samples"
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default 2
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depends on SAMV7_AFEC_DMA
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---help---
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Number of DMA samples to be transfered. Number of samples less than
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2 might be inneficient.
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choice
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prompt "AFEC Trigger mode"
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default SAMV7_AFEC0_TIOATRIG
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config SAMV7_AFEC0_TIOATRIG
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bool "Timer/counter trigger"
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select SAMV7_AFEC_TIOATRIG
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---help---
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Use output of Timer/Counter as a trigger.
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config SAMV7_AFEC0_SWTRIG
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bool "Software trigger"
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---help---
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Use software trigger.
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endchoice
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if SAMV7_AFEC0_TIOATRIG
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config SAMV7_AFEC0_TIOAFREQ
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int "AFEC sampling frequency"
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default 1000
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---help---
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This setting provides the rate at which the timer will driver AFEC
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sampling.
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config SAMV7_AFEC0_TIOACHAN
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int "Timer/counter channel number"
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default 0
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range 0 2
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---help---
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Number of TC channel to trigger the AFEC conversion.
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endif #SAMV7_AFEC0_TIOATRIG
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endif # SAMV7_AFEC0
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menuconfig SAMV7_AFEC1
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bool "Analog Front End 1 (AFEC1)"
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default n
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select SAMV7_AFEC
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---help---
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Support for AFEC1 (ADC) driver.
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if SAMV7_AFEC1
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@ -352,7 +411,58 @@ config SAMV7_AFEC1_RES
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3 OSR16
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4 OSR64
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5 OSR256
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endif
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config SAMV7_AFEC_DMA
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bool "DMA Support"
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default n
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depends on SAMV7_XDMAC
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---help---
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Enables transfer of converted data over DMA.
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config SAMV7_AFEC_DMASAMPLES
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int "Number of DMA samples"
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default 2
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depends on SAMV7_AFEC_DMA
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---help---
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Number of DMA samples to be transfered. Number of samples less than
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2 might be inneficient.
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choice
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prompt "AFEC Trigger mode"
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default SAMV7_AFEC1_TIOATRIG
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config SAMV7_AFEC1_TIOATRIG
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bool "Timer/counter trigger"
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select SAMV7_AFEC_TIOATRIG
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---help---
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Use output of Timer/Counter as a trigger.
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config SAMV7_AFEC1_SWTRIG
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bool "Software trigger"
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---help---
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Use software trigger.
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endchoice
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if SAMV7_AFEC1_TIOATRIG
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config SAMV7_AFEC1_TIOAFREQ
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int "AFEC sampling frequency"
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default 1000
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---help---
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This setting provides the rate at which the timer will driver ADC
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sampling.
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config SAMV7_AFEC1_TIOACHAN
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int "Timer/counter channel number"
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default 3
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range 3 5
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---help---
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Number of TC channel to trigger the AFEC conversion.
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endif #SAMV7_AFEC1_TIOATRIG
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endif # SAMV7_AFEC1
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config SAMV7_MCAN0
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bool "CAN controller 0 (MCAN0)"
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@ -36,6 +36,7 @@
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#include <arch/board/board.h>
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#include <nuttx/irq.h>
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#include <nuttx/arch.h>
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#include <nuttx/wqueue.h>
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#include <nuttx/analog/adc.h>
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#include <nuttx/analog/ioctl.h>
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@ -47,7 +48,9 @@
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#include "hardware/sam_pio.h"
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#include "sam_periphclks.h"
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#include "sam_gpio.h"
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#include "sam_tc.h"
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#include "sam_afec.h"
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#include "sam_xdmac.h"
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#ifdef CONFIG_ADC
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@ -59,6 +62,27 @@
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#define ADC_MAX_CHANNELS 11
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#ifdef CONFIG_SAMV7_AFEC_DMA
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#define DMA_FLAGS (DMACH_FLAG_FIFOCFG_LARGEST | \
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DMACH_FLAG_PERIPHH2SEL | DMACH_FLAG_PERIPHISPERIPH | \
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DMACH_FLAG_PERIPHWIDTH_32BITS | DMACH_FLAG_PERIPHCHUNKSIZE_1 | \
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DMACH_FLAG_MEMPID_MAX | DMACH_FLAG_MEMAHB_AHB_IF0 | \
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DMACH_FLAG_PERIPHAHB_AHB_IF1 | DMACH_FLAG_MEMWIDTH_32BITS | \
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DMACH_FLAG_MEMINCREMENT | DMACH_FLAG_MEMCHUNKSIZE_1 | \
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DMACH_FLAG_MEMBURST_1)
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#endif
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#if !defined(CONFIG_SAMV7_AFEC_DMA)
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# undef CONFIG_SAMV7_AFEC_DMASAMPLES
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# define CONFIG_SAMV7_AFEC_DMASAMPLES 1
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#elif !defined(CONFIG_SAMV7_AFEC_DMASAMPLES)
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# error CONFIG_SAMV7_AFEC_DMASAMPLES must be defined
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#elif CONFIG_SAMV7_AFEC_DMASAMPLES < 2
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# warning Values of CONFIG_SAMV7_AFEC_DMASAMPLES < 2 are inefficient
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#endif
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#define SAMV7_AFEC_SAMPLES (CONFIG_SAMV7_AFEC_DMASAMPLES * ADC_MAX_CHANNELS)
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/****************************************************************************
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* Private Types
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****************************************************************************/
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@ -70,10 +94,31 @@ struct samv7_dev_s
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uint32_t base; /* ADC register base */
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uint8_t initialized; /* ADC initialization counter */
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uint8_t resolution; /* ADC resolution (SAMV7_AFECn_RES) */
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uint8_t trigger; /* ADC trigger (software, timer...) */
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uint8_t timer_channel; /* Timer channel to trigger ADC */
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uint32_t frequency; /* Frequency of the timer */
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int irq; /* ADC IRQ number */
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int pid; /* ADC PID number */
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int nchannels; /* Number of configured channels */
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uint8_t chanlist[ADC_MAX_CHANNELS]; /* ADC channel list */
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uint8_t current; /* Current channel being converted */
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#ifdef CONFIG_SAMV7_AFEC_TIOATRIG
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TC_HANDLE tc; /* Handle for the timer channel */
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#endif
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#ifdef CONFIG_SAMV7_AFEC_DMA
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volatile bool odd; /* Odd buffer is in use */
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volatile bool ready; /* Worker has completed the last set of samples */
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volatile bool enabled; /* DMA data transfer is enabled */
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int nsamples;
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DMA_HANDLE dma; /* Handle for DMA channel */
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struct work_s work; /* Supports the interrupt handling "bottom half" */
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/* DMA sample data buffer */
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uint32_t evenbuf[SAMV7_AFEC_SAMPLES];
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uint32_t oddbuf[SAMV7_AFEC_SAMPLES];
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#endif
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};
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/****************************************************************************
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@ -84,6 +129,22 @@ static void afec_putreg(FAR struct samv7_dev_s *priv, uint32_t offset,
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uint32_t value);
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static uint32_t afec_getreg(FAR struct samv7_dev_s *priv, uint32_t offset);
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#ifdef CONFIG_SAMV7_AFEC_DMA
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static void sam_afec_dmadone(void *arg);
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static void sam_afec_dmacallback(DMA_HANDLE handle, void *arg, int result);
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static int sam_afec_dmasetup(struct adc_dev_s *dev, FAR uint8_t *buffer,
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size_t buflen);
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static void sam_afec_dmastart(struct adc_dev_s *dev);
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#endif
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#ifdef CONFIG_SAMV7_AFEC_TIOATRIG
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static int sam_afec_settimer(struct samv7_dev_s *priv, uint32_t frequency,
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int channel);
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static void sam_afec_freetimer(struct samv7_dev_s *priv);
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#endif
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static int sam_afec_trigger(struct samv7_dev_s *priv);
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/* ADC methods */
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static int afec_bind(FAR struct adc_dev_s *dev,
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@ -114,9 +175,17 @@ static const struct adc_ops_s g_adcops =
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static struct samv7_dev_s g_adcpriv0 =
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{
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.irq = SAM_IRQ_AFEC0,
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.pid = SAM_PID_AFEC0,
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.intf = 0,
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.initialized = 0,
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.resolution = CONFIG_SAMV7_AFEC0_RES,
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#ifdef CONFIG_SAMV7_AFEC0_SWTRIG
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.trigger = 0,
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#else
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.trigger = 1,
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.timer_channel = CONFIG_SAMV7_AFEC0_TIOACHAN,
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.frequency = CONFIG_SAMV7_AFEC0_TIOAFREQ,
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#endif
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.base = SAM_AFEC0_BASE,
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};
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@ -146,16 +215,24 @@ gpio_pinset_t g_adcpinlist0[ADC_MAX_CHANNELS] =
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static struct samv7_dev_s g_adcpriv1 =
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{
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.irq = SAM_IRQ_AFEC1,
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.pid = SAM_PID_AFEC1,
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.intf = 1,
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.initialized = 0,
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.resolution = CONFIG_SAMV7_AFEC1_RES,
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#ifdef CONFIG_SAMV7_AFEC1_SWTRIG
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.trigger = 0,
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#else
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.trigger = 1,
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.timer_channel = CONFIG_SAMV7_AFEC1_TIOACHAN,
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.frequency = CONFIG_SAMV7_AFEC1_TIOAFREQ,
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#endif
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.base = SAM_AFEC1_BASE,
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};
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static struct adc_dev_s g_adcdev1 =
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{
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.ad_ops = &g_adcops,
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.ad_priv = &g_adcpriv0,
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.ad_priv = &g_adcpriv1,
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};
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gpio_pinset_t g_adcpinlist1[ADC_MAX_CHANNELS] =
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@ -189,6 +266,405 @@ static uint32_t afec_getreg(FAR struct samv7_dev_s *priv, uint32_t offset)
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return getreg32(priv->base + offset);
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}
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/****************************************************************************
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* DMA Helpers
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****************************************************************************/
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/****************************************************************************
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* Name: sam_afec_dmadone
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*
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* Description:
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* This function executes on the worker thread. It is scheduled by
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* sam_adc_dmacallback at the complete of each DMA sequenece. There is
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* and interlock using ping-pong buffers and boolean values to prevent
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* overrunning the worker thread:
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*
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* oddbuf[]/evenbuf[] - Ping pong buffers are used. The DMA collects
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* data in one buffer while the worker thread processes data in the
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* other.
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* odd - If true, then DMA is active in the oddbuf[]; evenbuf[] holds
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* completed DMA data.
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* ready - Ping ponging is halted while ready is false; If data overrun
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* occurs, then sample data will be lost on one sequence. The worker
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* thread sets ready when it has completed processing the last sample
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* data.
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*
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* Input Parameters:
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* arg - The ADC private data structure cast to (void *)
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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#ifdef CONFIG_SAMV7_AFEC_DMA
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static void sam_afec_dmadone(void *arg)
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{
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FAR struct adc_dev_s *dev = (FAR struct adc_dev_s *)arg;
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FAR struct samv7_dev_s *priv = (FAR struct samv7_dev_s *)dev->ad_priv;
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uint32_t *buffer;
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uint32_t *next;
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uint32_t sample;
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int chan;
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int i;
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ainfo("ready=%d enabled=%d\n", priv->enabled, priv->ready);
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DEBUGASSERT(priv != NULL && !priv->ready);
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/* If the DMA transfer is not enabled, just ignore the data (and do not
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* start the next DMA transfer).
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*/
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if (priv->enabled)
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{
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/* Toggle to the next buffer.
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*
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* buffer - The buffer on which the DMA has just completed
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* next - The buffer in which to start the next DMA
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*/
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if (priv->odd)
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{
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buffer = priv->oddbuf;
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next = priv->evenbuf;
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priv->odd = false;
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}
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else
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{
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buffer = priv->evenbuf;
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next = priv->oddbuf;
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priv->odd = true;
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}
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/* Restart the DMA conversion as quickly as possible using the next
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* buffer.
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*/
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sam_afec_dmasetup(dev, (FAR uint8_t *)next,
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priv->nsamples * sizeof(uint32_t));
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/* Invalidate the DMA buffer so that we are guaranteed to reload the
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* newly DMAed data from RAM.
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*/
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up_invalidate_dcache((uintptr_t)buffer,
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(uintptr_t)buffer +
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priv->nsamples * sizeof(uint32_t));
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/* Process each sample */
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for (i = 0; i < priv->nsamples; i++, buffer++)
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{
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/* Get the sample and the channel number */
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chan = (int)((*buffer & AFEC_LCDR_CHANB_MASK) >>
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AFEC_LCDR_CHANB_SHIFT);
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sample = ((*buffer & AFEC_LCDR_LDATA_MASK) >>
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AFEC_LCDR_LDATA_SHIFT);
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/* Verify the upper-half driver has bound its callback functions */
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if (priv->cb != NULL)
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{
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/* Give the sample data to the ADC upper half */
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DEBUGASSERT(priv->cb->au_receive != NULL);
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priv->cb->au_receive(dev, chan, sample);
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}
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}
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}
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/* We are ready to handle the next sample sequence */
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priv->ready = true;
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}
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/****************************************************************************
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* Name: sam_afec_dmacallback
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*
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* Description:
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* Called when one ADC DMA sequence completes. This function defers
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* processing of the samples to sam_adc_dmadone which runs on the worker
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* thread.
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*
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****************************************************************************/
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static void sam_afec_dmacallback(DMA_HANDLE handle, void *arg, int result)
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{
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FAR struct adc_dev_s *dev = (FAR struct adc_dev_s *)arg;
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FAR struct samv7_dev_s *priv = (FAR struct samv7_dev_s *)dev->ad_priv;
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int ret;
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ainfo("ready=%d enabled=%d\n", priv->enabled, priv->ready);
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DEBUGASSERT(priv->ready);
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/* Check of the bottom half is keeping up with us.
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*
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* ready == false: Would mean that the worker thready has not ran since
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* the last DMA callback.
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* enabled == false: Means that the upper half has asked us nicely to stop
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* transferring DMA data.
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*/
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if (priv->ready && priv->enabled)
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{
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/* Verify that the worker is available */
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DEBUGASSERT(priv->work.worker == NULL);
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/* Mark the work as busy and schedule the DMA done processing to
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* occur on the worker thread.
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*/
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priv->ready = false;
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ret = work_queue(HPWORK, &priv->work, sam_afec_dmadone, dev, 0);
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if (ret != 0)
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{
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aerr("ERROR: Failed to queue work: %d\n", ret);
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}
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}
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}
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/****************************************************************************
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* Name: sam_afec_dmasetup
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*
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* Description:
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* Setup to perform a read DMA. If the processor supports a data cache,
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* then this method will also make sure that the contents of the DMA memory
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* and the data cache are coherent. For read transfers this may mean
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* invalidating the data cache.
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*
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* Input Parameters:
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* priv - An instance of the ADC device interface
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* buffer - The memory to DMA from
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* buflen - The size of the DMA transfer in bytes
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*
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* Returned Value:
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* OK on success; a negated errno on failure
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*
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****************************************************************************/
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static int sam_afec_dmasetup(FAR struct adc_dev_s *dev, FAR uint8_t *buffer,
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size_t buflen)
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{
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FAR struct samv7_dev_s *priv = (FAR struct samv7_dev_s *)dev->ad_priv;
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uint32_t paddr;
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uint32_t maddr;
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ainfo("buffer=%p buflen=%d\n", buffer, (int)buflen);
|
||||
DEBUGASSERT(priv != NULL && buffer != NULL && buflen > 0);
|
||||
DEBUGASSERT(((uint32_t)buffer & 3) == 0);
|
||||
|
||||
/* Physical address of the ADC LCDR register and of the buffer location in
|
||||
* RAM.
|
||||
*/
|
||||
|
||||
paddr = priv->base + SAM_AFEC_LCDR_OFFSET;
|
||||
maddr = (uintptr_t)buffer;
|
||||
|
||||
/* Configure the RX DMA */
|
||||
|
||||
sam_dmarxsetup(priv->dma, paddr, maddr, buflen);
|
||||
|
||||
/* Start the DMA */
|
||||
|
||||
sam_dmastart(priv->dma, sam_afec_dmacallback, dev);
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_afec_dmastart
|
||||
*
|
||||
* Description:
|
||||
* Initiate DMA sampling.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void sam_afec_dmastart(struct adc_dev_s *dev)
|
||||
{
|
||||
FAR struct samv7_dev_s *priv = (FAR struct samv7_dev_s *)dev->ad_priv;
|
||||
|
||||
/* Make sure that the worker is available and that DMA is not disabled */
|
||||
|
||||
if (priv->ready && priv->enabled)
|
||||
{
|
||||
priv->odd = false; /* Start with the even buffer */
|
||||
sam_afec_dmasetup(dev, (FAR uint8_t *)priv->evenbuf,
|
||||
priv->nsamples * sizeof(uint32_t));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_adc_settimer
|
||||
*
|
||||
* Description:
|
||||
* Configure a timer to trigger the sampling periodically
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SAMV7_AFEC_TIOATRIG
|
||||
static int sam_afec_settimer(struct samv7_dev_s *priv, uint32_t frequency,
|
||||
int channel)
|
||||
{
|
||||
uint32_t div;
|
||||
uint32_t tcclks;
|
||||
uint32_t actual;
|
||||
uint32_t mode;
|
||||
uint32_t fdiv;
|
||||
uint32_t regval;
|
||||
int ret;
|
||||
|
||||
ainfo("frequency=%ld channel=%d\n", (long)frequency, channel);
|
||||
DEBUGASSERT(priv && frequency > 0);
|
||||
|
||||
/* Configure TC for a 1Hz frequency and trigger on RC compare. */
|
||||
|
||||
ret = sam_tc_clockselect(frequency, &tcclks, &actual);
|
||||
if (ret < 0)
|
||||
{
|
||||
aerr("ERROR: sam_tc_divisor failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
div = BOARD_MCK_FREQUENCY / actual;
|
||||
|
||||
/* Set the timer/counter waveform mode the clock input selected by
|
||||
* sam_tc_clockselect()
|
||||
*/
|
||||
|
||||
mode = ((tcclks << TC_CMR_TCCLKS_SHIFT) | /* Use selected TCCLKS value */
|
||||
TC_CMR_WAVSEL_UPRC | /* UP mode w/ trigger on RC Compare */
|
||||
TC_CMR_WAVE | /* Wave mode */
|
||||
TC_CMR_ACPA_CLEAR | /* RA Compare Effect on TIOA: Clear */
|
||||
TC_CMR_ACPC_SET); /* RC effect on TIOA: Set */
|
||||
|
||||
/* Now allocate and configure the channel */
|
||||
|
||||
priv->tc = sam_tc_allocate(channel, mode);
|
||||
if (!priv->tc)
|
||||
{
|
||||
aerr("ERROR: Failed to allocate channel %d mode %08lx\n",
|
||||
channel, mode);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* The divider returned by sam_tc_clockselect() is the reload value
|
||||
* that will achieve a 1Hz rate. We need to multiply this to get the
|
||||
* desired frequency. sam_tc_divisor() should have already assure
|
||||
* that we can do this without overflowing a 32-bit unsigned integer.
|
||||
*/
|
||||
|
||||
fdiv = div * frequency;
|
||||
DEBUGASSERT(div > 0 && div <= fdiv); /* Will check for integer overflow */
|
||||
|
||||
/* Calculate the actual counter value from this divider and the tc input
|
||||
* frequency.
|
||||
*/
|
||||
|
||||
regval = BOARD_MCK_FREQUENCY / fdiv;
|
||||
|
||||
/* Set up TC_RA and TC_RC. The frequency is determined by RA and RC:
|
||||
* TIOA is cleared on RA match; TIOA is set on RC match.
|
||||
*/
|
||||
|
||||
sam_tc_setregister(priv->tc, TC_REGA, regval >> 1);
|
||||
sam_tc_setregister(priv->tc, TC_REGC, regval);
|
||||
|
||||
/* And start the timer */
|
||||
|
||||
sam_tc_start(priv->tc);
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_afec_freetimer
|
||||
*
|
||||
* Description:
|
||||
* Configure a timer to trigger the sampling periodically
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static void sam_afec_freetimer(struct samv7_dev_s *priv)
|
||||
{
|
||||
/* Is a timer allocated? */
|
||||
|
||||
ainfo("tc=%p\n", priv->tc);
|
||||
|
||||
if (priv->tc)
|
||||
{
|
||||
/* Yes.. stop it and free it */
|
||||
|
||||
sam_tc_stop(priv->tc);
|
||||
sam_tc_free(priv->tc);
|
||||
priv->tc = NULL;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_afec_trigger
|
||||
*
|
||||
* Description:
|
||||
* Configure trigger mode and start conversion.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int sam_afec_trigger(struct samv7_dev_s *priv)
|
||||
{
|
||||
uint32_t regval;
|
||||
int ret = OK;
|
||||
|
||||
#ifdef CONFIG_SAMV7_AFEC_SWTRIG
|
||||
if (priv->trigger == 0)
|
||||
{
|
||||
ainfo("Setup software trigger\n");
|
||||
|
||||
/* Configure the software trigger */
|
||||
|
||||
regval = afec_getreg(priv, SAM_AFEC_MR_OFFSET);
|
||||
regval &= ~AFEC_MR_TRGSEL_MASK;
|
||||
afec_putreg(priv, SAM_AFEC_MR_OFFSET, regval);
|
||||
}
|
||||
#elif CONFIG_SAMV7_AFEC_TIOATRIG
|
||||
if (priv->trigger == 1)
|
||||
{
|
||||
ainfo("Setup timer/counter trigger\n");
|
||||
|
||||
/* Start the timer */
|
||||
|
||||
ret = sam_afec_settimer(priv, priv->frequency, priv->timer_channel);
|
||||
if (ret < 0)
|
||||
{
|
||||
aerr("ERROR: sam_afec_settimer failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* AFEC_MR registr still needs to select corresponding channels with
|
||||
* 1, 2, 3 values (see TRGSEL bitfield description) even if channels
|
||||
* 3, 4 and 5 are selected for AFEC1
|
||||
*/
|
||||
|
||||
if (priv->intf == 1)
|
||||
{
|
||||
priv->timer_channel -= 3;
|
||||
}
|
||||
|
||||
/* Set trigger for AFECn driver */
|
||||
|
||||
regval = afec_getreg(priv, SAM_AFEC_MR_OFFSET);
|
||||
regval &= ~AFEC_MR_TRGSEL_MASK;
|
||||
|
||||
regval |= ((priv->timer_channel + 1) << AFEC_MR_TRGSEL_SHIFT) | \
|
||||
AFEC_MR_TRGEN;
|
||||
|
||||
afec_putreg(priv, SAM_AFEC_MR_OFFSET, regval);
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: afec_bind
|
||||
*
|
||||
@ -231,6 +707,22 @@ static void afec_reset(FAR struct adc_dev_s *dev)
|
||||
goto exit_leave_critical;
|
||||
}
|
||||
|
||||
/* Stop any ongoing DMA */
|
||||
|
||||
#ifdef CONFIG_SAMV7_AFEC_DMA
|
||||
if (priv->dma)
|
||||
{
|
||||
sam_dmastop(priv->dma);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SAMV7_AFEC_TIOATRIG
|
||||
if (priv->trigger == 1)
|
||||
{
|
||||
sam_afec_freetimer(priv);
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure clock gating */
|
||||
|
||||
switch (priv->intf)
|
||||
@ -368,6 +860,19 @@ static int afec_setup(FAR struct adc_dev_s *dev)
|
||||
uint32_t afec_cselr = AFEC_CSELR_CSEL(priv->chanlist[priv->current]);
|
||||
afec_putreg(priv, SAM_AFEC_CSELR_OFFSET, afec_cselr);
|
||||
|
||||
#ifdef CONFIG_SAMV7_AFEC_DMA
|
||||
/* Initiate DMA transfers */
|
||||
|
||||
priv->ready = true; /* Worker is available */
|
||||
priv->enabled = true; /* Transfers are enabled */
|
||||
|
||||
sam_afec_dmastart(dev);
|
||||
#endif
|
||||
|
||||
/* Setup AFEC trigger */
|
||||
|
||||
ret = sam_afec_trigger(priv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -382,6 +887,25 @@ static int afec_setup(FAR struct adc_dev_s *dev)
|
||||
static void afec_rxint(FAR struct adc_dev_s *dev, bool enable)
|
||||
{
|
||||
FAR struct samv7_dev_s *priv = (FAR struct samv7_dev_s *)dev->ad_priv;
|
||||
|
||||
#ifdef CONFIG_SAMV7_AFEC_DMA
|
||||
/* Ignore redundant requests */
|
||||
|
||||
if (priv->enabled != enable)
|
||||
{
|
||||
/* Set a flag. If disabling, the DMA sequence will terminate at the
|
||||
* completion of the next DMA.
|
||||
*/
|
||||
|
||||
priv->enabled = enable;
|
||||
|
||||
/* If enabling, then we need to restart the DMA transfer */
|
||||
|
||||
sam_afec_dmastart(dev);
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
uint32_t afec_ixr = 0;
|
||||
|
||||
for (int i = 0; i < priv->nchannels; i++)
|
||||
@ -399,6 +923,7 @@ static void afec_rxint(FAR struct adc_dev_s *dev, bool enable)
|
||||
{
|
||||
afec_putreg(priv, SAM_AFEC_IDR_OFFSET, afec_ixr);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@ -423,6 +948,10 @@ static void afec_shutdown(FAR struct adc_dev_s *dev)
|
||||
return;
|
||||
}
|
||||
|
||||
/* Reset ADC driver */
|
||||
|
||||
afec_reset(dev);
|
||||
|
||||
/* Disable ADC interrupts */
|
||||
|
||||
up_disable_irq(priv->irq);
|
||||
@ -455,11 +984,13 @@ static int afec_ioctl(FAR struct adc_dev_s *dev, int cmd, unsigned long arg)
|
||||
|
||||
switch (cmd)
|
||||
{
|
||||
#ifndef CONFIG_SAMV7_AFEC_TIOATRIG
|
||||
case ANIOC_TRIGGER:
|
||||
{
|
||||
afec_putreg(priv, SAM_AFEC_CR_OFFSET, AFEC_CR_START);
|
||||
}
|
||||
break;
|
||||
#endif
|
||||
case ANIOC_GET_NCHANNELS:
|
||||
{
|
||||
/* Return the number of configured channels */
|
||||
@ -519,7 +1050,7 @@ static int afec_interrupt(int irq, void *context, FAR void *arg)
|
||||
priv->current = 0;
|
||||
}
|
||||
|
||||
/* Start the next conversion */
|
||||
/* Setup the next conversion */
|
||||
|
||||
uint32_t afec_cselr = AFEC_CSELR_CSEL(priv->chanlist[priv->current]);
|
||||
afec_putreg(priv, SAM_AFEC_CSELR_OFFSET, afec_cselr);
|
||||
@ -589,6 +1120,12 @@ FAR struct adc_dev_s *sam_afec_initialize(int intf,
|
||||
priv->nchannels = nchannels;
|
||||
memcpy(priv->chanlist, chanlist, nchannels);
|
||||
|
||||
#ifdef CONFIG_SAMV7_AFEC_DMA
|
||||
priv->nsamples = priv->nchannels * CONFIG_SAMV7_AFEC_DMASAMPLES;
|
||||
priv->dma = sam_dmachannel(0, DMA_FLAGS | \
|
||||
DMACH_FLAG_PERIPHPID(priv->pid));
|
||||
#endif
|
||||
|
||||
ainfo("intf: %d nchannels: %d\n", priv->intf, priv->nchannels);
|
||||
|
||||
return dev;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user