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SAM4S: GPIO, chip characteristics, peripheral Kconfig

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This commit is contained in:
Gregory Nutt 2013-06-11 12:28:31 -06:00
parent da0526f0bd
commit ce8b9c0d3c
13 changed files with 731 additions and 150 deletions
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2
ChangeLog
View File

@ -4945,4 +4945,6 @@
Add SAM4S memory map and interrupt definitions (2013-6-10)
* configs/sam4s-xplained: Add framework for the SAM4S Xplained board.
There is not much there on initial checkin (2013-6-10).
* arch/arm/src/sam34: SAM3S support: GPIO, chip characteristics,
peripheral Kconfig (2013-6-11).

290
arch/arm/include/sam34/chip.h
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@ -54,20 +54,20 @@
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256Kb */
# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */
# define CONFIG_SAM34_SRAM1_SIZE (16*1024) /* 16Kb */
# define CONFIG_SAM34_NFCSRAM_SIZE (4*1024) /* 4Kb */
# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256KB */
# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32KB */
# define CONFIG_SAM34_SRAM1_SIZE (16*1024) /* 16KB */
# define CONFIG_SAM34_NFCSRAM_SIZE (4*1024) /* 4KB */
/* Peripherals */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 1 /* One USB high speed device */
# define SAM32_NUDPFS 0 /* No USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
# define SAM34_NDMACHAN 4 /* 4 DMA Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 1 /* One USB high speed device */
# define SAM32_NUDPFS 0 /* No USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
/* AT91SAM4L Family *****************************************************************/
/* Sub-family differences:
@ -123,84 +123,85 @@
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (128*1024) /* 128Kb */
# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
# define CONFIG_SAM34_FLASH_SIZE (128*1024) /* 128KB */
# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32KB */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
/* Peripherals */
# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM32_NSLCD 1 /* 1 segment LCD interface */
# define SAM32_NAESA 1 /* 1 advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */
# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM32_NSLCD 1 /* 1 segment LCD interface */
# define SAM32_NAESA 1 /* 1 advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4LC4C) || defined (CONFIG_ARCH_CHIP_ATSAM4LC4B) || \
defined(CONFIG_ARCH_CHIP_ATSAM4LC4A)
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256Kb */
# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256KB */
# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32KB */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
/* Peripherals */
# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM32_NSLCD 1 /* 1 segment LCD interface */
# define SAM32_NAESA 1 /* 1 advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */
# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM32_NSLCD 1 /* 1 segment LCD interface */
# define SAM32_NAESA 1 /* 1 advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 1 /* 1 USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4LS2C) || defined (CONFIG_ARCH_CHIP_ATSAM4LS2B) || \
defined(CONFIG_ARCH_CHIP_ATSAM4LS2A)
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (128*1024) /* 128Kb */
# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
# define CONFIG_SAM34_FLASH_SIZE (128*1024) /* 128KB */
# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32KB */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
/* Peripherals */
# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4LS4C) || defined (CONFIG_ARCH_CHIP_ATSAM4LS4B) || \
defined(CONFIG_ARCH_CHIP_ATSAM4LS4A)
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256Kb */
# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32Kb */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
# define CONFIG_SAM34_FLASH_SIZE (256*1024) /* 256KB */
# define CONFIG_SAM34_SRAM0_SIZE (32*1024) /* 32KB */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
/* Peripherals */
# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
# define SAM34_NDMACHAN 16 /* 16 Peripheral DMA Channels */
# define SAM34_NMCI2 0 /* No memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
/* AT91SAM4S Family *****************************************************************/
/*
* FEATURE SAM4SD32C SAM4SD32B SAM4SD16C SAM4SD16B SAM4SA16C SAM4SA16B SAM4S16C SAM4S16B SAM4S8C SAM4S8B
* ------------- --------- --------- --------- --------- --------- --------- -------- -------- ------- -------
* Flash 2x1MB 2x1MB 2x512KB 1x1MB 1x1MB 1x1MB 1x1MB 1x1MB 1x512KB 1x512KB
* SRAM 160KB 160KB 160KB 160KB 160KB 160KB 128KB 128KB 128KB 128KB
* HCACHE 2KB 2KB 2KB 2KB 2KB 2KB - - - -
@ -217,25 +218,184 @@
*/
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD32C)
# error To be provided
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (2*1024*1024) /* 2x1MB */
# define CONFIG_SAM34_SRAM0_SIZE (160*1024) /* 160KB */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD32B)
# error To be provided
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (2*1024*1024) /* 2x1MB */
# define CONFIG_SAM34_SRAM0_SIZE (160*1024) /* 160KB */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD16C)
# error To be provided
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (1024*1024) /* 2x512KB */
# define CONFIG_SAM34_SRAM0_SIZE (160*1024) /* 160KB */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD16B)
# error To be provided
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (1024*1024) /* 2x512KB */
# define CONFIG_SAM34_SRAM0_SIZE (160*1024) /* 160KB */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SA16C)
# error To be provided
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (1024*1024) /* 1MB */
# define CONFIG_SAM34_SRAM0_SIZE (160*1024) /* 160KB */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SA16B)
# error To be provided
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (1024*1024) /* 1MB */
# define CONFIG_SAM34_SRAM0_SIZE (160*1024) /* 160KB */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S16C)
# error To be provided
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (1024*1024) /* 1MB */
# define CONFIG_SAM34_SRAM0_SIZE (128*1024) /* 128KB */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S16B)
# error To be provided
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (1024*1024) /* 1MB */
# define CONFIG_SAM34_SRAM0_SIZE (128*1024) /* 128KB */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S8C)
# error To be provided
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (512*1024) /* 512KB */
# define CONFIG_SAM34_SRAM0_SIZE (128*1024) /* 128KB */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S8B)
# error To be provided
/* Internal memory */
# define CONFIG_SAM34_FLASH_SIZE (512*1024) /* 512KB */
# define CONFIG_SAM34_SRAM0_SIZE (128*1024) /* 128KB */
# define CONFIG_SAM34_SRAM1_SIZE (0) /* None */
# define CONFIG_SAM34_NFCSRAM_SIZE (0) /* None */
/* Peripherals */
# define SAM34_NDMACHAN 22 /* 22 PDC Channels */
# define SAM34_NMCI2 1 /* 1 memory card interface */
# define SAM32_NSLCD 0 /* No segment LCD interface */
# define SAM32_NAESA 0 /* No advanced encryption standard */
# define SAM32_NUDPHS 0 /* No USB high speed device */
# define SAM32_NUDPFS 1 /* 1 USB full speed device */
# define SAM32_NUHPFS 0 /* No USB full speed embedded host */
#else
# error "Unknown SAM3/4 chip type"

146
arch/arm/src/sam34/Kconfig
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@ -159,7 +159,7 @@ config SAM34_APBA
depends on ARCH_CHIP_SAM4L
config SAM34_AESA
bool "Advanced Encryption Standard"
bool "Advanced Encryption Standard (AESA)"
default n
depends on ARCH_CHIP_SAM4L
@ -169,57 +169,82 @@ config SAM34_IISC
depends on ARCH_CHIP_SAM4L
config SAM34_SPI
bool "SPI"
bool "Serial Peripheral Interface (SPI)"
default n
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4L
config SAM34_SSC
bool "Synchronous Serial Controller (SSC)"
default n
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S
config SAM34_TC0
bool "Timer/Counter 0"
bool "Timer/Counter 0 (TC0)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_TC1
bool "Timer/Counter 1"
bool "Timer/Counter 1 (TC1)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_TC2
bool "Timer/Counter 2 (TC2)"
default n
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S
config SAM34_TC3
bool "Timer/Counter 3 (TC3)"
default n
depends on ARCH_CHIP_SAM4S
config SAM34_TC4
bool "Timer/Counter 4 (TC4)"
default n
depends on ARCH_CHIP_SAM4S
config SAM34_TC5
bool "Timer/Counter 5 (TC5)"
default n
depends on ARCH_CHIP_SAM4S
config SAM34_PWM
bool "Pulse Width Modulation (PWM) Controller"
default n
depends on ARCH_CHIP_SAM3U|| ARCH_CHIP_SAM4S
config SAM34_TWIM0
bool "Two-wire Master Interface 0"
bool "Two-wire Master Interface 0 (TWIM0)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_TWIS0
bool "Two-wire Slave Interface 0"
bool "Two-wire Slave Interface 0 (TWIS0)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_TWIM1
bool "Two-wire Master Interface 1"
bool "Two-wire Master Interface 1 (TWIM1)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_TWIS1
bool "Two-wire Slave Interface 1"
bool "Two-wire Slave Interface 1 (TWIS1)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_TWIM2
bool "Two-wire Master Interface 2"
bool "Two-wire Master Interface 2 (TWIM2)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_TWIM3
bool "Two-wire Master Interface 3"
bool "Two-wire Master Interface 3 (TWIM3)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_UART0
bool "UART0"
bool "UART 0"
default y
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S
select ARCH_HAVE_UART0
config SAM43_UART1
bool "UART1"
bool "UART 1"
default y
depends on ARCH_CHIP_SAM4S
select ARCH_HAVE_UART1
@ -231,39 +256,45 @@ config SAM34_PICOUART
select ARCH_HAVE_UART
config SAM34_USART0
bool "USART0"
bool "USART 0"
default n
select ARCH_HAVE_USART0
config SAM34_USART1
bool "USART1"
bool "USART 1"
default n
select ARCH_HAVE_USART1
config SAM34_USART2
bool "USART2"
bool "USART 2"
default n
select ARCH_HAVE_USART2
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4L
config SAM34_USART3
bool "USART3"
bool "USART 3"
default n
select ARCH_HAVE_USART3
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4L
config SAM34_ADCIFE
bool "ADC controller interface"
config SAM34_ADC12B
bool "12-bit ADC Controller"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_ADC
bool "10-bit ADC Controller"
default n
depends on ARCH_CHIP_SAM3U
config SAM34_DACC
bool "DAC Controller"
bool "Digital To Analog Converter (DAC)"
default n
depends on ARCH_CHIP_SAM4L
depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S
config SAM34_ACIFC
bool "Analog Comparator Interface"
config SAM34_ACC
bool "Analog Comparator (AC)"
default n
depends on ARCH_CHIP_SAM4L
depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S
config SAM34_GLOC
bool "GLOC"
@ -271,27 +302,27 @@ config SAM34_GLOC
depends on ARCH_CHIP_SAM4L
config SAM34_ABDACB
bool "Audio Bitstream DAC"
bool "Audio Bitstream DAC (ABDAC)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_TRNG
bool "True Random Number Generator"
bool "True Random Number Generator (TRNG)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_PARC
bool "Parallel Capture"
bool "Parallel Capture (PARC)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_CATB
bool "Capacitive Touch Module B"
bool "Capacitive Touch Module B (CATB)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_LCDCA
bool "LCD Controller A"
bool "LCD Controller A (LCDCA)"
default n
depends on ARCH_CHIP_SAM4L
@ -300,6 +331,11 @@ config SAM34_HRAMC1
default n
depends on ARCH_CHIP_SAM4L
config SAM34_SMC
bool "Static Memory Controller (SMC)"
default n
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S
config SAM34_NAND
bool "NAND support"
default n
@ -311,13 +347,13 @@ config SAM34_HMATRIX
depends on ARCH_CHIP_SAM4L
config SAM34_PDCA
bool "Peripheral DMA controller"
bool "Peripheral DMA controller (PDC)"
default n
depends on ARCH_CHIP_SAM4L
depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S
select ARCH_DMA
config SAM34_DMA
bool "DMA"
bool "DMA controller"
default n
depends on ARCH_CHIP_SAM3U
select ARCH_DMA
@ -325,7 +361,17 @@ config SAM34_DMA
config SAM34_CRCCU
bool "CRC Calculation Unit"
default n
depends on ARCH_CHIP_SAM4L
depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S
config SAM34_UDPHS
bool "USB Device High Speed"
default n
depends on ARCH_CHIP_SAM3U
config SAM34_UDP
bool "USB Device Full Speed"
default n
depends on ARCH_CHIP_SAM4S
config SAM34_USBC
bool "USB 2.0 Interface"
@ -343,28 +389,38 @@ config SAM34_CHIPID
depends on ARCH_CHIP_SAM4L
config SAM34_FREQM
bool "Frequency Mete"
bool "Frequency Meter (FREQM)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_AST
bool "Asynchronous Timer"
bool "Asynchronous Timer (AST)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_RTC
bool "Real Time Clock (RTC)"
default n
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S
config SAM34_RTT
bool "Real Time Timer (RTT)"
default n
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S
config SAM34_WDT
bool "Watchdog Timer"
bool "Watchdog Timer (WDT)"
default n
config SAM34_EIC
bool "External Interrupt Controller"
bool "External Interrupt Controller (EIC)"
default n
depends on ARCH_CHIP_SAM4L
config SAM34_HSMCI
bool "HSMCI"
bool "High Speed Multimedia Card Interface (HSMCI)"
default n
depends on ARCH_CHIP_SAM3U
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4S
endmenu

12
arch/arm/src/sam34/chip/sam3u_pio.h
View File

@ -300,15 +300,15 @@
/* PIO Write Protect Mode Register */
#define PIO_WPMR_WPEN 1 << 0) /* Bit 0: Write Protect Enable */
#define PIO_WPMR_WPKEY_SHIFT 8) /* Bits 8-31: Write Protect KEY */
#define PIO_WPMR_WPKEY_MASK 0xffffff << PIO_WPMR_WPKEY_SHIFT)
#define PIO_WPMR_WPEN (1 << 0) /* Bit 0: Write Protect Enable */
#define PIO_WPMR_WPKEY_SHIFT (8) /* Bits 8-31: Write Protect KEY */
#define PIO_WPMR_WPKEY_MASK (0xffffff << PIO_WPMR_WPKEY_SHIFT)
/* PIO Write Protect Status Register */
#define PIO_WPSR_WPVS 1 << 0) /* Bit 0: Write Protect Violation Status */
#define PIO_WPSR_WPVSRC_SHIFT 8) /* Bits 8-23: Write Protect Violation Source */
#define PIO_WPSR_WPVSRC_MASK 0xffff << PIO_WPSR_WPVSRC_SHIFT)
#define PIO_WPSR_WPVS (1 << 0) /* Bit 0: Write Protect Violation Status */
#define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT)
/****************************************************************************************
* Public Types

10
arch/arm/src/sam34/chip/sam4s_pio.h
View File

@ -58,7 +58,7 @@
/* 0x000c: Reserved */
#define SAM_PIO_OER_OFFSET 0x0010 /* Output Enable Register */
#define SAM_PIO_ODR_OFFSET 0x0014 /* Output Disable Register */
#define SAM_PIO_OSR_OFFSET 0x0018 /* utput Status Register */
#define SAM_PIO_OSR_OFFSET 0x0018 /* Output Status Register */
/* 0x001c: Reserved */
#define SAM_PIO_IFER_OFFSET 0x0020 /* Glitch Input Filter Enable Register */
#define SAM_PIO_IFDR_OFFSET 0x0024 /* Glitch Input Filter Disable Register */
@ -83,13 +83,13 @@
#define SAM_PIO_ABCDSR1_OFFSET 0x0070 /* Peripheral Select Register 1 */
#define SAM_PIO_ABCDSR2_OFFSET 0x0074 /* Peripheral Select Register 2 */
/* 0x0078-0x007c: Reserved */
#define SAM_PIO_IFSCDR_OFFSET 0x0080 /* SInput Filter Slow Clock Disable Register */
#define SAM_PIO_IFSCDR_OFFSET 0x0080 /* Input Filter Slow Clock Disable Register */
#define SAM_PIO_IFSCER_OFFSET 0x0084 /* Input Filter Slow Clock Enable Register */
#define SAM_PIO_IFSCSR_OFFSET 0x0088 /* Input Filter Slow Clock Status Register */
#define SAM_PIO_SCDR_OFFSET 0x008c /* Slow Clock Divider Debouncing Register */
#define SAM_PIO_PPDDR_OFFSET 0x0090 /* Pad Pull-down Enable Register */
#define SAM_PIO_PPDER_OFFSET 0x0094 /* Pad Pull-down Status Register */
#define SAM_PIO_PPDSR_OFFSET 0x0098 /* Input Filter Slow Clock Disable Register */
#define SAM_PIO_PPDDR_OFFSET 0x0090 /* Pad Pull Down Disable Register */
#define SAM_PIO_PPDER_OFFSET 0x0094 /* PIO Pad Pull Down Enable Register */
#define SAM_PIO_PPDSR_OFFSET 0x0098 /* PIO Pad Pull Down Status Register */
/* 0x009c: Reserved */
#define SAM_PIO_OWER_OFFSET 0x00a0 /* Output Write Enable */
#define SAM_PIO_OWDR_OFFSET 0x00a4 /* Output Write Disable */

127
arch/arm/src/sam34/sam3u_gpio.c
View File

@ -1,5 +1,6 @@
/****************************************************************************
* arch/arm/src/sam34/sam3u_gpio.c
* General Purpose Input/Output (GPIO) logic for the SAM3U and SAM4S
*
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -111,6 +112,10 @@ static inline int sam_gpiopin(gpio_pinset_t cfgset)
static inline int sam_configinput(uintptr_t base, uint32_t pin,
gpio_pinset_t cfgset)
{
#ifdef GPIO_HAVE_SCHMITT
uint32_t regval;
#endif
/* Disable interrupts on the pin */
putreg32(pin, base + SAM_PIO_IDR_OFFSET);
@ -126,6 +131,19 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
#ifdef GPIO_HAVE_PULLDOWN
/* Enable/disable the pull-down as requested */
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
}
#endif
/* Check if filtering should be enabled */
if ((cfgset & GPIO_CFG_DEGLITCH) != 0)
@ -137,14 +155,29 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
putreg32(pin, base + SAM_PIO_IFDR_OFFSET);
}
#ifdef GPIO_HAVE_SCHMITT
/* Enable/disable the Schmitt trigger */
regval = getreg32(base + SAM_PIO_SCHMITT_OFFSET);
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
regval |= pin;
}
else
{
regval &= ~pin;
}
putreg32(regval, base + SAM_PIO_SCHMITT_OFFSET);
#endif
/* Configure the pin as an input and enable the GPIO function */
putreg32(pin, base + SAM_PIO_ODR_OFFSET);
putreg32(pin, base + SAM_PIO_PER_OFFSET);
/* To-Do: If DEGLITCH is selected, need to configure DIFSR, SCIFSR, and
* registers. This would probably best be done with another, new
* API... perhaps sam_configfilter()
* IFDGSR registers. This would probably best be done with
* another, new API... perhaps sam_configfilter()
*/
return OK;
@ -176,6 +209,19 @@ static inline int sam_configoutput(uintptr_t base, uint32_t pin,
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
#ifdef GPIO_HAVE_PULLDOWN
/* Enable/disable the pull-down as requested */
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
}
#endif
/* Enable the open drain driver if requrested */
if ((cfgset & GPIO_CFG_OPENDRAIN) != 0)
@ -234,7 +280,58 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
putreg32(pin, base + SAM_PIO_PUDR_OFFSET);
}
/* Configure pin, depending upon the peripheral A or B*/
#ifdef GPIO_HAVE_PULLDOWN
/* Enable/disable the pull-down as requested */
if ((cfgset & GPIO_CFG_PULLDOWN) != 0)
{
putreg32(pin, base + SAM_PIO_PPDER_OFFSET);
}
else
{
putreg32(pin, base + SAM_PIO_PPDDR_OFFSET);
}
#endif
#ifdef GPIO_HAVE_PERIPHCD
/* Configure pin, depending upon the peripheral A, B, C or D
*
* PERIPHA: ABCDSR1[n] = 0 ABCDSR2[n] = 0
* PERIPHB: ABCDSR1[n] = 1 ABCDSR2[n] = 0
* PERIPHC: ABCDSR1[n] = 0 ABCDSR2[n] = 1
* PERIPHD: ABCDSR1[n] = 1 ABCDSR2[n] = 1
*/
regval = getreg32(base + SAM_PIO_ABCDSR1_OFFSET);
if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA ||
(cfgset & GPIO_MODE_MASK) == GPIO_PERIPHC)
{
regval &= ~pin;
}
else
{
regval |= pin;
}
putreg32(regval, base + SAM_PIO_ABCDSR1_OFFSET);
regval = getreg32(base + SAM_PIO_ABCDSR2_OFFSET);
if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA ||
(cfgset & GPIO_MODE_MASK) == GPIO_PERIPHB)
{
regval &= ~pin;
}
else
{
regval |= pin;
}
putreg32(regval, base + SAM_PIO_ABCDSR2_OFFSET);
#else
/* Configure pin, depending upon the peripheral A or B:
*
* PERIPHA: ABSR[n] = 0
* PERIPHB: ABSR[n] = 1
*/
regval = getreg32(base + SAM_PIO_ABSR_OFFSET);
if ((cfgset & GPIO_MODE_MASK) == GPIO_PERIPHA)
@ -246,6 +343,7 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
regval |= pin;
}
putreg32(regval, base + SAM_PIO_ABSR_OFFSET);
#endif
/* Disable PIO functionality */
@ -375,11 +473,17 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
lldbg(" PDSR: %08x IMR: %08x ISR: %08x MDSR: %08x\n",
getreg32(base + SAM_PIO_PDSR_OFFSET), getreg32(base + SAM_PIO_IMR_OFFSET),
getreg32(base + SAM_PIO_ISR_OFFSET), getreg32(base + SAM_PIO_MDSR_OFFSET));
lldbg(" PUSR: %08x ABSR: %08x SCIFSR: %08x DIFSR: %08x\n",
getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_ABSR_OFFSET),
getreg32(base + SAM_PIO_SCIFSR_OFFSET), getreg32(base + SAM_PIO_DIFSR_OFFSET));
lldbg(" IFDGSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n",
getreg32(base + SAM_PIO_IFDGSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
#if defined(CONFIG_ARCH_CHIP_ATSAM3U)
lldbg(" ABSR: %08x SCIFSR: %08x DIFSR: %08x IFDGSR: %08x\n",
getreg32(base + SAM_PIO_ABSR_OFFSET), getreg32(base + SAM_PIO_SCIFSR_OFFSET),
getreg32(base + SAM_PIO_DIFSR_OFFSET), getreg32(base + SAM_PIO_IFDGSR_OFFSET));
#elif defined(CONFIG_ARCH_CHIP_ATSAM4S)
lldbg(" ABCDSR: %08x %08x IFSCSR: %08x PPDSR: %08x\n",
getreg32(base + SAM_PIO_ABCDSR1_OFFSET), getreg32(base + SAM_PIO_ABCDSR2_OFFSET),
getreg32(base + SAM_PIO_IFSCSR_OFFSET), getreg32(base + SAM_PIOC_PPDSR));
#endif
lldbg(" PUSR: %08x SCDR: %08x OWSR: %08x AIMMR: %08x\n",
getreg32(base + SAM_PIO_PUSR_OFFSET), getreg32(base + SAM_PIO_SCDR_OFFSET),
getreg32(base + SAM_PIO_OWSR_OFFSET), getreg32(base + SAM_PIO_AIMMR_OFFSET));
lldbg(" ESR: %08x LSR: %08x ELSR: %08x FELLSR: %08x\n",
getreg32(base + SAM_PIO_ESR_OFFSET), getreg32(base + SAM_PIO_LSR_OFFSET),
@ -387,6 +491,13 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
lldbg(" FRLHSR: %08x LOCKSR: %08x WPMR: %08x WPSR: %08x\n",
getreg32(base + SAM_PIO_FRLHSR_OFFSET), getreg32(base + SAM_PIO_LOCKSR_OFFSET),
getreg32(base + SAM_PIO_WPMR_OFFSET), getreg32(base + SAM_PIO_WPSR_OFFSET));
#if defined(CONFIG_ARCH_CHIP_ATSAM4S)
lldbg(" PCMR: %08x PCIMR: %08x PCISR: %08x PCRHR: %08x\n",
getreg32(base + SAM_PIO_PCMR_OFFSET), getreg32(base + SAM_PIO_PCIMR_OFFSET),
getreg32(base + SAM_PIO_PCISR_OFFSET), getreg32(base + SAM_PIO_PCRHR_OFFSET));
lldbg("SCHMITT: %08x\n",
getreg32(base + SAM_PIO_SCHMITT_OFFSET));
#endif
irqrestore(flags);
return OK;
}

30
arch/arm/src/sam34/sam3u_gpio.h
View File

@ -1,5 +1,6 @@
/************************************************************************************
* arch/arm/src/sam34/sam3u_gpio.h
* General Purpose Input/Output (GPIO) definitions for the SAM3U
*
* Copyright (C) 2009-2011, 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@ -45,16 +46,22 @@
/************************************************************************************
* Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#undef GPIO_HAVE_PULLDOWN
#undef GPIO_HAVE_PERIPHCD
#undef GPIO_HAVE_SCHMITT
/* Bit-encoded input to sam_configgpio() ********************************************/
/* 16-bit Encoding:
* MMCC CII. VPPB BBBB
*
* MMCC CII. VPPB BBBB
*/
/* Input/Output mode:
*
* MM.. .... .... ....
* MM.. .... .... ....
*/
#define GPIO_MODE_SHIFT (14) /* Bits 14-15: GPIO mode */
@ -65,7 +72,8 @@
# define GPIO_PERIPHB (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */
/* These bits set the configuration of the pin:
* ..CC C... .... ....
*
* ..CC C... .... ....
*/
#define GPIO_CFG_SHIFT (11) /* Bits 11-13: GPIO configuration bits */
@ -76,10 +84,11 @@
# define GPIO_CFG_OPENDRAIN (4 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */
/* Additional interrupt modes:
* .... .II. .... ....
*
* .... .II. .... ....
*/
#define GPIO_INT_SHIFT (9) /* Bits 9-10: GPIO configuration bits */
#define GPIO_INT_SHIFT (9) /* Bits 9-10: GPIO interrupt bits */
#define GPIO_INT_MASK (3 << GPIO_INT_SHIFT)
# define GPIO_INT_LEVEL (1 << 10) /* Bit 10: Level detection interrupt */
# define GPIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */
@ -89,14 +98,16 @@
# define GPIO_INT_FALLING (0) /* (vs. Falling edge detection interrupt) */
/* If the pin is an GPIO output, then this identifies the initial output value:
* .... .... V... ....
*
* .... .... V... ....
*/
#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Inital value of output */
#define GPIO_OUTPUT_CLEAR (0)
/* This identifies the GPIO port:
* .... .... .PP. ....
*
* .... .... .PP. ....
*/
#define GPIO_PORT_SHIFT (5) /* Bit 5-6: Port number */
@ -106,10 +117,11 @@
# define GPIO_PORT_PIOC (2 << GPIO_PORT_SHIFT)
/* This identifies the bit in the port:
* .... .... ...B BBBB
*
* .... .... ...B BBBB
*/
#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */
#define GPIO_PIN_SHIFT 0 /* Bits 0-4: GPIO number: 0-31 */
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)

201
arch/arm/src/sam34/sam4s_gpio.h Normal file
View File

@ -0,0 +1,201 @@
/************************************************************************************
* arch/arm/src/sam34/sam4s_gpio.h
* General Purpose Input/Output (GPIO) definitions for the SAM4S
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H
#define __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
/************************************************************************************
* Definitions
************************************************************************************/
/* Configuration ********************************************************************/
#define GPIO_HAVE_PULLDOWN 1
#define GPIO_HAVE_PERIPHCD 1
#define GPIO_HAVE_SCHMITT 1
/* Bit-encoded input to sam_configgpio() ********************************************/
/* 32-bit Encoding:
*
* MMMC CCCC II.. VPPB BBBB
*/
/* Input/Output mode:
*
* MMM. .... .... .... ....
*/
#define GPIO_MODE_SHIFT (17) /* Bits 17-23: GPIO mode */
#define GPIO_MODE_MASK (7 << GPIO_MODE_SHIFT)
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input */
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* Output */
# define GPIO_PERIPHA (2 << GPIO_MODE_SHIFT) /* Controlled by periph A signal */
# define GPIO_PERIPHB (3 << GPIO_MODE_SHIFT) /* Controlled by periph B signal */
# define GPIO_PERIPHC (4 << GPIO_MODE_SHIFT) /* Controlled by periph C signal */
# define GPIO_PERIPHD (5 << GPIO_MODE_SHIFT) /* Controlled by periph D signal */
/* These bits set the configuration of the pin:
* NOTE: No definitions for parallel capture mode
*
* ...C CCCC .... .... ....
*/
#define GPIO_CFG_SHIFT (12) /* Bits 12-16: GPIO configuration bits */
#define GPIO_CFG_MASK (31 << GPIO_CFG_SHIFT)
# define GPIO_CFG_DEFAULT (0 << GPIO_CFG_SHIFT) /* Default, no attribute */
# define GPIO_CFG_PULLUP (1 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-up */
# define GPIO_CFG_PULLDOWN (2 << GPIO_CFG_SHIFT) /* Bit 11: Internal pull-down */
# define GPIO_CFG_DEGLITCH (4 << GPIO_CFG_SHIFT) /* Bit 12: Internal glitch filter */
# define GPIO_CFG_OPENDRAIN (8 << GPIO_CFG_SHIFT) /* Bit 13: Open drain */
# define GPIO_CFG_SCHMITT (16 << GPIO_CFG_SHIFT) /* Bit 13: Schmitt trigger */
/* Additional interrupt modes:
*
* .... .... II.. .... ....
*/
#define GPIO_INT_SHIFT (10) /* Bits 10-11: GPIO interrupt bits */
#define GPIO_INT_MASK (3 << GPIO_INT_SHIFT)
# define GPIO_INT_LEVEL (1 << 10) /* Bit 10: Level detection interrupt */
# define GPIO_INT_EDGE (0) /* (vs. Edge detection interrupt) */
# define GPIO_INT_HIGHLEVEL (1 << 9) /* Bit 9: High level detection interrupt */
# define GPIO_INT_LOWLEVEL (0) /* (vs. Low level detection interrupt) */
# define GPIO_INT_RISING (1 << 9) /* Bit 9: Rising edge detection interrupt */
# define GPIO_INT_FALLING (0) /* (vs. Falling edge detection interrupt) */
/* If the pin is an GPIO output, then this identifies the initial output value:
*
* .... .... .... V... ....
*/
#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: Inital value of output */
#define GPIO_OUTPUT_CLEAR (0)
/* This identifies the GPIO port:
*
* .... .... .... .PP. ....
*/
#define GPIO_PORT_SHIFT (5) /* Bit 5-6: Port number */
#define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT)
# define GPIO_PORT_PIOA (0 << GPIO_PORT_SHIFT)
# define GPIO_PORT_PIOB (1 << GPIO_PORT_SHIFT)
# define GPIO_PORT_PIOC (2 << GPIO_PORT_SHIFT)
/* This identifies the bit in the port:
*
* .... .... .... ...B BBBB
*/
#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO number: 0-31 */
#define GPIO_PIN_MASK (31 << GPIO_PIN_SHIFT)
#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
#define GPIO_PIN16 (16 << GPIO_PIN_SHIFT)
#define GPIO_PIN17 (17 << GPIO_PIN_SHIFT)
#define GPIO_PIN18 (18 << GPIO_PIN_SHIFT)
#define GPIO_PIN19 (19 << GPIO_PIN_SHIFT)
#define GPIO_PIN20 (20 << GPIO_PIN_SHIFT)
#define GPIO_PIN21 (21 << GPIO_PIN_SHIFT)
#define GPIO_PIN22 (22 << GPIO_PIN_SHIFT)
#define GPIO_PIN23 (23 << GPIO_PIN_SHIFT)
#define GPIO_PIN24 (24 << GPIO_PIN_SHIFT)
#define GPIO_PIN25 (25 << GPIO_PIN_SHIFT)
#define GPIO_PIN26 (26 << GPIO_PIN_SHIFT)
#define GPIO_PIN27 (27 << GPIO_PIN_SHIFT)
#define GPIO_PIN28 (28 << GPIO_PIN_SHIFT)
#define GPIO_PIN29 (29 << GPIO_PIN_SHIFT)
#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
/************************************************************************************
* Public Types
************************************************************************************/
/* Must be big enough to hold the 32-bit encoding */
typedef uint32_t gpio_pinset_t;
/************************************************************************************
* Inline Functions
************************************************************************************/
#ifndef __ASSEMBLY__
/************************************************************************************
* Public Data
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/************************************************************************************
* Public Function Prototypes
************************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H */

2
arch/arm/src/sam34/sam_gpio.h
View File

@ -51,6 +51,8 @@
# include "sam3u_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_SAM4L)
# include "sam4l_gpio.h"
#elif defined(CONFIG_ARCH_CHIP_SAMSL)
# include "sam4s_gpio.h"
#else
# error Unrecognized SAM architecture
#endif

1
configs/mikroe-stm32f4/src/mikroe-stm32f4-internal.h
View File

@ -190,7 +190,6 @@
GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN7)
#define GPIO_VS1053_DREQ (GPIO_INPUT|GPIO_SPEED_50MHz|GPIO_PORTC|GPIO_PIN6)
/****************************************************************************************************
* Public Types
****************************************************************************************************/

32
configs/sam3u-ek/README.txt
View File

@ -313,15 +313,28 @@ SAM3U-EK-specific Configuration Options
Individual subsystems can be enabled:
CONFIG_SAM34_DMA
CONFIG_SAM34_HSMCI
CONFIG_SAM34_NAND
CONFIG_SAM34_SPI
CONFIG_SAM34_UART0
CONFIG_SAM34_USART0
CONFIG_SAM34_USART1
CONFIG_SAM34_USART2
CONFIG_SAM34_USART3
CONFIG_SAM34_RTC - Real Time Clock
CONFIG_SAM34_RTT - Real Time Timer
CONFIG_SAM34_WDT - Watchdog Timer
CONFIG_SAM34_UART0 - UART 0
CONFIG_SAM34_SMC - Static Memory Controller
CONFIG_SAM34_USART0 - USART 0
CONFIG_SAM34_USART1 - USART 1
CONFIG_SAM34_USART2 - USART 2
CONFIG_SAM34_USART3 - USART 3
CONFIG_SAM34_HSMCI - High Speed Multimedia Card Interface
CONFIG_SAM34_TWI0 - Two-Wire Interface 0
CONFIG_SAM34_TWI1 - Two-Wire Interface 1
CONFIG_SAM34_SPI - Serial Peripheral Interface
CONFIG_SAM34_SSC - Synchronous Serial Controller
CONFIG_SAM34_TC0 - Timer Counter 0
CONFIG_SAM34_TC1 - Timer Counter 1
CONFIG_SAM34_TC2 - Timer Counter 2
CONFIG_SAM34_PWM - Pulse Width Modulation Controller
CONFIG_SAM34_ADC12B - 12-bit ADC Controller
CONFIG_SAM34_ADC - 10-bit ADC Controller
CONFIG_SAM34_DMA - DMA Controller
CONFIG_SAM34_UDPHS - USB Device High Speed
Some subsystems can be configured to operate in different ways. The drivers
need to know how to configure the subsystem.
@ -333,6 +346,7 @@ SAM3U-EK-specific Configuration Options
CONFIG_USART1_ISUART
CONFIG_USART2_ISUART
CONFIG_USART3_ISUART
CONFIG_SAM34_NAND - NAND memory
AT91SAM3U specific device driver settings

4
configs/sam4l-xplained/README.txt
View File

@ -371,9 +371,9 @@ SAM4L Xplained Pro-specific Configuration Options
CONFIG_SAM34_USART1
CONFIG_SAM34_USART2
CONFIG_SAM34_USART3
CONFIG_SAM34_ADCIFE
CONFIG_SAM34_ADC12B
CONFIG_SAM34_DACC
CONFIG_SAM34_ACIFC
CONFIG_SAM34_ACC
CONFIG_SAM34_GLOC
CONFIG_SAM34_ABDACB
CONFIG_SAM34_TRNG

24
configs/sam4s-xplained/README.txt
View File

@ -401,6 +401,30 @@ SAM4S Xplained-specific Configuration Options
Individual subsystems can be enabled:
CONFIG_SAM34_RTC - Real Time Clock
CONFIG_SAM34_RTT - Real Time Timer
CONFIG_SAM34_WDT - Watchdog Timer
CONFIG_SAM34_UART0 - UART 0
CONFIG_SAM34_UART1 - UART 1
CONFIG_SAM34_SMC - Static Memory Controller
CONFIG_SAM34_USART0 - USART 0
CONFIG_SAM34_USART1 - USART 1
CONFIG_SAM34_HSMCI - High Speed Multimedia Card Interface
CONFIG_SAM34_TWI0 - Two-Wire Interface 0
CONFIG_SAM34_TWI1 - Two-Wire Interface 1
CONFIG_SAM34_SSC - Synchronous Serial Controller
CONFIG_SAM34_TC0 - Timer Counter 0
CONFIG_SAM34_TC1 - Timer Counter 1
CONFIG_SAM34_TC2 - Timer Counter 2
CONFIG_SAM34_TC3 - Timer Counter 3
CONFIG_SAM34_TC4 - Timer Counter 4
CONFIG_SAM34_TC5 - Timer Counter 5
CONFIG_SAM34_ADC12B - 12-bit Analog To Digital Converter
CONFIG_SAM34_DACC - Digital To Analog Converter
CONFIG_SAM34_PWM - Pulse Width Modulation
CONFIG_SAM34_CRCCU - CRC Calculation Unit
CONFIG_SAM34_ACC - Analog Comparator
CONFIG_SAM34_UDP - USB Device Port
Some subsystems can be configured to operate in different ways. The drivers
need to know how to configure the subsystem.