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SAMD21: Update SPI and I2C header files for SAMD21 support

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This commit is contained in:
Gregory Nutt 2015-06-22 13:12:00 -06:00
parent ccadb28730
commit ce9e321598
3 changed files with 333 additions and 65 deletions
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156
arch/arm/src/samdl/chip/samd_i2c_master.h
View File

@ -49,7 +49,7 @@
#include "chip.h"
#include "chip/samd_sercom.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD20
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/********************************************************************************************
* Pre-processor Definitions
@ -58,82 +58,125 @@
#define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */
#define SAM_I2C_BAUD_OFFSET 0x000a /* Baud register */
#define SAM_I2C_DBGCTRL_OFFSET 0x0008 /* Debug control register */
#define SAM_I2C_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */
#define SAM_I2C_INTENSET_OFFSET 0x000d /* Interrupt enable set register */
#define SAM_I2C_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */
#define SAM_I2C_STATUS_OFFSET 0x0010 /* Status register */
#define SAM_I2C_ADDR_OFFSET 0x0014 /* Address register */
#define SAM_I2C_DATA_OFFSET 0x0018 /* Data register */
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# define SAM_I2C_BAUD_OFFSET 0x000a /* Baud register */
# define SAM_I2C_DBGCTRL_OFFSET 0x0008 /* Debug control register */
# define SAM_I2C_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */
# define SAM_I2C_INTENSET_OFFSET 0x000d /* Interrupt enable set register */
# define SAM_I2C_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */
# define SAM_I2C_STATUS_OFFSET 0x0010 /* Status register */
# define SAM_I2C_ADDR_OFFSET 0x0014 /* Address register */
# define SAM_I2C_DATA_OFFSET 0x0018 /* Data register */
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# define SAM_I2C_BAUD_OFFSET 0x000c /* Baud register */
# define SAM_I2C_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */
# define SAM_I2C_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
# define SAM_I2C_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
# define SAM_I2C_STATUS_OFFSET 0x001a /* Status register */
# define SAM_I2C_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
# define SAM_I2C_ADDR_OFFSET 0x0024 /* Address register */
# define SAM_I2C_DATA_OFFSET 0x0028 /* Data register */
# define SAM_I2C_DBGCTRL_OFFSET 0x0030 /* Debug control register */
#endif
/* I2C register addresses *******************************************************************/
#define SAM_I2C0_CTRLA (SAM_SERCOM0_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C0_CTRLB (SAM_SERCOM0_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C0_BAUD (SAM_SERCOM0_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C0_DBGCTRL (SAM_SERCOM0_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C0_INTENCLR (SAM_SERCOM0_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C0_INTENSET (SAM_SERCOM0_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C0_INTFLAG (SAM_SERCOM0_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C0_STATUS (SAM_SERCOM0_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C0_SYNCBUSY (SAM_SERCOM0_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C0_ADDR (SAM_SERCOM0_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C0_DATA (SAM_SERCOM0_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C0_DBGCTRL (SAM_SERCOM0_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C1_CTRLA (SAM_SERCOM1_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C1_CTRLB (SAM_SERCOM1_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C1_BAUD (SAM_SERCOM1_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C1_DBGCTRL (SAM_SERCOM1_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C1_INTENCLR (SAM_SERCOM1_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C1_INTENSET (SAM_SERCOM1_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C1_INTFLAG (SAM_SERCOM1_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C1_STATUS (SAM_SERCOM1_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C1_SYNCBUSY (SAM_SERCOM1_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C1_ADDR (SAM_SERCOM1_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C1_DATA (SAM_SERCOM1_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C1_DBGCTRL (SAM_SERCOM1_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C2_CTRLA (SAM_SERCOM2_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C2_CTRLB (SAM_SERCOM2_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C2_BAUD (SAM_SERCOM2_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C2_DBGCTRL (SAM_SERCOM2_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C2_INTENCLR (SAM_SERCOM2_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C2_INTENSET (SAM_SERCOM2_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C2_INTFLAG (SAM_SERCOM2_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C2_STATUS (SAM_SERCOM2_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C2_SYNCBUSY (SAM_SERCOM2_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C2_ADDR (SAM_SERCOM2_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C2_DATA (SAM_SERCOM2_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C2_DBGCTRL (SAM_SERCOM2_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C3_CTRLA (SAM_SERCOM3_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C3_CTRLB (SAM_SERCOM3_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C3_BAUD (SAM_SERCOM3_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C3_DBGCTRL (SAM_SERCOM3_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C3_INTENCLR (SAM_SERCOM3_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C3_INTENSET (SAM_SERCOM3_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C3_INTFLAG (SAM_SERCOM3_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C3_STATUS (SAM_SERCOM3_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C3_SYNCBUSY (SAM_SERCOM3_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C3_ADDR (SAM_SERCOM3_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C3_DATA (SAM_SERCOM3_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C3_DBGCTRL (SAM_SERCOM3_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C4_CTRLA (SAM_SERCOM4_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C4_CTRLB (SAM_SERCOM4_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C4_BAUD (SAM_SERCOM4_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C4_DBGCTRL (SAM_SERCOM4_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C4_INTENCLR (SAM_SERCOM4_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C4_INTENSET (SAM_SERCOM4_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C4_INTFLAG (SAM_SERCOM4_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C4_STATUS (SAM_SERCOM4_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C4_SYNCBUSY (SAM_SERCOM4_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C4_ADDR (SAM_SERCOM4_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C4_DATA (SAM_SERCOM4_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C4_DBGCTRL (SAM_SERCOM4_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C5_CTRLA (SAM_SERCOM5_BASE+SAM_I2C_CTRLA_OFFSET)
#define SAM_I2C5_CTRLB (SAM_SERCOM5_BASE+SAM_I2C_CTRLB_OFFSET)
#define SAM_I2C5_BAUD (SAM_SERCOM5_BASE+SAM_I2C_BAUD_OFFSET)
#define SAM_I2C5_DBGCTRL (SAM_SERCOM5_BASE+SAM_I2C_DBGCTRL_OFFSET)
#define SAM_I2C5_INTENCLR (SAM_SERCOM5_BASE+SAM_I2C_INTENCLR_OFFSET)
#define SAM_I2C5_INTENSET (SAM_SERCOM5_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C5_INTFLAG (SAM_SERCOM5_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C5_STATUS (SAM_SERCOM5_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C5_SYNCBUSY (SAM_SERCOM5_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C5_ADDR (SAM_SERCOM5_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C5_DATA (SAM_SERCOM5_BASE+SAM_I2C_DATA_OFFSET)
#define SAM_I2C5_DBGCTRL (SAM_SERCOM5_BASE+SAM_I2C_DBGCTRL_OFFSET)
/* I2C register bit definitions *************************************************************/
@ -154,6 +197,18 @@
# define I2C_CTRLA_SDAHOLD_75NS (1 << I2C_CTRLA_SDAHOLD_SHIFT) /* 50-100ns hold time */
# define I2C_CTRLA_SDAHOLD_450NS (2 << I2C_CTRLA_SDAHOLD_SHIFT) /* 300-600ns hold time */
# define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_CTRLA_MEXTTOEN (1 << 22) /* Bit 22: Master SCL low extend time-out */
# define I2C_CTRLA_SEXTTOEN (1 << 23) /* Bit 23: Slave SCL low extend time-out */
# define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Transfer speed */
# define I2C_CTRLA_SPEED_MASK (3 << I2C_CTRLA_SPEED_SHIFT)
# define I2C_CTRLA_SPEED_STANDARD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard-mode (<=100 kHz) and Fast-mode (<=400 kHz) */
# define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode Plus (<=1 MHz) */
# define I2C_CTRLA_SPEED_HIGHSPEED (2 << I2C_CTRLA_SPEED_SHIFT) /* High-speed mode (<=3.4 MHz) */
# define I2C_CTRLA_SCLSM (1 << 27) /* Bit 27: SCL clock stretch mode */
#endif
#define I2C_CTRLA_INACTOUT_SHIFT (28) /* Bits 28-29: Inactive Time-Out */
#define I2C_CTRLA_INACTOUT_MASK (7 << I2C_CTRLA_INACTOUT_SHIFT)
# define I2C_CTRLA_INACTOUT_DIS (0 << I2C_CTRLA_INACTOUT_SHIFT) /* Disabled */
@ -176,19 +231,24 @@
# define I2C_CTRLB_ACK (0) /* Send ACK */
# define I2C_CTRLB_NACK I2C_CTRLB_ACKACT /* Send NACK */
/* Debug control register */
#define I2C_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */
/* Baud register (16-bit baud value) */
#define I2C_BAUD_SHIFT (0) /* Bits 0-7: Master Baud Rate */
#define I2C_BAUD_SHIFT (0) /* Bits 0-7: Master baud rate */
#define I2C_BAUD_MASK (0xff << I2C_BAUD_SHIFT)
# define I2C_BAUD(n) ((uint16)(n) << I2C_BAUD_SHIFT)
#define I2C_BAUDLOW_SHIFT (8) /* Bits 8-15: Master Baud Rate Low */
#define I2C_BAUDLOW_SHIFT (8) /* Bits 8-15: Master baud rate low */
#define I2C_BAUDLOW_MASK (0xff << I2C_BAUDLOW_SHIFT)
# define I2C_BAUDLOW(n) (uint16)(n) << I2C_BAUDLOW_SHIFT)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_HSBAUD_SHIFT (16) /* Bits 16-23: High speed master baud rate */
# define I2C_HSBAUD_MASK (0xff << I2C_HSBAUD_SHIFT)
# define I2C_HSBAUD(n) ((uint16)(n) << I2C_HSBAUD_SHIFT)
# define I2C_HSBAUDLOW_SHIFT (24) /* Bits 24-31: High speed master baud rate low */
# define I2C_HSBAUDLOW_MASK (0xff << I2C_HSBAUDLOW_SHIFT)
# define I2C_HSBAUDLOW(n) (uint16)(n) << I2C_HSBAUDLOW_SHIFT)
#endif
/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and
* status clear registers.
*/
@ -196,7 +256,12 @@
#define I2C_INT_MB (1 << 0) /* Bit 0: Master on bus interrupt */
#define I2C_INT_SB (1 << 1) /* Bit 1: Slave on bus interrupt */
#define I2C_INT_ALL (0x03)
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# define I2C_INT_ALL (0x03)
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# define I2C_INT_ERROR (1 << 7) /* Bit 7: Error interrupt */
# define I2C_INT_ALL (0x03)
#endif
/* Status register */
@ -211,15 +276,54 @@
# define I2C_STATUS_BUSSTATE_BUSY (3 << I2C_STATUS_BUSSTATE_SHIFT) /* Other master owns */
#define I2C_STATUS_LOWTOUT (1 << 6) /* Bit 6: SCL Low Time-Out */
#define I2C_STATUS_CLKHOLD (1 << 7) /* Bit 7: Clock Hold */
#define I2C_STATUS_SYNCBUSY (1 << 15) /* Bit 15: Synchronization busy */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_STATUS_MEXTTOUT (1 << 8) /* Bit 8: Master SCL low extend time-out */
# define I2C_STATUS_SEXTTOUT (1 << 9) /* Bit 9: Slave SCL low extend time-out */
# define I2C_STATUS_LENERR (1 << 10) /* Bit 10: Transaction length error */
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define I2C_STATUS_SYNCBUSY (1 << 15) /* Bit 15: Synchronization busy */
#endif
/* Synchronization busy register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
# define I2C_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
# define I2C_SYNCBUSY_SYSOP (1 << 2) /* Bit 2: System operation synchronization busy */
# define I2C_SYNCBUSY_ALL 0x0007
#endif
/* Address register */
#define I2C_ADDR_MASK (0xff) /* Bits 0-7: Address */
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define I2C_ADDR_SHIFT (0) /* Bits 0-7: Address */
# define I2C_ADDR_MASK (0xff << I2C_ADDR_SHIFT)
# define I2C_ADDR(n) ((uint16_t)(n) << I2C_ADDR_SHIFT)
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_ADDR_SHIFT (0) /* Bits 0-10: Address */
# define I2C_ADDR_MASK (0x7ff << I2C_ADDR_SHIFT)
# define I2C_ADDR(n) ((uint32_t)(n) << I2C_ADDR_SHIFT)
# define I2C_ADDR_LENEN (1 << 13) /* Bit 13: Transfer length enable */
# define I2C_ADDR_HS (1 << 14) /* Bit 14: High speed */
# define I2C_ADDR_TENBITEN (1 << 15) /* Bit 15: Ten Bit Addressing Enable */
# define I2C_ADDR_LEN_SHIFT (16) /* Bits 16-23: Transaction Length */
# define I2C_ADDR_LEN_MASK (0xff << I2C_ADDR_LEN_SHIFT)
# define I2C_ADDR_LEN(n) ((uint32_t)(n) << I2C_ADDR_LEN_SHIFT)
#endif
/* Data register */
#define I2C_DATA_MASK (0xff) /* Bits 0-7: Data */
#define I2C_DATA_MASK (0x00ff) /* Bits 0-7: Data */
/* Debug control register */
#define I2C_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */
/********************************************************************************************
* Public Types
@ -233,5 +337,5 @@
* Public Functions
********************************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_I2C_MASTER_H */

127
arch/arm/src/samdl/chip/samd_i2c_slave.h
View File

@ -58,12 +58,23 @@
#define SAM_I2C_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_I2C_CTRLB_OFFSET 0x0004 /* Control B register */
#define SAM_I2C_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */
#define SAM_I2C_INTENSET_OFFSET 0x000d /* Interrupt enable set register */
#define SAM_I2C_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */
#define SAM_I2C_STATUS_OFFSET 0x0010 /* Status register */
#define SAM_I2C_ADDR_OFFSET 0x0014 /* Address register */
#define SAM_I2C_DATA_OFFSET 0x0018 /* Data register */
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# define SAM_I2C_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */
# define SAM_I2C_INTENSET_OFFSET 0x000d /* Interrupt enable set register */
# define SAM_I2C_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */
# define SAM_I2C_STATUS_OFFSET 0x0010 /* Status register */
# define SAM_I2C_ADDR_OFFSET 0x0014 /* Address register */
# define SAM_I2C_DATA_OFFSET 0x0018 /* Data register */
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# define SAM_I2C_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */
# define SAM_I2C_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
# define SAM_I2C_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
# define SAM_I2C_STATUS_OFFSET 0x001a /* Status register */
# define SAM_I2C_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
# define SAM_I2C_ADDR_OFFSET 0x0024 /* Address register */
# define SAM_I2C_DATA_OFFSET 0x0028 /* Data register */
#endif
/* I2C register addresses *******************************************************************/
@ -73,6 +84,11 @@
#define SAM_I2C0_INTENSET (SAM_SERCOM0_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C0_INTFLAG (SAM_SERCOM0_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C0_STATUS (SAM_SERCOM0_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C0_SYNCBUSY (SAM_SERCOM0_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C0_ADDR (SAM_SERCOM0_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C0_DATA (SAM_SERCOM0_BASE+SAM_I2C_DATA_OFFSET)
@ -82,6 +98,11 @@
#define SAM_I2C1_INTENSET (SAM_SERCOM1_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C1_INTFLAG (SAM_SERCOM1_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C1_STATUS (SAM_SERCOM1_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C1_SYNCBUSY (SAM_SERCOM1_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C1_ADDR (SAM_SERCOM1_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C1_DATA (SAM_SERCOM1_BASE+SAM_I2C_DATA_OFFSET)
@ -91,6 +112,11 @@
#define SAM_I2C2_INTENSET (SAM_SERCOM2_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C2_INTFLAG (SAM_SERCOM2_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C2_STATUS (SAM_SERCOM2_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C2_SYNCBUSY (SAM_SERCOM2_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C2_ADDR (SAM_SERCOM2_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C2_DATA (SAM_SERCOM2_BASE+SAM_I2C_DATA_OFFSET)
@ -100,6 +126,11 @@
#define SAM_I2C3_INTENSET (SAM_SERCOM3_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C3_INTFLAG (SAM_SERCOM3_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C3_STATUS (SAM_SERCOM3_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C3_SYNCBUSY (SAM_SERCOM3_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C3_ADDR (SAM_SERCOM3_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C3_DATA (SAM_SERCOM3_BASE+SAM_I2C_DATA_OFFSET)
@ -109,6 +140,11 @@
#define SAM_I2C4_INTENSET (SAM_SERCOM4_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C4_INTFLAG (SAM_SERCOM4_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C4_STATUS (SAM_SERCOM4_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C4_SYNCBUSY (SAM_SERCOM4_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C4_ADDR (SAM_SERCOM4_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C4_DATA (SAM_SERCOM4_BASE+SAM_I2C_DATA_OFFSET)
@ -118,6 +154,11 @@
#define SAM_I2C5_INTENSET (SAM_SERCOM5_BASE+SAM_I2C_INTENSET_OFFSET)
#define SAM_I2C5_INTFLAG (SAM_SERCOM5_BASE+SAM_I2C_INTFLAG_OFFSET)
#define SAM_I2C5_STATUS (SAM_SERCOM5_BASE+SAM_I2C_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_I2C5_SYNCBUSY (SAM_SERCOM5_BASE+SAM_I2C_SYNCBUSY_OFFSET)
#endif
#define SAM_I2C5_ADDR (SAM_SERCOM5_BASE+SAM_I2C_ADDR_OFFSET)
#define SAM_I2C5_DATA (SAM_SERCOM5_BASE+SAM_I2C_DATA_OFFSET)
@ -140,11 +181,28 @@
# define I2C_CTRLA_SDAHOLD_75NS (1 << I2C_CTRLA_SDAHOLD_SHIFT) /* 50-100ns hold time */
# define I2C_CTRLA_SDAHOLD_450NS (2 << I2C_CTRLA_SDAHOLD_SHIFT) /* 300-600ns hold time */
# define I2C_CTRLA_SDAHOLD_600NS (3 << I2C_CTRLA_SDAHOLD_SHIFT) /* 400-800ns hold time */
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL Low Time-Out */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_CTRLA_SEXTTOEN (1 << 23) /* Bit 23: Slave SCL low extend time-out */
# define I2C_CTRLA_SPEED_SHIFT (24) /* Bits 24-25: Transfer speed */
# define I2C_CTRLA_SPEED_MASK (3 << I2C_CTRLA_SPEED_SHIFT)
# define I2C_CTRLA_SPEED_STANDARD (0 << I2C_CTRLA_SPEED_SHIFT) /* Standard-mode (<=100 kHz) and Fast-mode (<=400 kHz) */
# define I2C_CTRLA_SPEED_FAST (1 << I2C_CTRLA_SPEED_SHIFT) /* Fast-mode Plus (<=1 MHz) */
# define I2C_CTRLA_SPEED_HIGHSPEED (2 << I2C_CTRLA_SPEED_SHIFT) /* High-speed mode (<=3.4 MHz) */
# define I2C_CTRLA_SCLSM (1 << 27) /* Bit 27: SCL clock stretch mode */
#endif
#define I2C_CTRLA_LOWTOUT (1 << 30) /* Bit 30: SCL low time-out */
/* Control B register */
#define I2C_CTRLB_SMEN (1 << 8) /* Bit 8: Smart Mode Enable */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_CTRLB_GCMD (1 << 9) /* Bit 8: PMBus group command */
# define I2C_CTRLB_AACKEN (1 << 10) /* Bit 10: Automatic acknowledge enable */
#endif
#define I2C_CRLB_AMODE_SHIFT (14) /* Bits 14-15: Address Mode */
#define I2C_CRLB_AMODE_MASK (3 << I2C_CRLB_AMODE_SHIFT)
# define I2C_CRLB_AMODE_MASK (0 << I2C_CRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */
@ -167,7 +225,12 @@
#define I2C_INT_AMATCH (1 << 1) /* Bit 1: Address match interrupt */
#define I2C_INT_DRDY (1 << 2) /* Bit 2: Data ready interrupt */
#define I2C_INT_ALL (0x07)
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# define I2C_INT_ALL (0x07)
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# define I2C_INT_ERROR (1 << 7) /* Bit 7: Error interrupt */
# define I2C_INT_ALL (0x87)
#endif
/* Status register */
@ -178,21 +241,51 @@
#define I2C_STATUS_SR (1 << 4) /* Bit 4: Repeated Start */
#define I2C_STATUS_LOWTOUT (1 << 6) /* Bit 6: SCL Low Time-Out */
#define I2C_STATUS_CLKHOLD (1 << 7) /* Bit 7: Clock Hold */
#define I2C_STATUS_SYNCBUSY (1 << 15) /* Bit 15: Synchronization busy */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_STATUS_SEXTTOUT (1 << 9) /* Bit 9: Slave SCL low extend time-out */
# define I2C_STATUS_HS (1 << 10) /* Bit 10: High speed */
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define I2C_STATUS_SYNCBUSY (1 << 15) /* Bit 15: Synchronization busy */
#endif
/* Synchronization busy register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define I2C_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
# define I2C_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
# define I2C_SYNCBUSY_ALL 0x0003
#endif
/* Address register */
#define SPI_ADDR_GENCEN (1 << 0) /* Bit 0: General Call Address Enable */
#define SPI_ADDR_SHIFT (1) /* Bits 1-7: Address */
#define SPI_ADDR_MASK (0x7f << SPI_ADDR_SHIFT)
# define SPI_ADDR(n) ((uint32_t)(n) << SPI_ADDR_SHIFT)
#define SPI_ADDRMASK_SHIFT (17) /* Bits 17-23: Address Mask */
#define SPI_ADDRMASK_MASK (0x7f << SPI_ADDRMASK_SHIFT)
# define SPI_ADDRMASK(n) ((uint32_t)(n) << SPI_ADDRMASK_SHIFT)
#define SPI_ADDR_GENCEN (1 << 0) /* Bit 0: General call address enable */
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define SPI_ADDR_SHIFT (1) /* Bits 1-7: Address */
# define SPI_ADDR_MASK (0x7f << SPI_ADDR_SHIFT)
# define SPI_ADDR(n) ((uint32_t)(n) << SPI_ADDR_SHIFT)
# define SPI_ADDRMASK_SHIFT (17) /* Bits 17-23: Address Mask */
# define SPI_ADDRMASK_MASK (0x7f << SPI_ADDRMASK_SHIFT)
# define SPI_ADDRMASK(n) ((uint32_t)(n) << SPI_ADDRMASK_SHIFT)
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SPI_ADDR_SHIFT (1) /* Bits 1-10: Address */
# define SPI_ADDR_MASK (0x3ff << SPI_ADDR_SHIFT)
# define SPI_ADDR(n) ((uint32_t)(n) << SPI_ADDR_SHIFT)
# define SPI_ADDR_TENBITEN (1 << 15) /* Bit 15: Ten bit addressing enable */
# define SPI_ADDRMASK_SHIFT (17) /* Bits 17-26: Address Mask */
# define SPI_ADDRMASK_MASK (0x3ff << SPI_ADDRMASK_SHIFT)
# define SPI_ADDRMASK(n) ((uint32_t)(n) << SPI_ADDRMASK_SHIFT)
#endif
/* Data register */
#define I2C_DATA_MASK (0xff) /* Bits 0-7: Data */
#define I2C_DATA_MASK (0xooff) /* Bits 0-7: Data */
/********************************************************************************************
* Public Types

115
arch/arm/src/samdl/chip/samd_spi.h
View File

@ -49,7 +49,7 @@
#include "chip.h"
#include "chip/samd_sercom.h"
#ifdef CONFIG_ARCH_FAMILY_SAMD20
#if defined(CONFIG_ARCH_FAMILY_SAMD20) || defined(CONFIG_ARCH_FAMILY_SAMD21)
/********************************************************************************************
* Pre-processor Definitions
@ -58,69 +58,106 @@
#define SAM_SPI_CTRLA_OFFSET 0x0000 /* Control A register */
#define SAM_SPI_CTRLB_OFFSET 0x0004 /* Control B register */
#define SAM_SPI_DBGCTRL_OFFSET 0x0008 /* Debug control register */
#define SAM_SPI_BAUD_OFFSET 0x000a /* Baud register */
#define SAM_SPI_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */
#define SAM_SPI_INTENSET_OFFSET 0x000d /* Interrupt enable set register */
#define SAM_SPI_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */
#define SAM_SPI_STATUS_OFFSET 0x0010 /* Status register */
#define SAM_SPI_ADDR_OFFSET 0x0014 /* Address register */
#define SAM_SPI_DATA_OFFSET 0x0018 /* Data register */
#if defined(CONFIG_ARCH_FAMILY_SAMD20)
# define SAM_SPI_DBGCTRL_OFFSET 0x0008 /* Debug control register */
# define SAM_SPI_BAUD_OFFSET 0x000a /* Baud register */
# define SAM_SPI_INTENCLR_OFFSET 0x000c /* Interrupt enable clear register */
# define SAM_SPI_INTENSET_OFFSET 0x000d /* Interrupt enable set register */
# define SAM_SPI_INTFLAG_OFFSET 0x000e /* Interrupt flag and status clear register */
# define SAM_SPI_STATUS_OFFSET 0x0010 /* Status register */
# define SAM_SPI_ADDR_OFFSET 0x0014 /* Address register */
# define SAM_SPI_DATA_OFFSET 0x0018 /* Data register */
#elif defined(CONFIG_ARCH_FAMILY_SAMD21)
# define SAM_SPI_BAUD_OFFSET 0x000c /* Baud register */
# define SAM_SPI_INTENCLR_OFFSET 0x0014 /* Interrupt enable clear register */
# define SAM_SPI_INTENSET_OFFSET 0x0016 /* Interrupt enable set register */
# define SAM_SPI_INTFLAG_OFFSET 0x0018 /* Interrupt flag and status clear register */
# define SAM_SPI_STATUS_OFFSET 0x001a /* Status register */
# define SAM_SPI_SYNCBUSY_OFFSET 0x001c /* Synchronization busy register */
# define SAM_SPI_ADDR_OFFSET 0x0024 /* Address register */
# define SAM_SPI_DATA_OFFSET 0x0028 /* Data register */
# define SAM_SPI_DBGCTRL_OFFSET 0x0030 /* Debug control register */
#endif
/* SPI register addresses *******************************************************************/
#define SAM_SPI0_CTRLA (SAM_SERCOM0_BASE+SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI0_CTRLB (SAM_SERCOM0_BASE+SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI0_DBGCTRL (SAM_SERCOM0_BASE+SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI0_BAUD (SAM_SERCOM0_BASE+SAM_SPI_BAUD_OFFSET)
#define SAM_SPI0_INTENCLR (SAM_SERCOM0_BASE+SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI0_INTENSET (SAM_SERCOM0_BASE+SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI0_INTFLAG (SAM_SERCOM0_BASE+SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI0_STATUS (SAM_SERCOM0_BASE+SAM_SPI_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SPI0_SYNCBUSY (SAM_SERCOM0_BASE+SAM_SPI_SYNCBUSY_OFFSET)
#endif
#define SAM_SPI0_ADDR (SAM_SERCOM0_BASE+SAM_SPI_ADDR_OFFSET)
#define SAM_SPI0_DATA (SAM_SERCOM0_BASE+SAM_SPI_DATA_OFFSET)
#define SAM_SPI0_DBGCTRL (SAM_SERCOM0_BASE+SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI1_CTRLA (SAM_SERCOM1_BASE+SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI1_CTRLB (SAM_SERCOM1_BASE+SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI1_DBGCTRL (SAM_SERCOM1_BASE+SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI1_BAUD (SAM_SERCOM1_BASE+SAM_SPI_BAUD_OFFSET)
#define SAM_SPI1_INTENCLR (SAM_SERCOM1_BASE+SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI1_INTENSET (SAM_SERCOM1_BASE+SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI1_INTFLAG (SAM_SERCOM1_BASE+SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI1_STATUS (SAM_SERCOM1_BASE+SAM_SPI_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SPI1_SYNCBUSY (SAM_SERCOM1_BASE+SAM_SPI_SYNCBUSY_OFFSET)
#endif
#define SAM_SPI1_ADDR (SAM_SERCOM1_BASE+SAM_SPI_ADDR_OFFSET)
#define SAM_SPI1_DATA (SAM_SERCOM1_BASE+SAM_SPI_DATA_OFFSET)
#define SAM_SPI1_DBGCTRL (SAM_SERCOM1_BASE+SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI2_CTRLA (SAM_SERCOM2_BASE+SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI2_CTRLB (SAM_SERCOM2_BASE+SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI2_DBGCTRL (SAM_SERCOM2_BASE+SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI2_BAUD (SAM_SERCOM2_BASE+SAM_SPI_BAUD_OFFSET)
#define SAM_SPI2_INTENCLR (SAM_SERCOM2_BASE+SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI2_INTENSET (SAM_SERCOM2_BASE+SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI2_INTFLAG (SAM_SERCOM2_BASE+SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI2_STATUS (SAM_SERCOM2_BASE+SAM_SPI_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SPI2_SYNCBUSY (SAM_SERCOM2_BASE+SAM_SPI_SYNCBUSY_OFFSET)
#endif
#define SAM_SPI2_ADDR (SAM_SERCOM2_BASE+SAM_SPI_ADDR_OFFSET)
#define SAM_SPI2_DATA (SAM_SERCOM2_BASE+SAM_SPI_DATA_OFFSET)
#define SAM_SPI2_DBGCTRL (SAM_SERCOM2_BASE+SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI3_CTRLA (SAM_SERCOM3_BASE+SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI3_CTRLB (SAM_SERCOM3_BASE+SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI3_DBGCTRL (SAM_SERCOM3_BASE+SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI3_BAUD (SAM_SERCOM3_BASE+SAM_SPI_BAUD_OFFSET)
#define SAM_SPI3_INTENCLR (SAM_SERCOM3_BASE+SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI3_INTENSET (SAM_SERCOM3_BASE+SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI3_INTFLAG (SAM_SERCOM3_BASE+SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI3_STATUS (SAM_SERCOM3_BASE+SAM_SPI_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SPI3_SYNCBUSY (SAM_SERCOM3_BASE+SAM_SPI_SYNCBUSY_OFFSET)
#endif
#define SAM_SPI3_ADDR (SAM_SERCOM3_BASE+SAM_SPI_ADDR_OFFSET)
#define SAM_SPI3_DATA (SAM_SERCOM3_BASE+SAM_SPI_DATA_OFFSET)
#define SAM_SPI3_DBGCTRL (SAM_SERCOM3_BASE+SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI4_CTRLA (SAM_SERCOM4_BASE+SAM_SPI_CTRLA_OFFSET)
#define SAM_SPI4_CTRLB (SAM_SERCOM4_BASE+SAM_SPI_CTRLB_OFFSET)
#define SAM_SPI4_DBGCTRL (SAM_SERCOM4_BASE+SAM_SPI_DBGCTRL_OFFSET)
#define SAM_SPI4_BAUD (SAM_SERCOM4_BASE+SAM_SPI_BAUD_OFFSET)
#define SAM_SPI4_INTENCLR (SAM_SERCOM4_BASE+SAM_SPI_INTENCLR_OFFSET)
#define SAM_SPI4_INTENSET (SAM_SERCOM4_BASE+SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI4_INTFLAG (SAM_SERCOM4_BASE+SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI4_STATUS (SAM_SERCOM4_BASE+SAM_SPI_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SPI4_SYNCBUSY (SAM_SERCOM4_BASE+SAM_SPI_SYNCBUSY_OFFSET)
#endif
#define SAM_SPI4_ADDR (SAM_SERCOM4_BASE+SAM_SPI_ADDR_OFFSET)
#define SAM_SPI4_DATA (SAM_SERCOM4_BASE+SAM_SPI_DATA_OFFSET)
@ -132,8 +169,14 @@
#define SAM_SPI5_INTENSET (SAM_SERCOM5_BASE+SAM_SPI_INTENSET_OFFSET)
#define SAM_SPI5_INTFLAG (SAM_SERCOM5_BASE+SAM_SPI_INTFLAG_OFFSET)
#define SAM_SPI5_STATUS (SAM_SERCOM5_BASE+SAM_SPI_STATUS_OFFSET)
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SAM_SPI5_SYNCBUSY (SAM_SERCOM5_BASE+SAM_SPI_SYNCBUSY_OFFSET)
#endif
#define SAM_SPI5_ADDR (SAM_SERCOM5_BASE+SAM_SPI_ADDR_OFFSET)
#define SAM_SPI5_DATA (SAM_SERCOM5_BASE+SAM_SPI_DATA_OFFSET)
#define SAM_SPI4_DBGCTRL (SAM_SERCOM4_BASE+SAM_SPI_DBGCTRL_OFFSET)
/* SPI register bit definitions *************************************************************/
@ -176,6 +219,12 @@
# define SPI_CTRLB_CHSIZE_8BITS (0 << SPI_CTRLB_CHSIZE_SHIFT) /* 8 bits */
# define SPI_CTRLB_CHSIZE_9BITS (1 << SPI_CTRLB_CHSIZE_SHIFT) /* 9 bits */
#define SPI_CTRLB_PLOADEN (1 << 6) /* Bit 6: Slave Data Preload Enable */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SPI_CTRLB_SSDE (1 << 9) /* Bit 9: Slave Select Low Detect Enable */
# define SPI_CTRLB_MSSEN (1 << 13) /* Bit 13: Master Slave Select Enable */
#endif
#define SPI_CTRLB_AMODE_SHIFT (14) /* Bits 14-15: Address Mode */
#define SPI_CTRLB_AMODE_MASK (3 << SPI_CTRLB_AMODE_SHIFT)
# define SPI_CTRLB_AMODE_ADDRMASK (0 << SPI_CTRLB_AMODE_SHIFT) /* ADDRMASK used to mask ADDR */
@ -183,10 +232,6 @@
# define SPI_CTRLB_AMODE_RANGE (2 << SPI_CTRLB_AMODE_SHIFT) /* Slave range of addresses: ADDRMASK-ADDR */
#define SPI_CTRLB_RXEN (1 << 17) /* Bit 17: Receiver enable */
/* Debug control register */
#define SPI_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */
/* Baud register (8-bit baud value) */
/* Interrupt enable clear, interrupt enable set, interrupt enable set, interrupt flag and
@ -196,16 +241,38 @@
#define SPI_INT_DRE (1 << 0) /* Bit 0: Data register empty interrupt */
#define SPI_INT_TXC (1 << 1) /* Bit 1: Transmit complete interrupt */
#define SPI_INT_RXC (1 << 2) /* Bit 2: Receive complete interrupt */
#
#define SPI_INT_ALL (0x07)
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define SPI_INT_ALL (0x07)
#endif
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SPI_INT_ SSL (1 << 3) /* Bit 3: Slave select low interrupt */
# define SPI_INT_ ERROR (1 << 7) /* Bit 7: Error interrupt */
# define SPI_INT_ALL (0x8f)
#endif
/* Status register */
#define SPI_STATUS_BUFOVF (1 << 2) /* Bit 2: Buffer overflow */
#define SPI_STATUS_SYNCBUSY (1 << 15) /* Bit 15: Synchronization busy */
#ifdef CONFIG_ARCH_FAMILY_SAMD20
# define SPI_STATUS_SYNCBUSY (1 << 15) /* Bit 15: Synchronization busy */
#endif
#define SPI_STATUS_CLRALL SPI_STATUS_BUFOVF
/* Synchronization busy register */
#ifdef CONFIG_ARCH_FAMILY_SAMD21
# define SPI_SYNCBUSY_SWRST (1 << 0) /* Bit 0: Software reset synchronization busy */
# define SPI_SYNCBUSY_ENABLE (1 << 1) /* Bit 1: SERCOM enable synchronization busy */
# define SPI_SYNCBUSY_CTRLB (1 << 2) /* Bit 2: CTRLB synchronization busy */
# define SPI_SYNCBUSY_ALL 0x0007
#endif
/* Address register */
#define SPI_ADDR_SHIFT (0) /* Bits 0-7: Address */
@ -219,6 +286,10 @@
#define SPI_DATA_MASK (0x1ff) /* Bits 0-8: Data */
/* Debug control register */
#define SPI_DBGCTRL_DBGSTOP (1 << 0) /* Bit 0: Debug stop mode */
/********************************************************************************************
* Public Types
********************************************************************************************/
@ -231,5 +302,5 @@
* Public Functions
********************************************************************************************/
#endif /* CONFIG_ARCH_FAMILY_SAMD20 */
#endif /* CONFIG_ARCH_FAMILY_SAMD20 || CONFIG_ARCH_FAMILY_SAMD21 */
#endif /* __ARCH_ARM_SRC_SAMDL_CHIP_SAMD_SPI_H */