drivers: prepare 16550 UART driver to support PCI
prepare 16550 UART driver to support PCI: - [breaking change] change argument of uart_ioctl() from `struct file *filep` to `FAR struct u16550_s *priv` Also fix moxart_16550.c build related to this change - [breaking change] change argument of uart_getreg() and uart_putreg from `uart_addrwidth_t base` to `FAR struct u16550_s *priv` Also fix arch/x86/src/qemu/qemu_serial.c and arch/x86_64/src/intel64/intel64_serial.c related to this change - [breaking change] change argument of uart_dmachan() from `uart_addrwidth_t base` to `FAR struct u16550_s *priv` - move `struct u16550_s` to public header - generalize UART_XXX_OFFSET so we can use it with any register increment - make u16550_bind(), u16550_interrupt(), u16550_interrupt() public - remove arch/or1k/src/common/or1k_uart.c and use common 16550 MIMO interfacve - change irq type in `struct u16550_s` from uint8_t to int to match MSI API Signed-off-by: p-szafonimateusz <p-szafonimateusz@xiaomi.com>
This commit is contained in:
p-szafonimateusz
Xiang Xiao
parent
c7e8fd43a4
commit
ceb2921d79
@ -69,15 +69,12 @@ void uart_decodeirq(int irq, void *context)
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}
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#ifdef CONFIG_SERIAL_UART_ARCH_IOCTL
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int uart_ioctl(struct file *filep, int cmd, unsigned long arg)
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int uart_ioctl(FAR struct u16550_s *priv, int cmd, unsigned long arg)
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{
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struct inode *inode = filep->f_inode;
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struct uart_dev_s *dev = inode->i_private;
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struct u16550_s *priv = (struct u16550_s *)dev->priv;
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int ret = -ENOTTY;
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uint32_t vmode;
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unsigned int opmode;
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int bitm_off;
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int ret = -ENOTTY;
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uint32_t vmode;
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unsigned int opmode;
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int bitm_off;
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/* TODO: calculate bit offset from UART_BASE address.
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* E.g.:
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@ -1,45 +0,0 @@
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/****************************************************************************
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* arch/or1k/src/common/or1k_uart.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/arch.h>
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#include <nuttx/serial/uart_16550.h>
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#include "or1k_internal.h"
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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uart_datawidth_t uart_getreg(uart_addrwidth_t base, unsigned int offset)
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{
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return *(uint8_t *)(base + offset);
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}
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void uart_putreg(uart_addrwidth_t base, unsigned int offset,
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uart_datawidth_t value)
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{
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*(uint8_t *)(base + offset) = value;
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}
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@ -40,7 +40,6 @@ CMN_CSRCS = or1k_initialize.c \
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or1k_idle.c \
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or1k_irq.c \
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or1k_nputs.c \
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or1k_uart.c \
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or1k_timer.c \
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or1k_doirq.c \
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or1k_cpuinfo.c \
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@ -52,15 +52,15 @@
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*
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****************************************************************************/
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uart_datawidth_t uart_getreg(uart_addrwidth_t base, unsigned int offset)
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uart_datawidth_t uart_getreg(struct u16550_s *priv, unsigned int offset)
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{
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return inb(base + offset);
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return inb(priv->uartbase + offset);
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}
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void uart_putreg(uart_addrwidth_t base,
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void uart_putreg(struct u16550_s *priv,
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unsigned int offset, uart_datawidth_t value)
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{
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outb(value, base + offset);
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outb(value, priv->uartbase + offset);
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}
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#else /* USE_SERIALDRIVER */
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@ -52,12 +52,12 @@
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*
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****************************************************************************/
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uart_datawidth_t uart_getreg(uart_addrwidth_t base, unsigned int offset)
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uart_datawidth_t uart_getreg(struct u16550_s *priv, unsigned int offset)
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{
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return inb(base + offset);
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return inb(priv->uartbase + offset);
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}
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void uart_putreg(uart_addrwidth_t base, unsigned int offset,
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void uart_putreg(struct u16550_s *priv, unsigned int offset,
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uart_datawidth_t value)
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{
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/* Intel x86 platform require OUT2 of MCR being set
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@ -69,7 +69,7 @@ void uart_putreg(uart_addrwidth_t base, unsigned int offset,
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value |= UART_MCR_OUT2;
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}
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outb(value, base + offset);
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outb(value, priv->uartbase + offset);
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}
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#else /* USE_SERIALDRIVER */
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@ -84,6 +84,7 @@ CONFIG_PTHREAD_STACK_DEFAULT=1024
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CONFIG_RAM_SIZE=4194304
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CONFIG_RAM_START=0x0000
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CONFIG_RAW_BINARY=y
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CONFIG_SERIAL_UART_ARCH_MMIO=y
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CONFIG_START_DAY=7
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CONFIG_START_MONTH=12
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CONFIG_START_YEAR=2012
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@ -39,75 +39,55 @@
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#include <nuttx/arch.h>
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#include <nuttx/clk/clk.h>
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#include <nuttx/dma/dma.h>
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#include <nuttx/serial/serial.h>
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#include <nuttx/fs/ioctl.h>
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#include <nuttx/serial/uart_16550.h>
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#include <arch/board/board.h>
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#if defined(CONFIG_16550_UART0_DMA) || defined(CONFIG_16550_UART1_DMA) \
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|| defined(CONFIG_16550_UART2_DMA) || defined(CONFIG_16550_UART3_DMA)
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# define HAVE_16550_UART_DMA 1
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#endif
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#ifdef CONFIG_16550_UART
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Are any UARTs enabled? */
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#undef HAVE_16550_UART
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#if defined(CONFIG_16550_UART0) || defined(CONFIG_16550_UART1) \
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|| defined(CONFIG_16550_UART2) || defined(CONFIG_16550_UART3)
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# define HAVE_16550_UART 1
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#endif
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/* Timeout for UART Busy Wait, in milliseconds */
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#define UART_TIMEOUT_MS 100
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* Default getreg/putreg operations */
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struct u16550_s
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{
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uart_addrwidth_t uartbase; /* Base address of UART registers */
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#ifdef HAVE_16550_UART_DMA
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int32_t dmatx;
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FAR struct dma_chan_s *chantx;
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int32_t dmarx;
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FAR struct dma_chan_s *chanrx;
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FAR char *dmarxbuf;
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size_t dmarxsize;
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volatile size_t dmarxhead;
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volatile size_t dmarxtail;
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int32_t dmarxtimeout;
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#ifdef CONFIG_SERIAL_UART_ARCH_MMIO
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# define u16550_getreg u16550_mmio_getreg
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# define u16550_putreg u16550_mmio_putreg
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#else
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# define u16550_getreg uart_getreg
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# define u16550_putreg uart_putreg
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#endif
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#if !defined(CONFIG_16550_SUPRESS_CONFIG) || defined(HAVE_16550_UART_DMA)
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uint32_t baud; /* Configured baud */
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uint32_t uartclk; /* UART clock frequency */
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#endif
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#ifdef CONFIG_CLK
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FAR const char *clk_name; /* UART clock name */
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FAR struct clk_s *mclk; /* UART clock descriptor */
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#endif
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uart_datawidth_t ier; /* Saved IER value */
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uint8_t irq; /* IRQ associated with this UART */
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#ifndef CONFIG_16550_SUPRESS_CONFIG
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uint8_t parity; /* 0=none, 1=odd, 2=even */
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uint8_t bits; /* Number of bits (7 or 8) */
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bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
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#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
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bool flow; /* flow control (RTS/CTS) enabled */
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#endif
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#endif
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uart_datawidth_t rxtrigger; /* RX trigger level */
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};
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/****************************************************************************
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* Private Function Prototypes
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****************************************************************************/
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#ifdef CONFIG_SERIAL_UART_ARCH_MMIO
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static uart_datawidth_t u16550_mmio_getreg(FAR struct u16550_s *priv,
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unsigned int offset);
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static void u16550_mmio_putreg(FAR struct u16550_s *priv,
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unsigned int offset,
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uart_datawidth_t value);
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#endif
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static int u16550_setup(FAR struct uart_dev_s *dev);
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static void u16550_shutdown(FAR struct uart_dev_s *dev);
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static int u16550_attach(FAR struct uart_dev_s *dev);
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static void u16550_detach(FAR struct uart_dev_s *dev);
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static int u16550_interrupt(int irq, FAR void *context, FAR void *arg);
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static int u16550_ioctl(FAR struct file *filep, int cmd, unsigned long arg);
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static int u16550_receive(FAR struct uart_dev_s *dev, unsigned int *status);
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static void u16550_rxint(FAR struct uart_dev_s *dev, bool enable);
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@ -133,6 +113,21 @@ static bool u16550_txempty(FAR struct uart_dev_s *dev);
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* Private Data
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****************************************************************************/
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#ifdef HAVE_16550_UART
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static const struct u16550_ops_s g_u16550_ops =
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{
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.isr = u16550_interrupt,
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.getreg = u16550_getreg,
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.putreg = u16550_putreg,
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# ifdef CONFIG_SERIAL_UART_ARCH_IOCTL
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.ioctl = uart_ioctl,
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# endif
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# ifdef HAVE_16550_UART_DMA
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.dmachan = uart_dmachan,
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# endif
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};
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#endif
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static const struct uart_ops_s g_uart_ops =
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{
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.setup = u16550_setup,
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@ -197,7 +192,9 @@ static char g_uart3dmarxbuf[CONFIG_16550_UART3_DMA_RXBUFSIZE];
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#ifdef CONFIG_16550_UART0
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static struct u16550_s g_uart0priv =
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{
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.ops = &g_u16550_ops,
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.uartbase = CONFIG_16550_UART0_BASE,
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.regincr = CONFIG_16550_REGINCR,
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#ifdef CONFIG_16550_UART0_DMA
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.dmatx = CONFIG_16550_UART0_DMA_TX,
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.dmarx = CONFIG_16550_UART0_DMA_RX,
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@ -251,7 +248,9 @@ static uart_dev_t g_uart0port =
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#ifdef CONFIG_16550_UART1
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static struct u16550_s g_uart1priv =
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{
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.ops = &g_u16550_ops,
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.uartbase = CONFIG_16550_UART1_BASE,
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.regincr = CONFIG_16550_REGINCR,
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#ifdef CONFIG_16550_UART1_DMA
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.dmatx = CONFIG_16550_UART1_DMA_TX,
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.dmarx = CONFIG_16550_UART1_DMA_RX,
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@ -305,7 +304,9 @@ static uart_dev_t g_uart1port =
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#ifdef CONFIG_16550_UART2
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static struct u16550_s g_uart2priv =
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{
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.ops = &g_u16550_ops,
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.uartbase = CONFIG_16550_UART2_BASE,
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.regincr = CONFIG_16550_REGINCR,
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#ifdef CONFIG_16550_UART2_DMA
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.dmatx = CONFIG_16550_UART2_DMA_TX,
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.dmarx = CONFIG_16550_UART2_DMA_RX,
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@ -359,7 +360,9 @@ static uart_dev_t g_uart2port =
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#ifdef CONFIG_16550_UART3
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static struct u16550_s g_uart3priv =
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{
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.ops = &g_u16550_ops,
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.uartbase = CONFIG_16550_UART3_BASE,
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.regincr = CONFIG_16550_REGINCR,
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#ifdef CONFIG_16550_UART3_DMA
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.dmatx = CONFIG_16550_UART3_DMA_TX,
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.dmarx = CONFIG_16550_UART3_DMA_RX,
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@ -607,6 +610,31 @@ static uart_dev_t g_uart3port =
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* Private Functions
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****************************************************************************/
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#ifdef CONFIG_SERIAL_UART_ARCH_MMIO
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/****************************************************************************
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* Name: u16550_mmio_getreg
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****************************************************************************/
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static uart_datawidth_t u16550_mmio_getreg(FAR struct u16550_s *priv,
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unsigned int offset)
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{
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uintptr_t addr = priv->uartbase + offset;
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return *((FAR volatile uart_datawidth_t *)addr);
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}
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/****************************************************************************
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* Name: u16550_mmio_putreg
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****************************************************************************/
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static void u16550_mmio_putreg(FAR struct u16550_s *priv,
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unsigned int offset,
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uart_datawidth_t value)
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{
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uintptr_t addr = priv->uartbase + offset;
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*((FAR volatile uart_datawidth_t *)addr) = value;
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}
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#endif
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/****************************************************************************
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* Name: u16550_serialin
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****************************************************************************/
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@ -614,11 +642,10 @@ static uart_dev_t g_uart3port =
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static inline uart_datawidth_t u16550_serialin(FAR struct u16550_s *priv,
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int offset)
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{
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#ifdef CONFIG_SERIAL_UART_ARCH_MMIO
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return *((FAR volatile uart_datawidth_t *)priv->uartbase + offset);
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#else
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return uart_getreg(priv->uartbase, offset);
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#endif
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/* Get correct offset */
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offset *= (priv->regincr * sizeof(uart_datawidth_t));
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return priv->ops->getreg(priv, offset);
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}
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/****************************************************************************
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@ -628,11 +655,10 @@ static inline uart_datawidth_t u16550_serialin(FAR struct u16550_s *priv,
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static inline void u16550_serialout(FAR struct u16550_s *priv, int offset,
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uart_datawidth_t value)
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{
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#ifdef CONFIG_SERIAL_UART_ARCH_MMIO
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*((FAR volatile uart_datawidth_t *)priv->uartbase + offset) = value;
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#else
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uart_putreg(priv->uartbase, offset, value);
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#endif
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/* Get correct offset */
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offset *= (priv->regincr * sizeof(uart_datawidth_t));
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priv->ops->putreg(priv, offset, value);
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}
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#ifdef CONFIG_16550_WAIT_LCR
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@ -759,6 +785,13 @@ static int u16550_setup(FAR struct uart_dev_s *dev)
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uint32_t mcr;
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#endif
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if (priv->uartbase == 0)
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{
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/* Device must be initialized */
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return -EPERM;
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}
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/* Clear fifos */
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u16550_serialout(priv, UART_FCR_OFFSET,
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@ -930,7 +963,7 @@ static int u16550_attach(struct uart_dev_s *dev)
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/* Attach and enable the IRQ */
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ret = irq_attach(priv->irq, u16550_interrupt, dev);
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ret = irq_attach(priv->irq, priv->ops->isr, dev);
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#ifndef CONFIG_ARCH_NOINTC
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if (ret == OK)
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{
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@ -974,7 +1007,7 @@ static void u16550_detach(FAR struct uart_dev_s *dev)
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#endif
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up_disable_irq(priv->irq);
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irq_detach(priv->irq);
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irqchain_detach(priv->irq, priv->ops->isr, dev);
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#ifdef CONFIG_CLK
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/* Clk disaable */
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@ -986,109 +1019,6 @@ static void u16550_detach(FAR struct uart_dev_s *dev)
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#endif
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}
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/****************************************************************************
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* Name: u16550_interrupt
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*
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* Description:
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* This is the UART interrupt handler. It will be invoked when an
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* interrupt is received on the 'irq'. It should call uart_xmitchars or
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* uart_recvchars to perform the appropriate data transfers. The
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* interrupt handling logic must be able to map the 'arg' to the
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* appropriate uart_dev_s structure in order to call these functions.
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*
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****************************************************************************/
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static int u16550_interrupt(int irq, FAR void *context, FAR void *arg)
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{
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FAR struct uart_dev_s *dev = (struct uart_dev_s *)arg;
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FAR struct u16550_s *priv;
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uint32_t status;
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int passes;
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DEBUGASSERT(dev != NULL && dev->priv != NULL);
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priv = (FAR struct u16550_s *)dev->priv;
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/* Loop until there are no characters to be transferred or,
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* until we have been looping for a long time.
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*/
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for (passes = 0; passes < 256; passes++)
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{
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/* Get the current UART status and check for loop
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* termination conditions
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*/
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status = u16550_serialin(priv, UART_IIR_OFFSET);
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/* The UART_IIR_INTSTATUS bit should be zero if there are pending
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* interrupts
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*/
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if ((status & UART_IIR_INTSTATUS) != 0)
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{
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/* Break out of the loop when there is no longer a
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* pending interrupt
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*/
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break;
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}
|
||||
|
||||
/* Handle the interrupt by its interrupt ID field */
|
||||
|
||||
switch (status & UART_IIR_INTID_MASK)
|
||||
{
|
||||
/* Handle incoming, receive bytes (with or without timeout) */
|
||||
|
||||
case UART_IIR_INTID_RDA:
|
||||
case UART_IIR_INTID_CTI:
|
||||
{
|
||||
uart_recvchars(dev);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Handle outgoing, transmit bytes */
|
||||
|
||||
case UART_IIR_INTID_THRE:
|
||||
{
|
||||
uart_xmitchars(dev);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Just clear modem status interrupts (UART1 only) */
|
||||
|
||||
case UART_IIR_INTID_MSI:
|
||||
{
|
||||
/* Read the modem status register (MSR) to clear */
|
||||
|
||||
status = u16550_serialin(priv, UART_MSR_OFFSET);
|
||||
sinfo("MSR: %02"PRIx32"\n", status);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Just clear any line status interrupts */
|
||||
|
||||
case UART_IIR_INTID_RLS:
|
||||
{
|
||||
/* Read the line status register (LSR) to clear */
|
||||
|
||||
status = u16550_serialin(priv, UART_LSR_OFFSET);
|
||||
sinfo("LSR: %02"PRIx32"\n", status);
|
||||
break;
|
||||
}
|
||||
|
||||
/* There should be no other values */
|
||||
|
||||
default:
|
||||
{
|
||||
serr("ERROR: Unexpected IIR: %02"PRIx32"\n", status);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: u16550_ioctl
|
||||
*
|
||||
@ -1105,7 +1035,7 @@ static int u16550_ioctl(struct file *filep, int cmd, unsigned long arg)
|
||||
int ret;
|
||||
|
||||
#ifdef CONFIG_SERIAL_UART_ARCH_IOCTL
|
||||
ret = uart_ioctl(filep, cmd, arg);
|
||||
ret = priv->ops->ioctl(priv, cmd, arg);
|
||||
|
||||
if (ret != -ENOTTY)
|
||||
{
|
||||
@ -1538,7 +1468,7 @@ static void u16550_dmarxfree(FAR struct uart_dev_s *dev)
|
||||
|
||||
if (priv->chanrx == NULL)
|
||||
{
|
||||
priv->chanrx = uart_dmachan(priv->uartbase, priv->dmarx);
|
||||
priv->chanrx = priv->ops->dmachan(priv, priv->dmarx)
|
||||
if (priv->chanrx == NULL)
|
||||
{
|
||||
return; /* Fail to get DMA channel */
|
||||
@ -1589,7 +1519,7 @@ static void u16550_dmatxavail(FAR struct uart_dev_s *dev)
|
||||
|
||||
if (priv->chantx == NULL)
|
||||
{
|
||||
priv->chantx = uart_dmachan(priv->uartbase, priv->dmatx);
|
||||
priv->chantx = priv->ops->dmachan(priv, priv->dmatx);
|
||||
if (priv->chantx == NULL)
|
||||
{
|
||||
return; /* Fail to get DMA channel */
|
||||
@ -1692,22 +1622,6 @@ static bool u16550_txempty(struct uart_dev_s *dev)
|
||||
return ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_TEMT) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: u16550_putc
|
||||
*
|
||||
* Description:
|
||||
* Write one character to the UART (polled)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef HAVE_16550_CONSOLE
|
||||
static void u16550_putc(FAR struct u16550_s *priv, int ch)
|
||||
{
|
||||
while ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
|
||||
u16550_serialout(priv, UART_THR_OFFSET, (uart_datawidth_t)ch);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
@ -1769,7 +1683,7 @@ void u16550_serialinit(void)
|
||||
* Name: up_putc
|
||||
*
|
||||
* Description:
|
||||
* Provide priority, low-level access to support OS debug writes
|
||||
* Provide priority, low-level access to support OS debug writes
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
@ -1793,4 +1707,145 @@ int up_putc(int ch)
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: u16550_bind
|
||||
*
|
||||
* Description:
|
||||
* Bind 16550 compatible device with this driver.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int u16550_bind(FAR uart_dev_t *dev)
|
||||
{
|
||||
dev->ops = &g_uart_ops;
|
||||
|
||||
#ifdef CONFIG_16550_PCI_CONSOLE
|
||||
if (dev->isconsole)
|
||||
{
|
||||
/* Setup console device */
|
||||
|
||||
u16550_setup(dev);
|
||||
}
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: u16550_interrupt
|
||||
*
|
||||
* Description:
|
||||
* This is the UART interrupt handler. It will be invoked when an
|
||||
* interrupt is received on the 'irq'. It should call uart_xmitchars or
|
||||
* uart_recvchars to perform the appropriate data transfers. The
|
||||
* interrupt handling logic must be able to map the 'arg' to the
|
||||
* appropriate uart_dev_s structure in order to call these functions.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int u16550_interrupt(int irq, FAR void *context, FAR void *arg)
|
||||
{
|
||||
FAR struct uart_dev_s *dev = (struct uart_dev_s *)arg;
|
||||
FAR struct u16550_s *priv;
|
||||
uint32_t status;
|
||||
int passes;
|
||||
|
||||
DEBUGASSERT(dev != NULL && dev->priv != NULL);
|
||||
priv = (FAR struct u16550_s *)dev->priv;
|
||||
|
||||
/* Loop until there are no characters to be transferred or,
|
||||
* until we have been looping for a long time.
|
||||
*/
|
||||
|
||||
for (passes = 0; passes < 256; passes++)
|
||||
{
|
||||
/* Get the current UART status and check for loop
|
||||
* termination conditions
|
||||
*/
|
||||
|
||||
status = u16550_serialin(priv, UART_IIR_OFFSET);
|
||||
|
||||
/* The UART_IIR_INTSTATUS bit should be zero if there are pending
|
||||
* interrupts
|
||||
*/
|
||||
|
||||
if ((status & UART_IIR_INTSTATUS) != 0)
|
||||
{
|
||||
/* Break out of the loop when there is no longer a
|
||||
* pending interrupt
|
||||
*/
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
/* Handle the interrupt by its interrupt ID field */
|
||||
|
||||
switch (status & UART_IIR_INTID_MASK)
|
||||
{
|
||||
/* Handle incoming, receive bytes (with or without timeout) */
|
||||
|
||||
case UART_IIR_INTID_RDA:
|
||||
case UART_IIR_INTID_CTI:
|
||||
{
|
||||
uart_recvchars(dev);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Handle outgoing, transmit bytes */
|
||||
|
||||
case UART_IIR_INTID_THRE:
|
||||
{
|
||||
uart_xmitchars(dev);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Just clear modem status interrupts (UART1 only) */
|
||||
|
||||
case UART_IIR_INTID_MSI:
|
||||
{
|
||||
/* Read the modem status register (MSR) to clear */
|
||||
|
||||
status = u16550_serialin(priv, UART_MSR_OFFSET);
|
||||
sinfo("MSR: %02"PRIx32"\n", status);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Just clear any line status interrupts */
|
||||
|
||||
case UART_IIR_INTID_RLS:
|
||||
{
|
||||
/* Read the line status register (LSR) to clear */
|
||||
|
||||
status = u16550_serialin(priv, UART_LSR_OFFSET);
|
||||
sinfo("LSR: %02"PRIx32"\n", status);
|
||||
break;
|
||||
}
|
||||
|
||||
/* There should be no other values */
|
||||
|
||||
default:
|
||||
{
|
||||
serr("ERROR: Unexpected IIR: %02"PRIx32"\n", status);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: u16550_putc
|
||||
*
|
||||
* Description:
|
||||
* Write one character to the UART (polled)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void u16550_putc(FAR struct u16550_s *priv, int ch)
|
||||
{
|
||||
while ((u16550_serialin(priv, UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
|
||||
u16550_serialout(priv, UART_THR_OFFSET, (uart_datawidth_t)ch);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_16550_UART */
|
||||
|
||||
@ -27,7 +27,8 @@
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <nuttx/serial/serial.h>
|
||||
|
||||
#ifdef CONFIG_16550_UART
|
||||
|
||||
@ -37,12 +38,10 @@
|
||||
|
||||
/* CONFIGURATION ************************************************************/
|
||||
|
||||
/* Are any UARTs enabled? */
|
||||
|
||||
#undef HAVE_UART
|
||||
#if defined(CONFIG_16550_UART0) || defined(CONFIG_16550_UART1) || \
|
||||
defined(CONFIG_16550_UART2) || defined(CONFIG_16550_UART3)
|
||||
# define HAVE_UART 1
|
||||
#undef HAVE_16550_UART_DMA
|
||||
#if defined(CONFIG_16550_UART0_DMA) || defined(CONFIG_16550_UART1_DMA) || \
|
||||
defined(CONFIG_16550_UART2_DMA) || defined(CONFIG_16550_UART3_DMA)
|
||||
# define HAVE_16550_UART_DMA 1
|
||||
#endif
|
||||
|
||||
/* We need to be told the address increment between registers and the
|
||||
@ -173,33 +172,20 @@
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define UART_RBR_INCR 0 /* (DLAB =0) Receiver Buffer Register */
|
||||
#define UART_THR_INCR 0 /* (DLAB =0) Transmit Holding Register */
|
||||
#define UART_DLL_INCR 0 /* (DLAB =1) Divisor Latch LSB */
|
||||
#define UART_DLM_INCR 1 /* (DLAB =1) Divisor Latch MSB */
|
||||
#define UART_IER_INCR 1 /* (DLAB =0) Interrupt Enable Register */
|
||||
#define UART_IIR_INCR 2 /* Interrupt ID Register */
|
||||
#define UART_FCR_INCR 2 /* FIFO Control Register */
|
||||
#define UART_LCR_INCR 3 /* Line Control Register */
|
||||
#define UART_MCR_INCR 4 /* Modem Control Register */
|
||||
#define UART_LSR_INCR 5 /* Line Status Register */
|
||||
#define UART_MSR_INCR 6 /* Modem Status Register */
|
||||
#define UART_SCR_INCR 7 /* Scratch Pad Register */
|
||||
#define UART_USR_INCR 31 /* UART Status Register */
|
||||
|
||||
#define UART_RBR_OFFSET (CONFIG_16550_REGINCR*UART_RBR_INCR)
|
||||
#define UART_THR_OFFSET (CONFIG_16550_REGINCR*UART_THR_INCR)
|
||||
#define UART_DLL_OFFSET (CONFIG_16550_REGINCR*UART_DLL_INCR)
|
||||
#define UART_DLM_OFFSET (CONFIG_16550_REGINCR*UART_DLM_INCR)
|
||||
#define UART_IER_OFFSET (CONFIG_16550_REGINCR*UART_IER_INCR)
|
||||
#define UART_IIR_OFFSET (CONFIG_16550_REGINCR*UART_IIR_INCR)
|
||||
#define UART_FCR_OFFSET (CONFIG_16550_REGINCR*UART_FCR_INCR)
|
||||
#define UART_LCR_OFFSET (CONFIG_16550_REGINCR*UART_LCR_INCR)
|
||||
#define UART_MCR_OFFSET (CONFIG_16550_REGINCR*UART_MCR_INCR)
|
||||
#define UART_LSR_OFFSET (CONFIG_16550_REGINCR*UART_LSR_INCR)
|
||||
#define UART_MSR_OFFSET (CONFIG_16550_REGINCR*UART_MSR_INCR)
|
||||
#define UART_SCR_OFFSET (CONFIG_16550_REGINCR*UART_SCR_INCR)
|
||||
#define UART_USR_OFFSET (CONFIG_16550_REGINCR*UART_USR_INCR)
|
||||
#define UART_RBR_OFFSET 0 /* (DLAB =0) Receiver Buffer Register */
|
||||
#define UART_THR_OFFSET 0 /* (DLAB =0) Transmit Holding Register */
|
||||
#define UART_DLL_OFFSET 0 /* (DLAB =1) Divisor Latch LSB */
|
||||
#define UART_DLM_OFFSET 1 /* (DLAB =1) Divisor Latch MSB */
|
||||
#define UART_IER_OFFSET 1 /* (DLAB =0) Interrupt Enable Register */
|
||||
#define UART_IIR_OFFSET 2 /* Interrupt ID Register */
|
||||
#define UART_FCR_OFFSET 2 /* FIFO Control Register */
|
||||
#define UART_LCR_OFFSET 3 /* Line Control Register */
|
||||
#define UART_MCR_OFFSET 4 /* Modem Control Register */
|
||||
#define UART_LSR_OFFSET 5 /* Line Status Register */
|
||||
#define UART_MSR_OFFSET 6 /* Modem Status Register */
|
||||
#define UART_SCR_OFFSET 7 /* Scratch Pad Register */
|
||||
#define UART_USR_OFFSET 31 /* UART Status Register */
|
||||
#define UART_DLF_OFFSET 48 /* Divisor Latch Fraction Register */
|
||||
|
||||
/* Register bit definitions *************************************************/
|
||||
|
||||
@ -333,6 +319,64 @@ typedef uint64_t uart_addrwidth_t;
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/* UART 16550 ops */
|
||||
|
||||
struct u16550_s;
|
||||
struct u16550_ops_s
|
||||
{
|
||||
CODE int (*isr)(int irq, FAR void *context, FAR void *arg);
|
||||
CODE uart_datawidth_t (*getreg)(FAR struct u16550_s *priv,
|
||||
unsigned int offset);
|
||||
CODE void (*putreg)(FAR struct u16550_s *priv,
|
||||
unsigned int offset,
|
||||
uart_datawidth_t value);
|
||||
CODE int (*ioctl)(FAR struct u16550_s *priv, int cmd, unsigned long arg);
|
||||
CODE FAR struct dma_chan_s *(*dmachan)(FAR struct u16550_s *priv,
|
||||
unsigned int ident);
|
||||
};
|
||||
|
||||
/* UART 16550 private data */
|
||||
|
||||
struct u16550_s
|
||||
{
|
||||
/* UART 16550 operations */
|
||||
|
||||
FAR const struct u16550_ops_s *ops;
|
||||
|
||||
uart_addrwidth_t uartbase; /* Base address of UART registers */
|
||||
uint8_t regincr;
|
||||
#ifdef HAVE_16550_UART_DMA
|
||||
int32_t dmatx;
|
||||
FAR struct dma_chan_s *chantx;
|
||||
int32_t dmarx;
|
||||
FAR struct dma_chan_s *chanrx;
|
||||
FAR char *dmarxbuf;
|
||||
size_t dmarxsize;
|
||||
volatile size_t dmarxhead;
|
||||
volatile size_t dmarxtail;
|
||||
int32_t dmarxtimeout;
|
||||
#endif
|
||||
#if !defined(CONFIG_16550_SUPRESS_CONFIG) || defined(HAVE_16550_UART_DMA)
|
||||
uint32_t baud; /* Configured baud */
|
||||
uint32_t uartclk; /* UART clock frequency */
|
||||
#endif
|
||||
#ifdef CONFIG_CLK
|
||||
FAR const char *clk_name; /* UART clock name */
|
||||
FAR struct clk_s *mclk; /* UART clock descriptor */
|
||||
#endif
|
||||
uart_datawidth_t ier; /* Saved IER value */
|
||||
int irq; /* IRQ associated with this UART */
|
||||
#ifndef CONFIG_16550_SUPRESS_CONFIG
|
||||
uint8_t parity; /* 0=none, 1=odd, 2=even */
|
||||
uint8_t bits; /* Number of bits (7 or 8) */
|
||||
bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
|
||||
#if defined(CONFIG_SERIAL_IFLOWCONTROL) || defined(CONFIG_SERIAL_OFLOWCONTROL)
|
||||
bool flow; /* flow control (RTS/CTS) enabled */
|
||||
#endif
|
||||
#endif
|
||||
uart_datawidth_t rxtrigger; /* RX trigger level */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions Definitions
|
||||
****************************************************************************/
|
||||
@ -363,6 +407,36 @@ void u16550_earlyserialinit(void);
|
||||
|
||||
void u16550_serialinit(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: u16550_bind
|
||||
*
|
||||
* Description:
|
||||
* Bind 16550 compatible device with this driver.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int u16550_bind(FAR uart_dev_t *dev);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: u16550_interrupt
|
||||
*
|
||||
* Description:
|
||||
* Handle UART 16550 interrupt.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int u16550_interrupt(int irq, FAR void *context, FAR void *arg);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: u16550_putc
|
||||
*
|
||||
* Description:
|
||||
* Write one character to the UART (polled)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void u16550_putc(FAR struct u16550_s *priv, int ch);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: uart_getreg(), uart_putreg(), uart_ioctl()
|
||||
*
|
||||
@ -374,17 +448,16 @@ void u16550_serialinit(void);
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_SERIAL_UART_ARCH_MMIO
|
||||
uart_datawidth_t uart_getreg(uart_addrwidth_t base, unsigned int offset);
|
||||
void uart_putreg(uart_addrwidth_t base,
|
||||
uart_datawidth_t uart_getreg(FAR struct u16550_s *priv, unsigned int offset);
|
||||
void uart_putreg(FAR struct u16550_s *priv,
|
||||
unsigned int offset,
|
||||
uart_datawidth_t value);
|
||||
#endif
|
||||
|
||||
struct file; /* Forward reference */
|
||||
int uart_ioctl(struct file *filep, int cmd, unsigned long arg);
|
||||
int uart_ioctl(FAR struct u16550_s *priv, int cmd, unsigned long arg);
|
||||
|
||||
struct dma_chan_s;
|
||||
FAR struct dma_chan_s *uart_dmachan(uart_addrwidth_t base,
|
||||
FAR struct dma_chan_s *uart_dmachan(FAR struct u16550_s *priv,
|
||||
unsigned int ident);
|
||||
|
||||
#endif /* CONFIG_16550_UART */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user