sergiotarxz/nuttx
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Cosmetic update to comments and README files

Browse Source
This commit is contained in:
Gregory Nutt 2014-03-31 17:25:39 -06:00
parent 4a37d6b042
commit cec5d575c0
2 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
arch/arm/src/sama5/Kconfig
View File

@ -108,15 +108,15 @@ endchoice # Atmel AT91SAMA5 Chip Selection
menu "SAMA5 Peripheral Support" menu "SAMA5 Peripheral Support"
config SAMA5_DBGU config SAMA5_DBGU
bool "Debug Unit Interrupt (DBGU)" bool "Debug Unit (DBGU)"
default n default n
config SAMA5_PIT config SAMA5_PIT
bool "Periodic Interval Timer Interrupt (PIT)" bool "Periodic Interval Timer (PIT)"
default n default n
config SAMA5_WDT config SAMA5_WDT
bool "Watchdog timer Interrupt (WDT)" bool "Watchdog timer (WDT)"
default n default n
select WATCHDOG select WATCHDOG

14
arch/arm/src/sama5/chip/sam_uart.h
View File

@ -1,9 +1,9 @@
/************************************************************************************************ /************************************************************************************************
* arch/arm/src/sam34/chip/sam3u_uart.h * arch/arm/src/sama5/chip/sam3u_uart.h
* Universal Asynchronous Receiver Transmitter (UART) and Universal Synchronous Asynchronous * Universal Asynchronous Receiver Transmitter (UART) and Universal Synchronous Asynchronous
* Receiver Transmitter (USART) definitions for the SAM3U, SAM3X, SAM3A and SAM4S * Receiver Transmitter (USART) definitions for the SAMA5D3
* *
* Copyright (C) 2009, 2013 Gregory Nutt. All rights reserved. * Copyright (C) 2013 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org> * Author: Gregory Nutt <gnutt@nuttx.org>
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
@ -35,8 +35,8 @@
* *
************************************************************************************************/ ************************************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H #ifndef __ARCH_ARM_SRC_SAMA5_CHIP_SAM_UART_H
#define __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H #define __ARCH_ARM_SRC_SAMA5_CHIP_SAM_UART_H
/************************************************************************************************ /************************************************************************************************
* Included Files * Included Files
@ -200,7 +200,7 @@
#define UART_CR_RSTSTA (1 << 8) /* Bit 8: Reset Status Bits (Common) */ #define UART_CR_RSTSTA (1 << 8) /* Bit 8: Reset Status Bits (Common) */
#define UART_CR_STTBRK (1 << 9) /* Bit 9: Start Break (USART UART mode only) */ #define UART_CR_STTBRK (1 << 9) /* Bit 9: Start Break (USART UART mode only) */
#define UART_CR_STPBRK (1 << 10) /* Bit 10: Stop Break (USART UART mode only) */ #define UART_CR_STPBRK (1 << 10) /* Bit 10: Stop Break (USART UART mode only) */
#define UART_CR_STTTO (1 << 11) /* Bit 11: Start Time-out (USART oUART mode nly) */ #define UART_CR_STTTO (1 << 11) /* Bit 11: Start Time-out (USART UART mode only) */
#define UART_CR_SENDA (1 << 12) /* Bit 12: Send Address (USART UART mode only) */ #define UART_CR_SENDA (1 << 12) /* Bit 12: Send Address (USART UART mode only) */
#define UART_CR_RSTIT (1 << 13) /* Bit 13: Reset Iterations (USART UART mode only) */ #define UART_CR_RSTIT (1 << 13) /* Bit 13: Reset Iterations (USART UART mode only) */
#define UART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge (USART UART mode only) */ #define UART_CR_RSTNACK (1 << 14) /* Bit 14: Reset Non Acknowledge (USART UART mode only) */
@ -407,4 +407,4 @@
* Public Functions * Public Functions
************************************************************************************************/ ************************************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_CHIP_SAM3U_UART_H */ #endif /* __ARCH_ARM_SRC_SAMA5_CHIP_SAM_UART_H */