Cosmetic updates to some comments

This commit is contained in:
Gregory Nutt 2018-09-01 07:50:10 -06:00
parent 93c23a2c03
commit cecff14e34
3 changed files with 12 additions and 3 deletions

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@ -148,7 +148,6 @@
#define BOARD_GCLK_SET2 0x0fdf /* Post-configure: All GCLKs except GCLK5 */
#define BOARD_GCLK0_ENABLE TRUE /* Enable GCLK0 */
#define BOARD_GCLK0_IDC FALSE /* Don't improve duty cycle */
#define BOARD_GCLK0_OOV FALSE /* Clock output will be LOW */
#define BOARD_GCLK0_OE TRUE /* Generate output on GCLK_IO */
#define BOARD_GCLK0_DIVSEL 0 /* GCLK frequency is source/DIV */
@ -403,7 +402,7 @@
* before using the SERCOM.
*/
#define BOARD_SERCOM_SLOWGEN 3 /* 48MHz, common to all SERCOMS */
#define BOARD_SERCOM_SLOWGEN 3 /* 32.768KHz, common to all SERCOMS */
#define BOARD_SERCOM_SLOWLOCK FALSE /* Don't lock the SLOWCLOCK */
#define BOARD_SLOWCLOCK_FREQUENCY BOARD_GCLK3_FREQUENCY

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@ -374,6 +374,16 @@ Configuration sub-directories
The <subdir> that is provided above as an argument to the tools/configure.sh
must be is one of the following.
dhtxx:
Configuration added by Abdelatif Guettouche for testing the the DHTxx
sensor. This configuration expects this setup:
DHTXX_PIN_OUTPUT PG9
DHTXX_PIN_INPUT PG9
The STM32 free-running timer is also required.
kelf:
This is a protected mode version of the apps/examples/elf test of

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@ -169,7 +169,7 @@
#define GPIO_BTN_DOWN (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTG|GPIO_PIN8)
#define GPIO_BTN_CENTER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTG|GPIO_PIN15)
/* DHTxx confing pin. */
/* DHTxx pin configuration */
#define GPIO_DHTXX_PIN (GPIO_PORTG|GPIO_PIN9)
#define GPIO_DHTXX_PIN_OUTPUT (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_DHTXX_PIN)