Cosmetic updates to some comments
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@ -148,7 +148,6 @@
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#define BOARD_GCLK_SET2 0x0fdf /* Post-configure: All GCLKs except GCLK5 */
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#define BOARD_GCLK0_ENABLE TRUE /* Enable GCLK0 */
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#define BOARD_GCLK0_IDC FALSE /* Don't improve duty cycle */
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#define BOARD_GCLK0_OOV FALSE /* Clock output will be LOW */
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#define BOARD_GCLK0_OE TRUE /* Generate output on GCLK_IO */
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#define BOARD_GCLK0_DIVSEL 0 /* GCLK frequency is source/DIV */
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@ -403,7 +402,7 @@
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* before using the SERCOM.
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*/
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#define BOARD_SERCOM_SLOWGEN 3 /* 48MHz, common to all SERCOMS */
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#define BOARD_SERCOM_SLOWGEN 3 /* 32.768KHz, common to all SERCOMS */
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#define BOARD_SERCOM_SLOWLOCK FALSE /* Don't lock the SLOWCLOCK */
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#define BOARD_SLOWCLOCK_FREQUENCY BOARD_GCLK3_FREQUENCY
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@ -374,6 +374,16 @@ Configuration sub-directories
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The <subdir> that is provided above as an argument to the tools/configure.sh
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must be is one of the following.
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dhtxx:
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Configuration added by Abdelatif Guettouche for testing the the DHTxx
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sensor. This configuration expects this setup:
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DHTXX_PIN_OUTPUT PG9
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DHTXX_PIN_INPUT PG9
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The STM32 free-running timer is also required.
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kelf:
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This is a protected mode version of the apps/examples/elf test of
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@ -169,7 +169,7 @@
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#define GPIO_BTN_DOWN (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTG|GPIO_PIN8)
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#define GPIO_BTN_CENTER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTG|GPIO_PIN15)
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/* DHTxx confing pin. */
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/* DHTxx pin configuration */
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#define GPIO_DHTXX_PIN (GPIO_PORTG|GPIO_PIN9)
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#define GPIO_DHTXX_PIN_OUTPUT (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_DHTXX_PIN)
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