arch/arm/src/stm32/stm32_foc.c: add modifications to support STM32F1
- generalize DBGMCU for PWM timer - use ADC common data only if coupled ADC present - rename some ADC definitions that collide with stm32_adc.h
This commit is contained in:
raiden00pl
Xiang Xiao
parent
021a89569d
commit
cf645fc9ba
@ -106,12 +106,6 @@
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# error Not supported ADC IP core
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#endif
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/* Should works for ADC IPv1 basic but was not tested yet */
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#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && defined(HAVE_BASIC_ADC)
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# error Not tested yet
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#endif
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/* Multi instances support tested only on IP_ADC_V1 */
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#if CONFIG_MOTOR_FOC_INST > 1
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@ -141,13 +135,25 @@
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# error ADC sample-time configuration interface must be enabled
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#endif
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/* Debug register for PWM timers */
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#if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2)
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# define FOC_PWM_FZ_REG (STM32_DBGMCU_APB2_FZ)
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#elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1)
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# define FOC_PWM_FZ_REG (STM32_DBGMCU_CR)
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#endif
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/* FOC0 always use TIMER1 for PWM */
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#ifdef CONFIG_STM32_FOC_FOC0
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# define FOC0_PWM (1)
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# define FOC0_PWM_NCHANNELS (PWM_TIM1_NCHANNELS)
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# define FOC0_PWM_BASE (STM32_TIM1_BASE)
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# define FOC0_PWM_APB2FZ (DBGMCU_APB2_TIM1STOP)
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# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2)
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# define FOC0_PWM_FZ_BIT (DBGMCU_APB2_TIM1STOP)
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# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1)
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# define FOC0_PWM_FZ_BIT (DBGMCU_CR_TIM1STOP)
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# endif
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# if CONFIG_STM32_TIM1_MODE != 2
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# error TIM1 must be configured in center-aligned mode 1
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# endif
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@ -159,7 +165,11 @@
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# define FOC1_PWM (8)
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# define FOC1_PWM_NCHANNELS (PWM_TIM8_NCHANNELS)
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# define FOC1_PWM_BASE (STM32_TIM8_BASE)
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# define FOC1_PWM_APB2FZ (DBGMCU_APB2_TIM8STOP)
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# if defined(CONFIG_STM32_HAVE_IP_DBGMCU_V2)
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# define FOC1_PWM_FZ_BIT (DBGMCU_APB2_TIM8STOP)
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# elif defined(CONFIG_STM32_HAVE_IP_DBGMCU_V1)
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# define FOC1_PWM_FZ_BIT (DBGMCU_CR_TIM8STOP)
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# endif
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# if CONFIG_STM32_TIM8_MODE != 2
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# error TIM8 must be configured in center-aligned mode 1
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# endif
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@ -438,13 +448,13 @@
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/* Generalize ADC interupt flags */
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#if defined(CONFIG_STM32_HAVE_IP_ADC_V2)
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# define ADC_ISR_FOC ADC_ISR_JEOS
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# define ADC_IER_FOC ADC_IER_JEOS
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# define ADC_ISR_OVR ADC_INT_OVR
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# define FOC_ADC_ISR_FOC ADC_ISR_JEOS
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# define FOC_ADC_IER_FOC ADC_IER_JEOS
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# define FOC_ADC_ISR_OVR ADC_INT_OVR
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#elif defined(CONFIG_STM32_HAVE_IP_ADC_V1)
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# define ADC_ISR_FOC ADC_ISR_JEOC
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# define ADC_IER_FOC ADC_IER_JEOC
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# define ADC_ISR_OVR ADC_SR_OVR
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# define FOC_ADC_ISR_FOC ADC_ISR_JEOC
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# define FOC_ADC_IER_FOC ADC_IER_JEOC
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# define FOC_ADC_ISR_OVR ADC_SR_OVR
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#else
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# error Not supported
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#endif
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@ -483,6 +493,7 @@
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/* Common for ADCv1 */
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#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && !defined(HAVE_BASIC_ADC)
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# define FOC_ADC_HAVE_CMN (1)
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# ifdef CONFIG_STM32_HAVE_ADC1
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# define FOC_ADC1_CMN (&g_stm32_foc_adccmn123)
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# endif
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@ -497,12 +508,22 @@
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/* Common for ADCv1 basic */
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#if defined(CONFIG_STM32_HAVE_IP_ADC_V1) && defined(HAVE_BASIC_ADC)
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# error ADCv1 basic not supported by this implementation
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# undef FOC_ADC_HAVE_CMN
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# ifdef CONFIG_STM32_HAVE_ADC1
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# define FOC_ADC1_CMN (0)
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# endif
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# ifdef CONFIG_STM32_HAVE_ADC2
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# define FOC_ADC2_CMN (0)
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# endif
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# ifdef CONFIG_STM32_HAVE_ADC3
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# define FOC_ADC3_CMN (0)
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# endif
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#endif
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/* Common for ADCv2 */
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#ifdef CONFIG_STM32_HAVE_IP_ADC_V2
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# define FOC_ADC_HAVE_CMN (1)
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# ifdef CONFIG_STM32_HAVE_ADC1
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# define FOC_ADC1_CMN (&g_stm32_foc_adccmn12)
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# endif
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@ -594,8 +615,8 @@
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/* Enable/disable ADC interrupts (FOC worker loop) */
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#define STM32_ADC_ENABLEINT(adc) STM32_ADC_INT_ENABLE(adc, ADC_IER_FOC)
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#define STM32_ADC_DISABLEINT(adc) STM32_ADC_INT_DISABLE(adc, ADC_IER_FOC)
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#define STM32_ADC_ENABLEINT(adc) STM32_ADC_INT_ENABLE(adc, FOC_ADC_IER_FOC)
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#define STM32_ADC_DISABLEINT(adc) STM32_ADC_INT_DISABLE(adc, FOC_ADC_IER_FOC)
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/* ADC calibration samples */
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@ -687,9 +708,11 @@ struct stm32_foc_priv_s
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FAR const struct foc_callbacks_s *cb;
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#ifdef FOC_ADC_HAVE_CMN
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/* Common data */
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FAR struct stm32_foc_adccmn_s *adc_cmn;
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#endif
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};
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/****************************************************************************
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@ -747,33 +770,35 @@ static void stm32_foc_hw_config_get(FAR struct foc_dev_s *dev);
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* Private Data
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****************************************************************************/
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#ifdef CONFIG_STM32_HAVE_IP_ADC_V1
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#ifdef FOC_ADC_HAVE_CMN
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# ifdef CONFIG_STM32_HAVE_IP_ADC_V1
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/* Common for ADC123 */
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static struct stm32_foc_adccmn_s g_stm32_foc_adccmn123 =
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{
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.cntr = 0
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};
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#endif
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# endif /* CONFIG_STM32_HAVE_IP_ADC_V1 */
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#ifdef CONFIG_STM32_HAVE_IP_ADC_V2
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# if defined(CONFIG_STM32_HAVE_ADC1) || defined(CONFIG_STM32_HAVE_ADC2)
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# ifdef CONFIG_STM32_HAVE_IP_ADC_V2
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# if defined(CONFIG_STM32_HAVE_ADC1) || defined(CONFIG_STM32_HAVE_ADC2)
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/* Common for ADC12 */
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static struct stm32_foc_adccmn_s g_stm32_foc_adccmn12 =
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{
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.cntr = 0
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};
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# endif
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# if defined(CONFIG_STM32_HAVE_ADC3) || defined(CONFIG_STM32_HAVE_ADC4)
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# endif /* CONFIG_STM32_HAVE_ADC1 || CONFIG_STM32_HAVE_ADC2 */
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# if defined(CONFIG_STM32_HAVE_ADC3) || defined(CONFIG_STM32_HAVE_ADC4)
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/* Common for ADC34 */
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static struct stm32_foc_adccmn_s g_stm32_foc_adccmn34 =
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{
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.cntr = 0
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};
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# endif
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#endif
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# endif /* CONFIG_STM32_HAVE_ADC3 || CONFIG_STM32_HAVE_ADC4 */
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# endif /* CONFIG_STM32_HAVE_IP_ADC_V2 */
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#endif /* FOC_ADC_HAVE_CMN */
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/* STM32 specific FOC data */
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@ -1256,7 +1281,9 @@ static int stm32_foc_setup(FAR struct foc_dev_s *dev)
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DEBUGASSERT(board);
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DEBUGASSERT(priv);
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DEBUGASSERT(adc);
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#ifdef FOC_ADC_HAVE_CMN
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DEBUGASSERT(priv->adc_cmn);
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#endif
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/* Call board-specific setup - must be done before TIM enable */
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@ -1271,6 +1298,7 @@ static int stm32_foc_setup(FAR struct foc_dev_s *dev)
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STM32_ADC_SETUP(foc_dev->adc);
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#ifdef FOC_ADC_HAVE_CMN
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/* Lock ADC common data */
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ret = nxsem_wait_uninterruptible(&priv->adc_cmn->sem);
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@ -1295,6 +1323,7 @@ static int stm32_foc_setup(FAR struct foc_dev_s *dev)
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/* Unlock ADC common data */
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nxsem_post(&priv->adc_cmn->sem);
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#endif
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/* Setup PWM */
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@ -1403,6 +1432,7 @@ static int stm32_foc_shutdown(FAR struct foc_dev_s *dev)
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STM32_ADC_SHUTDOWN(foc_dev->adc);
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#ifdef FOC_ADC_HAVE_CMN
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/* Lock ADC common data */
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ret = nxsem_wait_uninterruptible(&priv->adc_cmn->sem);
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@ -1418,15 +1448,18 @@ static int stm32_foc_shutdown(FAR struct foc_dev_s *dev)
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/* Deinitialize ADC only if last device */
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if (priv->adc_cmn->cntr == 0)
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#endif
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{
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/* Disable ADC interrupts */
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up_disable_irq(foc_dev->adc_irq);
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}
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#ifdef FOC_ADC_HAVE_CMN
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/* Unlock ADC common data */
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nxsem_post(&priv->adc_cmn->sem);
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#endif
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/* Call board-specific shutdown */
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@ -1436,7 +1469,9 @@ static int stm32_foc_shutdown(FAR struct foc_dev_s *dev)
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memset(&priv->data, 0, sizeof(struct stm32_foc_data_s));
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#ifdef FOC_ADC_HAVE_CMN
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errout:
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#endif
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return ret;
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}
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@ -1557,7 +1592,7 @@ static int stm32_foc_adc_handler(int irq, FAR void *context, FAR void *arg)
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/* Only if end of injected sequence */
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if (pending & ADC_ISR_FOC)
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if (pending & FOC_ADC_ISR_FOC)
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{
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/* Found device with penidng ADC interrupt */
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@ -2049,13 +2084,15 @@ stm32_foc_initialize(int inst, FAR struct stm32_foc_board_s *board)
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FAR struct foc_lower_s *foc_lower = NULL;
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FAR struct stm32_foc_dev_s *foc_dev = NULL;
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FAR struct stm32_foc_priv_s *foc_priv = NULL;
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#ifdef FOC_ADC_HAVE_CMN
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FAR struct stm32_foc_adccmn_s *adc_cmn = NULL;
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#endif
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uint32_t adc_irq = 0;
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uint32_t pwm_base = 0;
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uint32_t jextval = 0;
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uint8_t pwm_inst = 0;
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uint8_t adc_inst = 0;
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uint32_t apb2_fz = 0;
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uint32_t pwmfzbit = 0;
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int j = 0;
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DEBUGASSERT(board != NULL);
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@ -2092,8 +2129,10 @@ stm32_foc_initialize(int inst, FAR struct stm32_foc_board_s *board)
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adc_irq = FOC0_ADC_IRQ;
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pwm_base = FOC0_PWM_BASE;
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jextval = FOC0_ADC_JEXT;
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apb2_fz = FOC0_PWM_APB2FZ;
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pwmfzbit = FOC0_PWM_FZ_BIT;
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#ifdef FOC_ADC_HAVE_CMN
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adc_cmn = FOC0_ADC_CMN;
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#endif
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break;
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}
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#endif
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@ -2106,8 +2145,10 @@ stm32_foc_initialize(int inst, FAR struct stm32_foc_board_s *board)
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adc_irq = FOC1_ADC_IRQ;
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pwm_base = FOC1_PWM_BASE;
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jextval = FOC1_ADC_JEXT;
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apb2_fz = FOC1_PWM_APB2FZ;
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pwmfzbit = FOC1_PWM_FZ_BIT;
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#ifdef FOC_ADC_HAVE_CMN
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adc_cmn = FOC1_ADC_CMN;
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#endif
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break;
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}
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#endif
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@ -2142,9 +2183,11 @@ stm32_foc_initialize(int inst, FAR struct stm32_foc_board_s *board)
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foc_priv->board = board;
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#ifdef FOC_ADC_HAVE_CMN
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/* Connect ADC common data */
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foc_priv->adc_cmn = adc_cmn;
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#endif
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/* Get archspecific devive */
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@ -2210,11 +2253,13 @@ stm32_foc_initialize(int inst, FAR struct stm32_foc_board_s *board)
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* TODO: move this to stm32_pwm.c and configure from Kconfig
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*/
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modifyreg32(STM32_DBGMCU_APB2_FZ, 0, apb2_fz);
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modifyreg32(FOC_PWM_FZ_REG, 0, pwmfzbit);
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#ifdef FOC_ADC_HAVE_CMN
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/* Initialize ADC common data semaphore */
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nxsem_init(&foc_priv->adc_cmn->sem, 0, 1);
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#endif
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/* Initialize calibration semaphore */
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